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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/kernel.h>
0008 #include <linux/delay.h>
0009 #include <linux/errno.h>
0010 #include <linux/i2c.h>
0011 #include <linux/fs.h>
0012 #include <linux/io.h>
0013 #include <linux/types.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/jiffies.h>
0016 #include <linux/pci.h>
0017 #include <linux/mutex.h>
0018 #include <linux/ktime.h>
0019 #include <linux/slab.h>
0020 
0021 #define PCH_EVENT_SET   0   /* I2C Interrupt Event Set Status */
0022 #define PCH_EVENT_NONE  1   /* I2C Interrupt Event Clear Status */
0023 #define PCH_MAX_CLK     100000  /* Maximum Clock speed in MHz */
0024 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
0025 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
0026 
0027 #define PCH_I2CSADR 0x00    /* I2C slave address register */
0028 #define PCH_I2CCTL  0x04    /* I2C control register */
0029 #define PCH_I2CSR   0x08    /* I2C status register */
0030 #define PCH_I2CDR   0x0C    /* I2C data register */
0031 #define PCH_I2CMON  0x10    /* I2C bus monitor register */
0032 #define PCH_I2CBC   0x14    /* I2C bus transfer rate setup counter */
0033 #define PCH_I2CMOD  0x18    /* I2C mode register */
0034 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
0035 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
0036 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
0037 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
0038 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
0039 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
0040 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
0041 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
0042 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
0043 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
0044 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
0045 #define PCH_I2CTMR  0x48    /* I2C timer register */
0046 #define PCH_I2CSRST 0xFC    /* I2C reset register */
0047 #define PCH_I2CNF   0xF8    /* I2C noise filter register */
0048 
0049 #define BUS_IDLE_TIMEOUT    20
0050 #define PCH_I2CCTL_I2CMEN   0x0080
0051 #define TEN_BIT_ADDR_DEFAULT    0xF000
0052 #define TEN_BIT_ADDR_MASK   0xF0
0053 #define PCH_START       0x0020
0054 #define PCH_RESTART     0x0004
0055 #define PCH_ESR_START       0x0001
0056 #define PCH_BUFF_START      0x1
0057 #define PCH_REPSTART        0x0004
0058 #define PCH_ACK         0x0008
0059 #define PCH_GETACK      0x0001
0060 #define CLR_REG         0x0
0061 #define I2C_RD          0x1
0062 #define I2CMCF_BIT      0x0080
0063 #define I2CMIF_BIT      0x0002
0064 #define I2CMAL_BIT      0x0010
0065 #define I2CBMFI_BIT     0x0001
0066 #define I2CBMAL_BIT     0x0002
0067 #define I2CBMNA_BIT     0x0004
0068 #define I2CBMTO_BIT     0x0008
0069 #define I2CBMIS_BIT     0x0010
0070 #define I2CESRFI_BIT        0X0001
0071 #define I2CESRTO_BIT        0x0002
0072 #define I2CESRFIIE_BIT      0x1
0073 #define I2CESRTOIE_BIT      0x2
0074 #define I2CBMDZ_BIT     0x0040
0075 #define I2CBMAG_BIT     0x0020
0076 #define I2CMBB_BIT      0x0020
0077 #define BUFFER_MODE_MASK    (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
0078                 I2CBMTO_BIT | I2CBMIS_BIT)
0079 #define I2C_ADDR_MSK        0xFF
0080 #define I2C_MSB_2B_MSK      0x300
0081 #define FAST_MODE_CLK       400
0082 #define FAST_MODE_EN        0x0001
0083 #define SUB_ADDR_LEN_MAX    4
0084 #define BUF_LEN_MAX     32
0085 #define PCH_BUFFER_MODE     0x1
0086 #define EEPROM_SW_RST_MODE  0x0002
0087 #define NORMAL_INTR_ENBL    0x0300
0088 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
0089 #define EEPROM_RST_INTR_DISBL   0x0
0090 #define BUFFER_MODE_INTR_ENBL   0x001F
0091 #define BUFFER_MODE_INTR_DISBL  0x0
0092 #define NORMAL_MODE     0x0
0093 #define BUFFER_MODE     0x1
0094 #define EEPROM_SR_MODE      0x2
0095 #define I2C_TX_MODE     0x0010
0096 #define PCH_BUF_TX      0xFFF7
0097 #define PCH_BUF_RD      0x0008
0098 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
0099             I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
0100 #define I2CMAL_EVENT        0x0001
0101 #define I2CMCF_EVENT        0x0002
0102 #define I2CBMFI_EVENT       0x0004
0103 #define I2CBMAL_EVENT       0x0008
0104 #define I2CBMNA_EVENT       0x0010
0105 #define I2CBMTO_EVENT       0x0020
0106 #define I2CBMIS_EVENT       0x0040
0107 #define I2CESRFI_EVENT      0x0080
0108 #define I2CESRTO_EVENT      0x0100
0109 #define PCI_DEVICE_ID_PCH_I2C   0x8817
0110 
0111 #define pch_dbg(adap, fmt, arg...)  \
0112     dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
0113 
0114 #define pch_err(adap, fmt, arg...)  \
0115     dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
0116 
0117 #define pch_pci_err(pdev, fmt, arg...)  \
0118     dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
0119 
0120 #define pch_pci_dbg(pdev, fmt, arg...)  \
0121     dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
0122 
0123 /*
0124 Set the number of I2C instance max
0125 Intel EG20T PCH :       1ch
0126 LAPIS Semiconductor ML7213 IOH :    2ch
0127 LAPIS Semiconductor ML7831 IOH :    1ch
0128 */
0129 #define PCH_I2C_MAX_DEV         2
0130 
0131 /**
0132  * struct i2c_algo_pch_data - for I2C driver functionalities
0133  * @pch_adapter:        stores the reference to i2c_adapter structure
0134  * @p_adapter_info:     stores the reference to adapter_info structure
0135  * @pch_base_address:       specifies the remapped base address
0136  * @pch_buff_mode_en:       specifies if buffer mode is enabled
0137  * @pch_event_flag:     specifies occurrence of interrupt events
0138  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
0139  */
0140 struct i2c_algo_pch_data {
0141     struct i2c_adapter pch_adapter;
0142     struct adapter_info *p_adapter_info;
0143     void __iomem *pch_base_address;
0144     int pch_buff_mode_en;
0145     u32 pch_event_flag;
0146     bool pch_i2c_xfer_in_progress;
0147 };
0148 
0149 /**
0150  * struct adapter_info - This structure holds the adapter information for the
0151  *           PCH i2c controller
0152  * @pch_data:       stores a list of i2c_algo_pch_data
0153  * @pch_i2c_suspended:  specifies whether the system is suspended or not
0154  *          perhaps with more lines and words.
0155  * @ch_num:     specifies the number of i2c instance
0156  *
0157  * pch_data has as many elements as maximum I2C channels
0158  */
0159 struct adapter_info {
0160     struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
0161     bool pch_i2c_suspended;
0162     int ch_num;
0163 };
0164 
0165 
0166 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
0167 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
0168 static wait_queue_head_t pch_event;
0169 static DEFINE_MUTEX(pch_mutex);
0170 
0171 /* Definition for ML7213 by LAPIS Semiconductor */
0172 #define PCI_DEVICE_ID_ML7213_I2C    0x802D
0173 #define PCI_DEVICE_ID_ML7223_I2C    0x8010
0174 #define PCI_DEVICE_ID_ML7831_I2C    0x8817
0175 
0176 static const struct pci_device_id pch_pcidev_id[] = {
0177     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
0178     { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
0179     { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
0180     { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
0181     {0,}
0182 };
0183 MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
0184 
0185 static irqreturn_t pch_i2c_handler(int irq, void *pData);
0186 
0187 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
0188 {
0189     u32 val;
0190     val = ioread32(addr + offset);
0191     val |= bitmask;
0192     iowrite32(val, addr + offset);
0193 }
0194 
0195 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
0196 {
0197     u32 val;
0198     val = ioread32(addr + offset);
0199     val &= (~bitmask);
0200     iowrite32(val, addr + offset);
0201 }
0202 
0203 /**
0204  * pch_i2c_init() - hardware initialization of I2C module
0205  * @adap:   Pointer to struct i2c_algo_pch_data.
0206  */
0207 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
0208 {
0209     void __iomem *p = adap->pch_base_address;
0210     u32 pch_i2cbc;
0211     u32 pch_i2ctmr;
0212     u32 reg_value;
0213 
0214     /* reset I2C controller */
0215     iowrite32(0x01, p + PCH_I2CSRST);
0216     msleep(20);
0217     iowrite32(0x0, p + PCH_I2CSRST);
0218 
0219     /* Initialize I2C registers */
0220     iowrite32(0x21, p + PCH_I2CNF);
0221 
0222     pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
0223 
0224     if (pch_i2c_speed != 400)
0225         pch_i2c_speed = 100;
0226 
0227     reg_value = PCH_I2CCTL_I2CMEN;
0228     if (pch_i2c_speed == FAST_MODE_CLK) {
0229         reg_value |= FAST_MODE_EN;
0230         pch_dbg(adap, "Fast mode enabled\n");
0231     }
0232 
0233     if (pch_clk > PCH_MAX_CLK)
0234         pch_clk = 62500;
0235 
0236     pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
0237     /* Set transfer speed in I2CBC */
0238     iowrite32(pch_i2cbc, p + PCH_I2CBC);
0239 
0240     pch_i2ctmr = (pch_clk) / 8;
0241     iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
0242 
0243     reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
0244     iowrite32(reg_value, p + PCH_I2CCTL);
0245 
0246     pch_dbg(adap,
0247         "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
0248         ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
0249 
0250     init_waitqueue_head(&pch_event);
0251 }
0252 
0253 /**
0254  * pch_i2c_wait_for_bus_idle() - check the status of bus.
0255  * @adap:   Pointer to struct i2c_algo_pch_data.
0256  * @timeout:    waiting time counter (ms).
0257  */
0258 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
0259                      s32 timeout)
0260 {
0261     void __iomem *p = adap->pch_base_address;
0262     int schedule = 0;
0263     unsigned long end = jiffies + msecs_to_jiffies(timeout);
0264 
0265     while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
0266         if (time_after(jiffies, end)) {
0267             pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
0268             pch_err(adap, "%s: Timeout Error.return%d\n",
0269                     __func__, -ETIME);
0270             pch_i2c_init(adap);
0271 
0272             return -ETIME;
0273         }
0274 
0275         if (!schedule)
0276             /* Retry after some usecs */
0277             udelay(5);
0278         else
0279             /* Wait a bit more without consuming CPU */
0280             usleep_range(20, 1000);
0281 
0282         schedule = 1;
0283     }
0284 
0285     return 0;
0286 }
0287 
0288 /**
0289  * pch_i2c_start() - Generate I2C start condition in normal mode.
0290  * @adap:   Pointer to struct i2c_algo_pch_data.
0291  *
0292  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
0293  */
0294 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
0295 {
0296     void __iomem *p = adap->pch_base_address;
0297     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0298     pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
0299 }
0300 
0301 /**
0302  * pch_i2c_stop() - generate stop condition in normal mode.
0303  * @adap:   Pointer to struct i2c_algo_pch_data.
0304  */
0305 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
0306 {
0307     void __iomem *p = adap->pch_base_address;
0308     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0309     /* clear the start bit */
0310     pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
0311 }
0312 
0313 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
0314 {
0315     long ret;
0316     void __iomem *p = adap->pch_base_address;
0317 
0318     ret = wait_event_timeout(pch_event,
0319             (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
0320     if (!ret) {
0321         pch_err(adap, "%s:wait-event timeout\n", __func__);
0322         adap->pch_event_flag = 0;
0323         pch_i2c_stop(adap);
0324         pch_i2c_init(adap);
0325         return -ETIMEDOUT;
0326     }
0327 
0328     if (adap->pch_event_flag & I2C_ERROR_MASK) {
0329         pch_err(adap, "Lost Arbitration\n");
0330         adap->pch_event_flag = 0;
0331         pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
0332         pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
0333         pch_i2c_init(adap);
0334         return -EAGAIN;
0335     }
0336 
0337     adap->pch_event_flag = 0;
0338 
0339     if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
0340         pch_dbg(adap, "Receive NACK for slave address setting\n");
0341         return -ENXIO;
0342     }
0343 
0344     return 0;
0345 }
0346 
0347 /**
0348  * pch_i2c_repstart() - generate repeated start condition in normal mode
0349  * @adap:   Pointer to struct i2c_algo_pch_data.
0350  */
0351 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
0352 {
0353     void __iomem *p = adap->pch_base_address;
0354     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0355     pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
0356 }
0357 
0358 /**
0359  * pch_i2c_writebytes() - write data to I2C bus in normal mode
0360  * @i2c_adap:   Pointer to the struct i2c_adapter.
0361  * @msgs:   Pointer to the i2c message structure.
0362  * @last:   specifies whether last message or not.
0363  *      In the case of compound mode it will be 1 for last message,
0364  *      otherwise 0.
0365  * @first:  specifies whether first message or not.
0366  *      1 for first message otherwise 0.
0367  */
0368 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
0369                   struct i2c_msg *msgs, u32 last, u32 first)
0370 {
0371     struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
0372     u8 *buf;
0373     u32 length;
0374     u32 addr;
0375     u32 addr_2_msb;
0376     u32 addr_8_lsb;
0377     s32 wrcount;
0378     s32 rtn;
0379     void __iomem *p = adap->pch_base_address;
0380 
0381     length = msgs->len;
0382     buf = msgs->buf;
0383     addr = msgs->addr;
0384 
0385     /* enable master tx */
0386     pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
0387 
0388     pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
0389         length);
0390 
0391     if (first) {
0392         if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
0393             return -ETIME;
0394     }
0395 
0396     if (msgs->flags & I2C_M_TEN) {
0397         addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
0398         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
0399         if (first)
0400             pch_i2c_start(adap);
0401 
0402         rtn = pch_i2c_wait_for_check_xfer(adap);
0403         if (rtn)
0404             return rtn;
0405 
0406         addr_8_lsb = (addr & I2C_ADDR_MSK);
0407         iowrite32(addr_8_lsb, p + PCH_I2CDR);
0408     } else {
0409         /* set 7 bit slave address and R/W bit as 0 */
0410         iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
0411         if (first)
0412             pch_i2c_start(adap);
0413     }
0414 
0415     rtn = pch_i2c_wait_for_check_xfer(adap);
0416     if (rtn)
0417         return rtn;
0418 
0419     for (wrcount = 0; wrcount < length; ++wrcount) {
0420         /* write buffer value to I2C data register */
0421         iowrite32(buf[wrcount], p + PCH_I2CDR);
0422         pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
0423 
0424         rtn = pch_i2c_wait_for_check_xfer(adap);
0425         if (rtn)
0426             return rtn;
0427 
0428         pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
0429         pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
0430     }
0431 
0432     /* check if this is the last message */
0433     if (last)
0434         pch_i2c_stop(adap);
0435     else
0436         pch_i2c_repstart(adap);
0437 
0438     pch_dbg(adap, "return=%d\n", wrcount);
0439 
0440     return wrcount;
0441 }
0442 
0443 /**
0444  * pch_i2c_sendack() - send ACK
0445  * @adap:   Pointer to struct i2c_algo_pch_data.
0446  */
0447 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
0448 {
0449     void __iomem *p = adap->pch_base_address;
0450     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0451     pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
0452 }
0453 
0454 /**
0455  * pch_i2c_sendnack() - send NACK
0456  * @adap:   Pointer to struct i2c_algo_pch_data.
0457  */
0458 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
0459 {
0460     void __iomem *p = adap->pch_base_address;
0461     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0462     pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
0463 }
0464 
0465 /**
0466  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
0467  * @adap:   Pointer to struct i2c_algo_pch_data.
0468  *
0469  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
0470  */
0471 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
0472 {
0473     void __iomem *p = adap->pch_base_address;
0474     pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
0475     pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
0476 }
0477 
0478 /**
0479  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
0480  * @i2c_adap:   Pointer to the struct i2c_adapter.
0481  * @msgs:   Pointer to i2c_msg structure.
0482  * @last:   specifies whether last message or not.
0483  * @first:  specifies whether first message or not.
0484  */
0485 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
0486                  u32 last, u32 first)
0487 {
0488     struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
0489 
0490     u8 *buf;
0491     u32 count;
0492     u32 length;
0493     u32 addr;
0494     u32 addr_2_msb;
0495     u32 addr_8_lsb;
0496     void __iomem *p = adap->pch_base_address;
0497     s32 rtn;
0498 
0499     length = msgs->len;
0500     buf = msgs->buf;
0501     addr = msgs->addr;
0502 
0503     /* enable master reception */
0504     pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
0505 
0506     if (first) {
0507         if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
0508             return -ETIME;
0509     }
0510 
0511     if (msgs->flags & I2C_M_TEN) {
0512         addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
0513         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
0514         if (first)
0515             pch_i2c_start(adap);
0516 
0517         rtn = pch_i2c_wait_for_check_xfer(adap);
0518         if (rtn)
0519             return rtn;
0520 
0521         addr_8_lsb = (addr & I2C_ADDR_MSK);
0522         iowrite32(addr_8_lsb, p + PCH_I2CDR);
0523 
0524         pch_i2c_restart(adap);
0525 
0526         rtn = pch_i2c_wait_for_check_xfer(adap);
0527         if (rtn)
0528             return rtn;
0529 
0530         addr_2_msb |= I2C_RD;
0531         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
0532     } else {
0533         /* 7 address bits + R/W bit */
0534         iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
0535     }
0536 
0537     /* check if it is the first message */
0538     if (first)
0539         pch_i2c_start(adap);
0540 
0541     rtn = pch_i2c_wait_for_check_xfer(adap);
0542     if (rtn)
0543         return rtn;
0544 
0545     if (length == 0) {
0546         pch_i2c_stop(adap);
0547         ioread32(p + PCH_I2CDR); /* Dummy read needs */
0548 
0549         count = length;
0550     } else {
0551         int read_index;
0552         int loop;
0553         pch_i2c_sendack(adap);
0554 
0555         /* Dummy read */
0556         for (loop = 1, read_index = 0; loop < length; loop++) {
0557             buf[read_index] = ioread32(p + PCH_I2CDR);
0558 
0559             if (loop != 1)
0560                 read_index++;
0561 
0562             rtn = pch_i2c_wait_for_check_xfer(adap);
0563             if (rtn)
0564                 return rtn;
0565         }   /* end for */
0566 
0567         pch_i2c_sendnack(adap);
0568 
0569         buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
0570 
0571         if (length != 1)
0572             read_index++;
0573 
0574         rtn = pch_i2c_wait_for_check_xfer(adap);
0575         if (rtn)
0576             return rtn;
0577 
0578         if (last)
0579             pch_i2c_stop(adap);
0580         else
0581             pch_i2c_repstart(adap);
0582 
0583         buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
0584         count = read_index;
0585     }
0586 
0587     return count;
0588 }
0589 
0590 /**
0591  * pch_i2c_cb() - Interrupt handler Call back function
0592  * @adap:   Pointer to struct i2c_algo_pch_data.
0593  */
0594 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
0595 {
0596     u32 sts;
0597     void __iomem *p = adap->pch_base_address;
0598 
0599     sts = ioread32(p + PCH_I2CSR);
0600     sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
0601     if (sts & I2CMAL_BIT)
0602         adap->pch_event_flag |= I2CMAL_EVENT;
0603 
0604     if (sts & I2CMCF_BIT)
0605         adap->pch_event_flag |= I2CMCF_EVENT;
0606 
0607     /* clear the applicable bits */
0608     pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
0609 
0610     pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
0611 
0612     wake_up(&pch_event);
0613 }
0614 
0615 /**
0616  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
0617  * @irq:    irq number.
0618  * @pData:  cookie passed back to the handler function.
0619  */
0620 static irqreturn_t pch_i2c_handler(int irq, void *pData)
0621 {
0622     u32 reg_val;
0623     int flag;
0624     int i;
0625     struct adapter_info *adap_info = pData;
0626     void __iomem *p;
0627     u32 mode;
0628 
0629     for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
0630         p = adap_info->pch_data[i].pch_base_address;
0631         mode = ioread32(p + PCH_I2CMOD);
0632         mode &= BUFFER_MODE | EEPROM_SR_MODE;
0633         if (mode != NORMAL_MODE) {
0634             pch_err(adap_info->pch_data,
0635                 "I2C-%d mode(%d) is not supported\n", mode, i);
0636             continue;
0637         }
0638         reg_val = ioread32(p + PCH_I2CSR);
0639         if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
0640             pch_i2c_cb(&adap_info->pch_data[i]);
0641             flag = 1;
0642         }
0643     }
0644 
0645     return flag ? IRQ_HANDLED : IRQ_NONE;
0646 }
0647 
0648 /**
0649  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
0650  * @i2c_adap:   Pointer to the struct i2c_adapter.
0651  * @msgs:   Pointer to i2c_msg structure.
0652  * @num:    number of messages.
0653  */
0654 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
0655             struct i2c_msg *msgs, s32 num)
0656 {
0657     struct i2c_msg *pmsg;
0658     u32 i = 0;
0659     u32 status;
0660     s32 ret;
0661 
0662     struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
0663 
0664     ret = mutex_lock_interruptible(&pch_mutex);
0665     if (ret)
0666         return ret;
0667 
0668     if (adap->p_adapter_info->pch_i2c_suspended) {
0669         mutex_unlock(&pch_mutex);
0670         return -EBUSY;
0671     }
0672 
0673     pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
0674         adap->p_adapter_info->pch_i2c_suspended);
0675     /* transfer not completed */
0676     adap->pch_i2c_xfer_in_progress = true;
0677 
0678     for (i = 0; i < num && ret >= 0; i++) {
0679         pmsg = &msgs[i];
0680         pmsg->flags |= adap->pch_buff_mode_en;
0681         status = pmsg->flags;
0682         pch_dbg(adap,
0683             "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
0684 
0685         if ((status & (I2C_M_RD)) != false) {
0686             ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
0687                         (i == 0));
0688         } else {
0689             ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
0690                          (i == 0));
0691         }
0692     }
0693 
0694     adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
0695 
0696     mutex_unlock(&pch_mutex);
0697 
0698     return (ret < 0) ? ret : num;
0699 }
0700 
0701 /**
0702  * pch_i2c_func() - return the functionality of the I2C driver
0703  * @adap:   Pointer to struct i2c_algo_pch_data.
0704  */
0705 static u32 pch_i2c_func(struct i2c_adapter *adap)
0706 {
0707     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
0708 }
0709 
0710 static const struct i2c_algorithm pch_algorithm = {
0711     .master_xfer = pch_i2c_xfer,
0712     .functionality = pch_i2c_func
0713 };
0714 
0715 /**
0716  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
0717  * @adap:   Pointer to struct i2c_algo_pch_data.
0718  */
0719 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
0720 {
0721     void __iomem *p = adap->pch_base_address;
0722 
0723     pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
0724 
0725     iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
0726 
0727     iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
0728 }
0729 
0730 static int pch_i2c_probe(struct pci_dev *pdev,
0731                    const struct pci_device_id *id)
0732 {
0733     void __iomem *base_addr;
0734     int ret;
0735     int i, j;
0736     struct adapter_info *adap_info;
0737     struct i2c_adapter *pch_adap;
0738 
0739     pch_pci_dbg(pdev, "Entered.\n");
0740 
0741     adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
0742     if (adap_info == NULL)
0743         return -ENOMEM;
0744 
0745     ret = pci_enable_device(pdev);
0746     if (ret) {
0747         pch_pci_err(pdev, "pci_enable_device FAILED\n");
0748         goto err_pci_enable;
0749     }
0750 
0751     ret = pci_request_regions(pdev, KBUILD_MODNAME);
0752     if (ret) {
0753         pch_pci_err(pdev, "pci_request_regions FAILED\n");
0754         goto err_pci_req;
0755     }
0756 
0757     base_addr = pci_iomap(pdev, 1, 0);
0758 
0759     if (base_addr == NULL) {
0760         pch_pci_err(pdev, "pci_iomap FAILED\n");
0761         ret = -ENOMEM;
0762         goto err_pci_iomap;
0763     }
0764 
0765     /* Set the number of I2C channel instance */
0766     adap_info->ch_num = id->driver_data;
0767 
0768     for (i = 0; i < adap_info->ch_num; i++) {
0769         pch_adap = &adap_info->pch_data[i].pch_adapter;
0770         adap_info->pch_i2c_suspended = false;
0771 
0772         adap_info->pch_data[i].p_adapter_info = adap_info;
0773 
0774         pch_adap->owner = THIS_MODULE;
0775         pch_adap->class = I2C_CLASS_HWMON;
0776         strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
0777         pch_adap->algo = &pch_algorithm;
0778         pch_adap->algo_data = &adap_info->pch_data[i];
0779 
0780         /* base_addr + offset; */
0781         adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
0782 
0783         pch_adap->dev.of_node = pdev->dev.of_node;
0784         pch_adap->dev.parent = &pdev->dev;
0785     }
0786 
0787     ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
0788           KBUILD_MODNAME, adap_info);
0789     if (ret) {
0790         pch_pci_err(pdev, "request_irq FAILED\n");
0791         goto err_request_irq;
0792     }
0793 
0794     for (i = 0; i < adap_info->ch_num; i++) {
0795         pch_adap = &adap_info->pch_data[i].pch_adapter;
0796 
0797         pch_i2c_init(&adap_info->pch_data[i]);
0798 
0799         pch_adap->nr = i;
0800         ret = i2c_add_numbered_adapter(pch_adap);
0801         if (ret) {
0802             pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
0803             goto err_add_adapter;
0804         }
0805     }
0806 
0807     pci_set_drvdata(pdev, adap_info);
0808     pch_pci_dbg(pdev, "returns %d.\n", ret);
0809     return 0;
0810 
0811 err_add_adapter:
0812     for (j = 0; j < i; j++)
0813         i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
0814     free_irq(pdev->irq, adap_info);
0815 err_request_irq:
0816     pci_iounmap(pdev, base_addr);
0817 err_pci_iomap:
0818     pci_release_regions(pdev);
0819 err_pci_req:
0820     pci_disable_device(pdev);
0821 err_pci_enable:
0822     kfree(adap_info);
0823     return ret;
0824 }
0825 
0826 static void pch_i2c_remove(struct pci_dev *pdev)
0827 {
0828     int i;
0829     struct adapter_info *adap_info = pci_get_drvdata(pdev);
0830 
0831     free_irq(pdev->irq, adap_info);
0832 
0833     for (i = 0; i < adap_info->ch_num; i++) {
0834         pch_i2c_disbl_int(&adap_info->pch_data[i]);
0835         i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
0836     }
0837 
0838     if (adap_info->pch_data[0].pch_base_address)
0839         pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
0840 
0841     for (i = 0; i < adap_info->ch_num; i++)
0842         adap_info->pch_data[i].pch_base_address = NULL;
0843 
0844     pci_release_regions(pdev);
0845 
0846     pci_disable_device(pdev);
0847     kfree(adap_info);
0848 }
0849 
0850 static int __maybe_unused pch_i2c_suspend(struct device *dev)
0851 {
0852     int i;
0853     struct pci_dev *pdev = to_pci_dev(dev);
0854     struct adapter_info *adap_info = pci_get_drvdata(pdev);
0855     void __iomem *p = adap_info->pch_data[0].pch_base_address;
0856 
0857     adap_info->pch_i2c_suspended = true;
0858 
0859     for (i = 0; i < adap_info->ch_num; i++) {
0860         while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
0861             /* Wait until all channel transfers are completed */
0862             msleep(20);
0863         }
0864     }
0865 
0866     /* Disable the i2c interrupts */
0867     for (i = 0; i < adap_info->ch_num; i++)
0868         pch_i2c_disbl_int(&adap_info->pch_data[i]);
0869 
0870     pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
0871         "invoked function pch_i2c_disbl_int successfully\n",
0872         ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
0873         ioread32(p + PCH_I2CESRSTA));
0874 
0875     return 0;
0876 }
0877 
0878 static int __maybe_unused pch_i2c_resume(struct device *dev)
0879 {
0880     int i;
0881     struct adapter_info *adap_info = dev_get_drvdata(dev);
0882 
0883     for (i = 0; i < adap_info->ch_num; i++)
0884         pch_i2c_init(&adap_info->pch_data[i]);
0885 
0886     adap_info->pch_i2c_suspended = false;
0887 
0888     return 0;
0889 }
0890 
0891 static SIMPLE_DEV_PM_OPS(pch_i2c_pm_ops, pch_i2c_suspend, pch_i2c_resume);
0892 
0893 static struct pci_driver pch_pcidriver = {
0894     .name = KBUILD_MODNAME,
0895     .id_table = pch_pcidev_id,
0896     .probe = pch_i2c_probe,
0897     .remove = pch_i2c_remove,
0898     .driver.pm = &pch_i2c_pm_ops,
0899 };
0900 
0901 module_pci_driver(pch_pcidriver);
0902 
0903 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
0904 MODULE_LICENSE("GPL");
0905 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
0906 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
0907 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
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