Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * I2C bus driver for Conexant Digicolor SoCs
0004  *
0005  * Author: Baruch Siach <baruch@tkos.co.il>
0006  *
0007  * Copyright (C) 2015 Paradox Innovation Ltd.
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/delay.h>
0013 #include <linux/i2c.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/platform_device.h>
0020 
0021 #define TIMEOUT_MS      100
0022 
0023 #define II_CONTROL      0x0
0024 #define II_CONTROL_LOCAL_RESET  BIT(0)
0025 
0026 #define II_CLOCKTIME        0x1
0027 
0028 #define II_COMMAND      0x2
0029 #define II_CMD_START        1
0030 #define II_CMD_RESTART      2
0031 #define II_CMD_SEND_ACK     3
0032 #define II_CMD_GET_ACK      6
0033 #define II_CMD_GET_NOACK    7
0034 #define II_CMD_STOP     10
0035 #define II_COMMAND_GO       BIT(7)
0036 #define II_COMMAND_COMPLETION_STATUS(r) (((r) >> 5) & 3)
0037 #define II_CMD_STATUS_NORMAL    0
0038 #define II_CMD_STATUS_ACK_GOOD  1
0039 #define II_CMD_STATUS_ACK_BAD   2
0040 #define II_CMD_STATUS_ABORT 3
0041 
0042 #define II_DATA         0x3
0043 #define II_INTFLAG_CLEAR    0x8
0044 #define II_INTENABLE        0xa
0045 
0046 struct dc_i2c {
0047     struct i2c_adapter  adap;
0048     struct device       *dev;
0049     void __iomem        *regs;
0050     struct clk      *clk;
0051     unsigned int        frequency;
0052 
0053     struct i2c_msg      *msg;
0054     unsigned int        msgbuf_ptr;
0055     int         last;
0056     spinlock_t      lock;
0057     struct completion   done;
0058     int         state;
0059     int         error;
0060 };
0061 
0062 enum {
0063     STATE_IDLE,
0064     STATE_START,
0065     STATE_ADDR,
0066     STATE_WRITE,
0067     STATE_READ,
0068     STATE_STOP,
0069 };
0070 
0071 static void dc_i2c_cmd(struct dc_i2c *i2c, u8 cmd)
0072 {
0073     writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND);
0074 }
0075 
0076 static u8 dc_i2c_addr_cmd(struct i2c_msg *msg)
0077 {
0078     u8 addr = (msg->addr & 0x7f) << 1;
0079 
0080     if (msg->flags & I2C_M_RD)
0081         addr |= 1;
0082 
0083     return addr;
0084 }
0085 
0086 static void dc_i2c_data(struct dc_i2c *i2c, u8 data)
0087 {
0088     writeb_relaxed(data, i2c->regs + II_DATA);
0089 }
0090 
0091 static void dc_i2c_write_byte(struct dc_i2c *i2c, u8 byte)
0092 {
0093     dc_i2c_data(i2c, byte);
0094     dc_i2c_cmd(i2c, II_CMD_SEND_ACK);
0095 }
0096 
0097 static void dc_i2c_write_buf(struct dc_i2c *i2c)
0098 {
0099     dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]);
0100 }
0101 
0102 static void dc_i2c_next_read(struct dc_i2c *i2c)
0103 {
0104     bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len);
0105 
0106     dc_i2c_cmd(i2c, last ? II_CMD_GET_NOACK : II_CMD_GET_ACK);
0107 }
0108 
0109 static void dc_i2c_stop(struct dc_i2c *i2c)
0110 {
0111     i2c->state = STATE_STOP;
0112     if (i2c->last)
0113         dc_i2c_cmd(i2c, II_CMD_STOP);
0114     else
0115         complete(&i2c->done);
0116 }
0117 
0118 static u8 dc_i2c_read_byte(struct dc_i2c *i2c)
0119 {
0120     return readb_relaxed(i2c->regs + II_DATA);
0121 }
0122 
0123 static void dc_i2c_read_buf(struct dc_i2c *i2c)
0124 {
0125     i2c->msg->buf[i2c->msgbuf_ptr++] = dc_i2c_read_byte(i2c);
0126     dc_i2c_next_read(i2c);
0127 }
0128 
0129 static void dc_i2c_set_irq(struct dc_i2c *i2c, int enable)
0130 {
0131     if (enable)
0132         writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
0133     writeb_relaxed(!!enable, i2c->regs + II_INTENABLE);
0134 }
0135 
0136 static int dc_i2c_cmd_status(struct dc_i2c *i2c)
0137 {
0138     u8 cmd = readb_relaxed(i2c->regs + II_COMMAND);
0139 
0140     return II_COMMAND_COMPLETION_STATUS(cmd);
0141 }
0142 
0143 static void dc_i2c_start_msg(struct dc_i2c *i2c, int first)
0144 {
0145     struct i2c_msg *msg = i2c->msg;
0146 
0147     if (!(msg->flags & I2C_M_NOSTART)) {
0148         i2c->state = STATE_START;
0149         dc_i2c_cmd(i2c, first ? II_CMD_START : II_CMD_RESTART);
0150     } else if (msg->flags & I2C_M_RD) {
0151         i2c->state = STATE_READ;
0152         dc_i2c_next_read(i2c);
0153     } else {
0154         i2c->state = STATE_WRITE;
0155         dc_i2c_write_buf(i2c);
0156     }
0157 }
0158 
0159 static irqreturn_t dc_i2c_irq(int irq, void *dev_id)
0160 {
0161     struct dc_i2c *i2c = dev_id;
0162     int cmd_status = dc_i2c_cmd_status(i2c);
0163     u8 addr_cmd;
0164 
0165     writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
0166 
0167     spin_lock(&i2c->lock);
0168 
0169     if (cmd_status == II_CMD_STATUS_ACK_BAD
0170         || cmd_status == II_CMD_STATUS_ABORT) {
0171         i2c->error = -EIO;
0172         complete(&i2c->done);
0173         goto out;
0174     }
0175 
0176     switch (i2c->state) {
0177     case STATE_START:
0178         addr_cmd = dc_i2c_addr_cmd(i2c->msg);
0179         dc_i2c_write_byte(i2c, addr_cmd);
0180         i2c->state = STATE_ADDR;
0181         break;
0182     case STATE_ADDR:
0183         if (i2c->msg->flags & I2C_M_RD) {
0184             dc_i2c_next_read(i2c);
0185             i2c->state = STATE_READ;
0186             break;
0187         }
0188         i2c->state = STATE_WRITE;
0189         fallthrough;
0190     case STATE_WRITE:
0191         if (i2c->msgbuf_ptr < i2c->msg->len)
0192             dc_i2c_write_buf(i2c);
0193         else
0194             dc_i2c_stop(i2c);
0195         break;
0196     case STATE_READ:
0197         if (i2c->msgbuf_ptr < i2c->msg->len)
0198             dc_i2c_read_buf(i2c);
0199         else
0200             dc_i2c_stop(i2c);
0201         break;
0202     case STATE_STOP:
0203         i2c->state = STATE_IDLE;
0204         complete(&i2c->done);
0205         break;
0206     }
0207 
0208 out:
0209     spin_unlock(&i2c->lock);
0210     return IRQ_HANDLED;
0211 }
0212 
0213 static int dc_i2c_xfer_msg(struct dc_i2c *i2c, struct i2c_msg *msg, int first,
0214                int last)
0215 {
0216     unsigned long timeout = msecs_to_jiffies(TIMEOUT_MS);
0217     unsigned long flags;
0218 
0219     spin_lock_irqsave(&i2c->lock, flags);
0220     i2c->msg = msg;
0221     i2c->msgbuf_ptr = 0;
0222     i2c->last = last;
0223     i2c->error = 0;
0224 
0225     reinit_completion(&i2c->done);
0226     dc_i2c_set_irq(i2c, 1);
0227     dc_i2c_start_msg(i2c, first);
0228     spin_unlock_irqrestore(&i2c->lock, flags);
0229 
0230     timeout = wait_for_completion_timeout(&i2c->done, timeout);
0231     dc_i2c_set_irq(i2c, 0);
0232     if (timeout == 0) {
0233         i2c->state = STATE_IDLE;
0234         return -ETIMEDOUT;
0235     }
0236 
0237     if (i2c->error)
0238         return i2c->error;
0239 
0240     return 0;
0241 }
0242 
0243 static int dc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0244 {
0245     struct dc_i2c *i2c = adap->algo_data;
0246     int i, ret;
0247 
0248     for (i = 0; i < num; i++) {
0249         ret = dc_i2c_xfer_msg(i2c, &msgs[i], i == 0, i == num - 1);
0250         if (ret)
0251             return ret;
0252     }
0253 
0254     return num;
0255 }
0256 
0257 static int dc_i2c_init_hw(struct dc_i2c *i2c)
0258 {
0259     unsigned long clk_rate = clk_get_rate(i2c->clk);
0260     unsigned int clocktime;
0261 
0262     writeb_relaxed(II_CONTROL_LOCAL_RESET, i2c->regs + II_CONTROL);
0263     udelay(100);
0264     writeb_relaxed(0, i2c->regs + II_CONTROL);
0265     udelay(100);
0266 
0267     clocktime = DIV_ROUND_UP(clk_rate, 64 * i2c->frequency);
0268     if (clocktime < 1 || clocktime > 0xff) {
0269         dev_err(i2c->dev, "can't set bus speed of %u Hz\n",
0270             i2c->frequency);
0271         return -EINVAL;
0272     }
0273     writeb_relaxed(clocktime - 1, i2c->regs + II_CLOCKTIME);
0274 
0275     return 0;
0276 }
0277 
0278 static u32 dc_i2c_func(struct i2c_adapter *adap)
0279 {
0280     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
0281 }
0282 
0283 static const struct i2c_algorithm dc_i2c_algorithm = {
0284     .master_xfer    = dc_i2c_xfer,
0285     .functionality  = dc_i2c_func,
0286 };
0287 
0288 static int dc_i2c_probe(struct platform_device *pdev)
0289 {
0290     struct device_node *np = pdev->dev.of_node;
0291     struct dc_i2c *i2c;
0292     int ret = 0, irq;
0293 
0294     i2c = devm_kzalloc(&pdev->dev, sizeof(struct dc_i2c), GFP_KERNEL);
0295     if (!i2c)
0296         return -ENOMEM;
0297 
0298     if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
0299                  &i2c->frequency))
0300         i2c->frequency = I2C_MAX_STANDARD_MODE_FREQ;
0301 
0302     i2c->dev = &pdev->dev;
0303     platform_set_drvdata(pdev, i2c);
0304 
0305     spin_lock_init(&i2c->lock);
0306     init_completion(&i2c->done);
0307 
0308     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0309     if (IS_ERR(i2c->clk))
0310         return PTR_ERR(i2c->clk);
0311 
0312     i2c->regs = devm_platform_ioremap_resource(pdev, 0);
0313     if (IS_ERR(i2c->regs))
0314         return PTR_ERR(i2c->regs);
0315 
0316     irq = platform_get_irq(pdev, 0);
0317     if (irq < 0)
0318         return irq;
0319 
0320     ret = devm_request_irq(&pdev->dev, irq, dc_i2c_irq, 0,
0321                    dev_name(&pdev->dev), i2c);
0322     if (ret < 0)
0323         return ret;
0324 
0325     strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
0326         sizeof(i2c->adap.name));
0327     i2c->adap.owner = THIS_MODULE;
0328     i2c->adap.algo = &dc_i2c_algorithm;
0329     i2c->adap.dev.parent = &pdev->dev;
0330     i2c->adap.dev.of_node = np;
0331     i2c->adap.algo_data = i2c;
0332 
0333     ret = dc_i2c_init_hw(i2c);
0334     if (ret)
0335         return ret;
0336 
0337     ret = clk_prepare_enable(i2c->clk);
0338     if (ret < 0)
0339         return ret;
0340 
0341     ret = i2c_add_adapter(&i2c->adap);
0342     if (ret < 0) {
0343         clk_disable_unprepare(i2c->clk);
0344         return ret;
0345     }
0346 
0347     return 0;
0348 }
0349 
0350 static int dc_i2c_remove(struct platform_device *pdev)
0351 {
0352     struct dc_i2c *i2c = platform_get_drvdata(pdev);
0353 
0354     i2c_del_adapter(&i2c->adap);
0355     clk_disable_unprepare(i2c->clk);
0356 
0357     return 0;
0358 }
0359 
0360 static const struct of_device_id dc_i2c_match[] = {
0361     { .compatible = "cnxt,cx92755-i2c" },
0362     { },
0363 };
0364 MODULE_DEVICE_TABLE(of, dc_i2c_match);
0365 
0366 static struct platform_driver dc_i2c_driver = {
0367     .probe   = dc_i2c_probe,
0368     .remove  = dc_i2c_remove,
0369     .driver  = {
0370         .name  = "digicolor-i2c",
0371         .of_match_table = dc_i2c_match,
0372     },
0373 };
0374 module_platform_driver(dc_i2c_driver);
0375 
0376 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
0377 MODULE_DESCRIPTION("Conexant Digicolor I2C master driver");
0378 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!