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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Synopsys DesignWare I2C adapter driver (master only).
0004  *
0005  * Based on the TI DAVINCI I2C adapter driver.
0006  *
0007  * Copyright (C) 2006 Texas Instruments.
0008  * Copyright (C) 2007 MontaVista Software Inc.
0009  * Copyright (C) 2009 Provigent Ltd.
0010  */
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/errno.h>
0014 #include <linux/export.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/i2c.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/module.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/regmap.h>
0022 #include <linux/reset.h>
0023 
0024 #include "i2c-designware-core.h"
0025 
0026 #define AMD_TIMEOUT_MIN_US  25
0027 #define AMD_TIMEOUT_MAX_US  250
0028 #define AMD_MASTERCFG_MASK  GENMASK(15, 0)
0029 
0030 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
0031 {
0032     /* Configure Tx/Rx FIFO threshold levels */
0033     regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
0034     regmap_write(dev->map, DW_IC_RX_TL, 0);
0035 
0036     /* Configure the I2C master */
0037     regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
0038 }
0039 
0040 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
0041 {
0042     u32 comp_param1;
0043     u32 sda_falling_time, scl_falling_time;
0044     struct i2c_timings *t = &dev->timings;
0045     const char *fp_str = "";
0046     u32 ic_clk;
0047     int ret;
0048 
0049     ret = i2c_dw_acquire_lock(dev);
0050     if (ret)
0051         return ret;
0052 
0053     ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
0054     i2c_dw_release_lock(dev);
0055     if (ret)
0056         return ret;
0057 
0058     /* Set standard and fast speed dividers for high/low periods */
0059     sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
0060     scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
0061 
0062     /* Calculate SCL timing parameters for standard mode if not set */
0063     if (!dev->ss_hcnt || !dev->ss_lcnt) {
0064         ic_clk = i2c_dw_clk_rate(dev);
0065         dev->ss_hcnt =
0066             i2c_dw_scl_hcnt(ic_clk,
0067                     4000,   /* tHD;STA = tHIGH = 4.0 us */
0068                     sda_falling_time,
0069                     0,  /* 0: DW default, 1: Ideal */
0070                     0); /* No offset */
0071         dev->ss_lcnt =
0072             i2c_dw_scl_lcnt(ic_clk,
0073                     4700,   /* tLOW = 4.7 us */
0074                     scl_falling_time,
0075                     0); /* No offset */
0076     }
0077     dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
0078         dev->ss_hcnt, dev->ss_lcnt);
0079 
0080     /*
0081      * Set SCL timing parameters for fast mode or fast mode plus. Only
0082      * difference is the timing parameter values since the registers are
0083      * the same.
0084      */
0085     if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) {
0086         /*
0087          * Check are Fast Mode Plus parameters available. Calculate
0088          * SCL timing parameters for Fast Mode Plus if not set.
0089          */
0090         if (dev->fp_hcnt && dev->fp_lcnt) {
0091             dev->fs_hcnt = dev->fp_hcnt;
0092             dev->fs_lcnt = dev->fp_lcnt;
0093         } else {
0094             ic_clk = i2c_dw_clk_rate(dev);
0095             dev->fs_hcnt =
0096                 i2c_dw_scl_hcnt(ic_clk,
0097                         260,    /* tHIGH = 260 ns */
0098                         sda_falling_time,
0099                         0,  /* DW default */
0100                         0); /* No offset */
0101             dev->fs_lcnt =
0102                 i2c_dw_scl_lcnt(ic_clk,
0103                         500,    /* tLOW = 500 ns */
0104                         scl_falling_time,
0105                         0); /* No offset */
0106         }
0107         fp_str = " Plus";
0108     }
0109     /*
0110      * Calculate SCL timing parameters for fast mode if not set. They are
0111      * needed also in high speed mode.
0112      */
0113     if (!dev->fs_hcnt || !dev->fs_lcnt) {
0114         ic_clk = i2c_dw_clk_rate(dev);
0115         dev->fs_hcnt =
0116             i2c_dw_scl_hcnt(ic_clk,
0117                     600,    /* tHD;STA = tHIGH = 0.6 us */
0118                     sda_falling_time,
0119                     0,  /* 0: DW default, 1: Ideal */
0120                     0); /* No offset */
0121         dev->fs_lcnt =
0122             i2c_dw_scl_lcnt(ic_clk,
0123                     1300,   /* tLOW = 1.3 us */
0124                     scl_falling_time,
0125                     0); /* No offset */
0126     }
0127     dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
0128         fp_str, dev->fs_hcnt, dev->fs_lcnt);
0129 
0130     /* Check is high speed possible and fall back to fast mode if not */
0131     if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
0132         DW_IC_CON_SPEED_HIGH) {
0133         if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
0134             != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
0135             dev_err(dev->dev, "High Speed not supported!\n");
0136             t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
0137             dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
0138             dev->master_cfg |= DW_IC_CON_SPEED_FAST;
0139             dev->hs_hcnt = 0;
0140             dev->hs_lcnt = 0;
0141         } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
0142             ic_clk = i2c_dw_clk_rate(dev);
0143             dev->hs_hcnt =
0144                 i2c_dw_scl_hcnt(ic_clk,
0145                         160,    /* tHIGH = 160 ns */
0146                         sda_falling_time,
0147                         0,  /* DW default */
0148                         0); /* No offset */
0149             dev->hs_lcnt =
0150                 i2c_dw_scl_lcnt(ic_clk,
0151                         320,    /* tLOW = 320 ns */
0152                         scl_falling_time,
0153                         0); /* No offset */
0154         }
0155         dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
0156             dev->hs_hcnt, dev->hs_lcnt);
0157     }
0158 
0159     ret = i2c_dw_set_sda_hold(dev);
0160     if (ret)
0161         return ret;
0162 
0163     dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
0164     return 0;
0165 }
0166 
0167 /**
0168  * i2c_dw_init_master() - Initialize the designware I2C master hardware
0169  * @dev: device private data
0170  *
0171  * This functions configures and enables the I2C master.
0172  * This function is called during I2C init function, and in case of timeout at
0173  * run time.
0174  */
0175 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
0176 {
0177     int ret;
0178 
0179     ret = i2c_dw_acquire_lock(dev);
0180     if (ret)
0181         return ret;
0182 
0183     /* Disable the adapter */
0184     __i2c_dw_disable(dev);
0185 
0186     /* Write standard speed timing parameters */
0187     regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
0188     regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
0189 
0190     /* Write fast mode/fast mode plus timing parameters */
0191     regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
0192     regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
0193 
0194     /* Write high speed timing parameters if supported */
0195     if (dev->hs_hcnt && dev->hs_lcnt) {
0196         regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
0197         regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
0198     }
0199 
0200     /* Write SDA hold time if supported */
0201     if (dev->sda_hold_time)
0202         regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
0203 
0204     i2c_dw_configure_fifo_master(dev);
0205     i2c_dw_release_lock(dev);
0206 
0207     return 0;
0208 }
0209 
0210 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
0211 {
0212     struct i2c_msg *msgs = dev->msgs;
0213     u32 ic_con = 0, ic_tar = 0;
0214     u32 dummy;
0215 
0216     /* Disable the adapter */
0217     __i2c_dw_disable(dev);
0218 
0219     /* If the slave address is ten bit address, enable 10BITADDR */
0220     if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
0221         ic_con = DW_IC_CON_10BITADDR_MASTER;
0222         /*
0223          * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
0224          * mode has to be enabled via bit 12 of IC_TAR register.
0225          * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
0226          * detected from registers.
0227          */
0228         ic_tar = DW_IC_TAR_10BITADDR_MASTER;
0229     }
0230 
0231     regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
0232                ic_con);
0233 
0234     /*
0235      * Set the slave (target) address and enable 10-bit addressing mode
0236      * if applicable.
0237      */
0238     regmap_write(dev->map, DW_IC_TAR,
0239              msgs[dev->msg_write_idx].addr | ic_tar);
0240 
0241     /* Enforce disabled interrupts (due to HW issues) */
0242     i2c_dw_disable_int(dev);
0243 
0244     /* Enable the adapter */
0245     __i2c_dw_enable(dev);
0246 
0247     /* Dummy read to avoid the register getting stuck on Bay Trail */
0248     regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
0249 
0250     /* Clear and enable interrupts */
0251     regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
0252     regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
0253 }
0254 
0255 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
0256 {
0257     u32 val;
0258     int ret;
0259 
0260     ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
0261                        !(val & DW_IC_INTR_STOP_DET),
0262                     1100, 20000);
0263     if (ret)
0264         dev_err(dev->dev, "i2c timeout error %d\n", ret);
0265 
0266     return ret;
0267 }
0268 
0269 static int i2c_dw_status(struct dw_i2c_dev *dev)
0270 {
0271     int status;
0272 
0273     status = i2c_dw_wait_bus_not_busy(dev);
0274     if (status)
0275         return status;
0276 
0277     return i2c_dw_check_stopbit(dev);
0278 }
0279 
0280 /*
0281  * Initiate and continue master read/write transaction with polling
0282  * based transfer routine afterward write messages into the Tx buffer.
0283  */
0284 static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
0285 {
0286     struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
0287     int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
0288     int cmd = 0, status;
0289     u8 *tx_buf;
0290     u32 val;
0291 
0292     /*
0293      * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
0294      * it is mandatory to set the right value in specific register
0295      * (offset:0x474) as per the hardware IP specification.
0296      */
0297     regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
0298 
0299     dev->msgs = msgs;
0300     dev->msgs_num = num_msgs;
0301     i2c_dw_xfer_init(dev);
0302     i2c_dw_disable_int(dev);
0303 
0304     /* Initiate messages read/write transaction */
0305     for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
0306         tx_buf = msgs[msg_wrt_idx].buf;
0307         buf_len = msgs[msg_wrt_idx].len;
0308 
0309         if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
0310             regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
0311         /*
0312          * Initiate the i2c read/write transaction of buffer length,
0313          * and poll for bus busy status. For the last message transfer,
0314          * update the command with stopbit enable.
0315          */
0316         for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
0317             if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
0318                 cmd |= BIT(9);
0319 
0320             if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
0321                 /* Due to hardware bug, need to write the same command twice. */
0322                 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
0323                 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
0324                 if (cmd) {
0325                     regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
0326                     regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
0327                     /*
0328                      * Need to check the stop bit. However, it cannot be
0329                      * detected from the registers so we check it always
0330                      * when read/write the last byte.
0331                      */
0332                     status = i2c_dw_status(dev);
0333                     if (status)
0334                         return status;
0335 
0336                     for (data_idx = 0; data_idx < buf_len; data_idx++) {
0337                         regmap_read(dev->map, DW_IC_DATA_CMD, &val);
0338                         tx_buf[data_idx] = val;
0339                     }
0340                     status = i2c_dw_check_stopbit(dev);
0341                     if (status)
0342                         return status;
0343                 }
0344             } else {
0345                 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
0346                 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);
0347             }
0348         }
0349         status = i2c_dw_check_stopbit(dev);
0350         if (status)
0351             return status;
0352     }
0353 
0354     return 0;
0355 }
0356 
0357 /*
0358  * Initiate (and continue) low level master read/write transaction.
0359  * This function is only called from i2c_dw_isr, and pumping i2c_msg
0360  * messages into the tx buffer.  Even if the size of i2c_msg data is
0361  * longer than the size of the tx buffer, it handles everything.
0362  */
0363 static void
0364 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
0365 {
0366     struct i2c_msg *msgs = dev->msgs;
0367     u32 intr_mask;
0368     int tx_limit, rx_limit;
0369     u32 addr = msgs[dev->msg_write_idx].addr;
0370     u32 buf_len = dev->tx_buf_len;
0371     u8 *buf = dev->tx_buf;
0372     bool need_restart = false;
0373     unsigned int flr;
0374 
0375     intr_mask = DW_IC_INTR_MASTER_MASK;
0376 
0377     for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
0378         u32 flags = msgs[dev->msg_write_idx].flags;
0379 
0380         /*
0381          * If target address has changed, we need to
0382          * reprogram the target address in the I2C
0383          * adapter when we are done with this transfer.
0384          */
0385         if (msgs[dev->msg_write_idx].addr != addr) {
0386             dev_err(dev->dev,
0387                 "%s: invalid target address\n", __func__);
0388             dev->msg_err = -EINVAL;
0389             break;
0390         }
0391 
0392         if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
0393             /* new i2c_msg */
0394             buf = msgs[dev->msg_write_idx].buf;
0395             buf_len = msgs[dev->msg_write_idx].len;
0396 
0397             /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
0398              * IC_RESTART_EN are set, we must manually
0399              * set restart bit between messages.
0400              */
0401             if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
0402                     (dev->msg_write_idx > 0))
0403                 need_restart = true;
0404         }
0405 
0406         regmap_read(dev->map, DW_IC_TXFLR, &flr);
0407         tx_limit = dev->tx_fifo_depth - flr;
0408 
0409         regmap_read(dev->map, DW_IC_RXFLR, &flr);
0410         rx_limit = dev->rx_fifo_depth - flr;
0411 
0412         while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
0413             u32 cmd = 0;
0414 
0415             /*
0416              * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
0417              * manually set the stop bit. However, it cannot be
0418              * detected from the registers so we set it always
0419              * when writing/reading the last byte.
0420              */
0421 
0422             /*
0423              * i2c-core always sets the buffer length of
0424              * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
0425              * be adjusted when receiving the first byte.
0426              * Thus we can't stop the transaction here.
0427              */
0428             if (dev->msg_write_idx == dev->msgs_num - 1 &&
0429                 buf_len == 1 && !(flags & I2C_M_RECV_LEN))
0430                 cmd |= BIT(9);
0431 
0432             if (need_restart) {
0433                 cmd |= BIT(10);
0434                 need_restart = false;
0435             }
0436 
0437             if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
0438 
0439                 /* Avoid rx buffer overrun */
0440                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
0441                     break;
0442 
0443                 regmap_write(dev->map, DW_IC_DATA_CMD,
0444                          cmd | 0x100);
0445                 rx_limit--;
0446                 dev->rx_outstanding++;
0447             } else {
0448                 regmap_write(dev->map, DW_IC_DATA_CMD,
0449                          cmd | *buf++);
0450             }
0451             tx_limit--; buf_len--;
0452         }
0453 
0454         dev->tx_buf = buf;
0455         dev->tx_buf_len = buf_len;
0456 
0457         /*
0458          * Because we don't know the buffer length in the
0459          * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
0460          * the transaction here.
0461          */
0462         if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
0463             /* more bytes to be written */
0464             dev->status |= STATUS_WRITE_IN_PROGRESS;
0465             break;
0466         } else
0467             dev->status &= ~STATUS_WRITE_IN_PROGRESS;
0468     }
0469 
0470     /*
0471      * If i2c_msg index search is completed, we don't need TX_EMPTY
0472      * interrupt any more.
0473      */
0474     if (dev->msg_write_idx == dev->msgs_num)
0475         intr_mask &= ~DW_IC_INTR_TX_EMPTY;
0476 
0477     if (dev->msg_err)
0478         intr_mask = 0;
0479 
0480     regmap_write(dev->map,  DW_IC_INTR_MASK, intr_mask);
0481 }
0482 
0483 static u8
0484 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
0485 {
0486     struct i2c_msg *msgs = dev->msgs;
0487     u32 flags = msgs[dev->msg_read_idx].flags;
0488 
0489     /*
0490      * Adjust the buffer length and mask the flag
0491      * after receiving the first byte.
0492      */
0493     len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
0494     dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
0495     msgs[dev->msg_read_idx].len = len;
0496     msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
0497 
0498     return len;
0499 }
0500 
0501 static void
0502 i2c_dw_read(struct dw_i2c_dev *dev)
0503 {
0504     struct i2c_msg *msgs = dev->msgs;
0505     unsigned int rx_valid;
0506 
0507     for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
0508         u32 len, tmp;
0509         u8 *buf;
0510 
0511         if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
0512             continue;
0513 
0514         if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
0515             len = msgs[dev->msg_read_idx].len;
0516             buf = msgs[dev->msg_read_idx].buf;
0517         } else {
0518             len = dev->rx_buf_len;
0519             buf = dev->rx_buf;
0520         }
0521 
0522         regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
0523 
0524         for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
0525             u32 flags = msgs[dev->msg_read_idx].flags;
0526 
0527             regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
0528             /* Ensure length byte is a valid value */
0529             if (flags & I2C_M_RECV_LEN &&
0530                 (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
0531                 len = i2c_dw_recv_len(dev, tmp);
0532             }
0533             *buf++ = tmp;
0534             dev->rx_outstanding--;
0535         }
0536 
0537         if (len > 0) {
0538             dev->status |= STATUS_READ_IN_PROGRESS;
0539             dev->rx_buf_len = len;
0540             dev->rx_buf = buf;
0541             return;
0542         } else
0543             dev->status &= ~STATUS_READ_IN_PROGRESS;
0544     }
0545 }
0546 
0547 /*
0548  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
0549  */
0550 static int
0551 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0552 {
0553     struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
0554     int ret;
0555 
0556     dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
0557 
0558     pm_runtime_get_sync(dev->dev);
0559 
0560     /*
0561      * Initiate I2C message transfer when AMD NAVI GPU card is enabled,
0562      * As it is polling based transfer mechanism, which does not support
0563      * interrupt based functionalities of existing DesignWare driver.
0564      */
0565     if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
0566         ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
0567         goto done_nolock;
0568     }
0569 
0570     reinit_completion(&dev->cmd_complete);
0571     dev->msgs = msgs;
0572     dev->msgs_num = num;
0573     dev->cmd_err = 0;
0574     dev->msg_write_idx = 0;
0575     dev->msg_read_idx = 0;
0576     dev->msg_err = 0;
0577     dev->status = STATUS_IDLE;
0578     dev->abort_source = 0;
0579     dev->rx_outstanding = 0;
0580 
0581     ret = i2c_dw_acquire_lock(dev);
0582     if (ret)
0583         goto done_nolock;
0584 
0585     ret = i2c_dw_wait_bus_not_busy(dev);
0586     if (ret < 0)
0587         goto done;
0588 
0589     /* Start the transfers */
0590     i2c_dw_xfer_init(dev);
0591 
0592     /* Wait for tx to complete */
0593     if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
0594         dev_err(dev->dev, "controller timed out\n");
0595         /* i2c_dw_init implicitly disables the adapter */
0596         i2c_recover_bus(&dev->adapter);
0597         i2c_dw_init_master(dev);
0598         ret = -ETIMEDOUT;
0599         goto done;
0600     }
0601 
0602     /*
0603      * We must disable the adapter before returning and signaling the end
0604      * of the current transfer. Otherwise the hardware might continue
0605      * generating interrupts which in turn causes a race condition with
0606      * the following transfer.  Needs some more investigation if the
0607      * additional interrupts are a hardware bug or this driver doesn't
0608      * handle them correctly yet.
0609      */
0610     __i2c_dw_disable_nowait(dev);
0611 
0612     if (dev->msg_err) {
0613         ret = dev->msg_err;
0614         goto done;
0615     }
0616 
0617     /* No error */
0618     if (likely(!dev->cmd_err && !dev->status)) {
0619         ret = num;
0620         goto done;
0621     }
0622 
0623     /* We have an error */
0624     if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
0625         ret = i2c_dw_handle_tx_abort(dev);
0626         goto done;
0627     }
0628 
0629     if (dev->status)
0630         dev_err(dev->dev,
0631             "transfer terminated early - interrupt latency too high?\n");
0632 
0633     ret = -EIO;
0634 
0635 done:
0636     i2c_dw_release_lock(dev);
0637 
0638 done_nolock:
0639     pm_runtime_mark_last_busy(dev->dev);
0640     pm_runtime_put_autosuspend(dev->dev);
0641 
0642     return ret;
0643 }
0644 
0645 static const struct i2c_algorithm i2c_dw_algo = {
0646     .master_xfer = i2c_dw_xfer,
0647     .functionality = i2c_dw_func,
0648 };
0649 
0650 static const struct i2c_adapter_quirks i2c_dw_quirks = {
0651     .flags = I2C_AQ_NO_ZERO_LEN,
0652 };
0653 
0654 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
0655 {
0656     u32 stat, dummy;
0657 
0658     /*
0659      * The IC_INTR_STAT register just indicates "enabled" interrupts.
0660      * The unmasked raw version of interrupt status bits is available
0661      * in the IC_RAW_INTR_STAT register.
0662      *
0663      * That is,
0664      *   stat = readl(IC_INTR_STAT);
0665      * equals to,
0666      *   stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
0667      *
0668      * The raw version might be useful for debugging purposes.
0669      */
0670     regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
0671 
0672     /*
0673      * Do not use the IC_CLR_INTR register to clear interrupts, or
0674      * you'll miss some interrupts, triggered during the period from
0675      * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
0676      *
0677      * Instead, use the separately-prepared IC_CLR_* registers.
0678      */
0679     if (stat & DW_IC_INTR_RX_UNDER)
0680         regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
0681     if (stat & DW_IC_INTR_RX_OVER)
0682         regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
0683     if (stat & DW_IC_INTR_TX_OVER)
0684         regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
0685     if (stat & DW_IC_INTR_RD_REQ)
0686         regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
0687     if (stat & DW_IC_INTR_TX_ABRT) {
0688         /*
0689          * The IC_TX_ABRT_SOURCE register is cleared whenever
0690          * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
0691          */
0692         regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
0693         regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
0694     }
0695     if (stat & DW_IC_INTR_RX_DONE)
0696         regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
0697     if (stat & DW_IC_INTR_ACTIVITY)
0698         regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
0699     if ((stat & DW_IC_INTR_STOP_DET) &&
0700         ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
0701         regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
0702     if (stat & DW_IC_INTR_START_DET)
0703         regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
0704     if (stat & DW_IC_INTR_GEN_CALL)
0705         regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
0706 
0707     return stat;
0708 }
0709 
0710 /*
0711  * Interrupt service routine. This gets called whenever an I2C master interrupt
0712  * occurs.
0713  */
0714 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
0715 {
0716     u32 stat;
0717 
0718     stat = i2c_dw_read_clear_intrbits(dev);
0719     if (stat & DW_IC_INTR_TX_ABRT) {
0720         dev->cmd_err |= DW_IC_ERR_TX_ABRT;
0721         dev->status = STATUS_IDLE;
0722         dev->rx_outstanding = 0;
0723 
0724         /*
0725          * Anytime TX_ABRT is set, the contents of the tx/rx
0726          * buffers are flushed. Make sure to skip them.
0727          */
0728         regmap_write(dev->map, DW_IC_INTR_MASK, 0);
0729         goto tx_aborted;
0730     }
0731 
0732     if (stat & DW_IC_INTR_RX_FULL)
0733         i2c_dw_read(dev);
0734 
0735     if (stat & DW_IC_INTR_TX_EMPTY)
0736         i2c_dw_xfer_msg(dev);
0737 
0738     /*
0739      * No need to modify or disable the interrupt mask here.
0740      * i2c_dw_xfer_msg() will take care of it according to
0741      * the current transmit status.
0742      */
0743 
0744 tx_aborted:
0745     if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) &&
0746          (dev->rx_outstanding == 0))
0747         complete(&dev->cmd_complete);
0748     else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
0749         /* Workaround to trigger pending interrupt */
0750         regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
0751         i2c_dw_disable_int(dev);
0752         regmap_write(dev->map, DW_IC_INTR_MASK, stat);
0753     }
0754 
0755     return 0;
0756 }
0757 
0758 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
0759 {
0760     struct dw_i2c_dev *dev = dev_id;
0761     u32 stat, enabled;
0762 
0763     regmap_read(dev->map, DW_IC_ENABLE, &enabled);
0764     regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
0765     dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
0766     if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
0767         return IRQ_NONE;
0768 
0769     i2c_dw_irq_handler_master(dev);
0770 
0771     return IRQ_HANDLED;
0772 }
0773 
0774 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
0775 {
0776     struct i2c_timings *t = &dev->timings;
0777 
0778     dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
0779 
0780     dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
0781               DW_IC_CON_RESTART_EN;
0782 
0783     dev->mode = DW_IC_MASTER;
0784 
0785     switch (t->bus_freq_hz) {
0786     case I2C_MAX_STANDARD_MODE_FREQ:
0787         dev->master_cfg |= DW_IC_CON_SPEED_STD;
0788         break;
0789     case I2C_MAX_HIGH_SPEED_MODE_FREQ:
0790         dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
0791         break;
0792     default:
0793         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
0794     }
0795 }
0796 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
0797 
0798 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
0799 {
0800     struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
0801 
0802     i2c_dw_disable(dev);
0803     reset_control_assert(dev->rst);
0804     i2c_dw_prepare_clk(dev, false);
0805 }
0806 
0807 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
0808 {
0809     struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
0810 
0811     i2c_dw_prepare_clk(dev, true);
0812     reset_control_deassert(dev->rst);
0813     i2c_dw_init_master(dev);
0814 }
0815 
0816 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
0817 {
0818     struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
0819     struct i2c_adapter *adap = &dev->adapter;
0820     struct gpio_desc *gpio;
0821 
0822     gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
0823     if (IS_ERR_OR_NULL(gpio))
0824         return PTR_ERR_OR_ZERO(gpio);
0825 
0826     rinfo->scl_gpiod = gpio;
0827 
0828     gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
0829     if (IS_ERR(gpio))
0830         return PTR_ERR(gpio);
0831     rinfo->sda_gpiod = gpio;
0832 
0833     rinfo->recover_bus = i2c_generic_scl_recovery;
0834     rinfo->prepare_recovery = i2c_dw_prepare_recovery;
0835     rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
0836     adap->bus_recovery_info = rinfo;
0837 
0838     dev_info(dev->dev, "running with gpio recovery mode! scl%s",
0839          rinfo->sda_gpiod ? ",sda" : "");
0840 
0841     return 0;
0842 }
0843 
0844 static int amd_i2c_adap_quirk(struct dw_i2c_dev *dev)
0845 {
0846     struct i2c_adapter *adap = &dev->adapter;
0847     int ret;
0848 
0849     pm_runtime_get_noresume(dev->dev);
0850     ret = i2c_add_numbered_adapter(adap);
0851     if (ret)
0852         dev_err(dev->dev, "Failed to add adapter: %d\n", ret);
0853     pm_runtime_put_noidle(dev->dev);
0854 
0855     return ret;
0856 }
0857 
0858 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
0859 {
0860     struct i2c_adapter *adap = &dev->adapter;
0861     unsigned long irq_flags;
0862     int ret;
0863 
0864     init_completion(&dev->cmd_complete);
0865 
0866     dev->init = i2c_dw_init_master;
0867     dev->disable = i2c_dw_disable;
0868     dev->disable_int = i2c_dw_disable_int;
0869 
0870     ret = i2c_dw_init_regmap(dev);
0871     if (ret)
0872         return ret;
0873 
0874     ret = i2c_dw_set_timings_master(dev);
0875     if (ret)
0876         return ret;
0877 
0878     ret = i2c_dw_set_fifo_size(dev);
0879     if (ret)
0880         return ret;
0881 
0882     ret = dev->init(dev);
0883     if (ret)
0884         return ret;
0885 
0886     snprintf(adap->name, sizeof(adap->name),
0887          "Synopsys DesignWare I2C adapter");
0888     adap->retries = 3;
0889     adap->algo = &i2c_dw_algo;
0890     adap->quirks = &i2c_dw_quirks;
0891     adap->dev.parent = dev->dev;
0892     i2c_set_adapdata(adap, dev);
0893 
0894     if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
0895         return amd_i2c_adap_quirk(dev);
0896 
0897     if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
0898         irq_flags = IRQF_NO_SUSPEND;
0899     } else {
0900         irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
0901     }
0902 
0903     ret = i2c_dw_acquire_lock(dev);
0904     if (ret)
0905         return ret;
0906 
0907     i2c_dw_disable_int(dev);
0908     i2c_dw_release_lock(dev);
0909 
0910     ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
0911                    dev_name(dev->dev), dev);
0912     if (ret) {
0913         dev_err(dev->dev, "failure requesting irq %i: %d\n",
0914             dev->irq, ret);
0915         return ret;
0916     }
0917 
0918     ret = i2c_dw_init_recovery_info(dev);
0919     if (ret)
0920         return ret;
0921 
0922     /*
0923      * Increment PM usage count during adapter registration in order to
0924      * avoid possible spurious runtime suspend when adapter device is
0925      * registered to the device core and immediate resume in case bus has
0926      * registered I2C slaves that do I2C transfers in their probe.
0927      */
0928     pm_runtime_get_noresume(dev->dev);
0929     ret = i2c_add_numbered_adapter(adap);
0930     if (ret)
0931         dev_err(dev->dev, "failure adding adapter: %d\n", ret);
0932     pm_runtime_put_noidle(dev->dev);
0933 
0934     return ret;
0935 }
0936 EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
0937 
0938 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
0939 MODULE_LICENSE("GPL");
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