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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Synopsys DesignWare I2C adapter driver.
0004  *
0005  * Based on the TI DAVINCI I2C adapter driver.
0006  *
0007  * Copyright (C) 2006 Texas Instruments.
0008  * Copyright (C) 2007 MontaVista Software Inc.
0009  * Copyright (C) 2009 Provigent Ltd.
0010  */
0011 
0012 #include <linux/bits.h>
0013 #include <linux/compiler_types.h>
0014 #include <linux/completion.h>
0015 #include <linux/dev_printk.h>
0016 #include <linux/errno.h>
0017 #include <linux/i2c.h>
0018 #include <linux/regmap.h>
0019 #include <linux/types.h>
0020 
0021 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |         \
0022                     I2C_FUNC_SMBUS_BYTE |       \
0023                     I2C_FUNC_SMBUS_BYTE_DATA |  \
0024                     I2C_FUNC_SMBUS_WORD_DATA |  \
0025                     I2C_FUNC_SMBUS_BLOCK_DATA | \
0026                     I2C_FUNC_SMBUS_I2C_BLOCK)
0027 
0028 #define DW_IC_CON_MASTER            BIT(0)
0029 #define DW_IC_CON_SPEED_STD         (1 << 1)
0030 #define DW_IC_CON_SPEED_FAST            (2 << 1)
0031 #define DW_IC_CON_SPEED_HIGH            (3 << 1)
0032 #define DW_IC_CON_SPEED_MASK            GENMASK(2, 1)
0033 #define DW_IC_CON_10BITADDR_SLAVE       BIT(3)
0034 #define DW_IC_CON_10BITADDR_MASTER      BIT(4)
0035 #define DW_IC_CON_RESTART_EN            BIT(5)
0036 #define DW_IC_CON_SLAVE_DISABLE         BIT(6)
0037 #define DW_IC_CON_STOP_DET_IFADDRESSED      BIT(7)
0038 #define DW_IC_CON_TX_EMPTY_CTRL         BIT(8)
0039 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL     BIT(9)
0040 
0041 #define DW_IC_DATA_CMD_DAT          GENMASK(7, 0)
0042 
0043 /*
0044  * Registers offset
0045  */
0046 #define DW_IC_CON       0x00
0047 #define DW_IC_TAR       0x04
0048 #define DW_IC_SAR       0x08
0049 #define DW_IC_DATA_CMD      0x10
0050 #define DW_IC_SS_SCL_HCNT   0x14
0051 #define DW_IC_SS_SCL_LCNT   0x18
0052 #define DW_IC_FS_SCL_HCNT   0x1c
0053 #define DW_IC_FS_SCL_LCNT   0x20
0054 #define DW_IC_HS_SCL_HCNT   0x24
0055 #define DW_IC_HS_SCL_LCNT   0x28
0056 #define DW_IC_INTR_STAT     0x2c
0057 #define DW_IC_INTR_MASK     0x30
0058 #define DW_IC_RAW_INTR_STAT 0x34
0059 #define DW_IC_RX_TL     0x38
0060 #define DW_IC_TX_TL     0x3c
0061 #define DW_IC_CLR_INTR      0x40
0062 #define DW_IC_CLR_RX_UNDER  0x44
0063 #define DW_IC_CLR_RX_OVER   0x48
0064 #define DW_IC_CLR_TX_OVER   0x4c
0065 #define DW_IC_CLR_RD_REQ    0x50
0066 #define DW_IC_CLR_TX_ABRT   0x54
0067 #define DW_IC_CLR_RX_DONE   0x58
0068 #define DW_IC_CLR_ACTIVITY  0x5c
0069 #define DW_IC_CLR_STOP_DET  0x60
0070 #define DW_IC_CLR_START_DET 0x64
0071 #define DW_IC_CLR_GEN_CALL  0x68
0072 #define DW_IC_ENABLE        0x6c
0073 #define DW_IC_STATUS        0x70
0074 #define DW_IC_TXFLR     0x74
0075 #define DW_IC_RXFLR     0x78
0076 #define DW_IC_SDA_HOLD      0x7c
0077 #define DW_IC_TX_ABRT_SOURCE    0x80
0078 #define DW_IC_ENABLE_STATUS 0x9c
0079 #define DW_IC_CLR_RESTART_DET   0xa8
0080 #define DW_IC_COMP_PARAM_1  0xf4
0081 #define DW_IC_COMP_VERSION  0xf8
0082 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
0083 #define DW_IC_COMP_TYPE     0xfc
0084 #define DW_IC_COMP_TYPE_VALUE   0x44570140
0085 
0086 #define DW_IC_INTR_RX_UNDER BIT(0)
0087 #define DW_IC_INTR_RX_OVER  BIT(1)
0088 #define DW_IC_INTR_RX_FULL  BIT(2)
0089 #define DW_IC_INTR_TX_OVER  BIT(3)
0090 #define DW_IC_INTR_TX_EMPTY BIT(4)
0091 #define DW_IC_INTR_RD_REQ   BIT(5)
0092 #define DW_IC_INTR_TX_ABRT  BIT(6)
0093 #define DW_IC_INTR_RX_DONE  BIT(7)
0094 #define DW_IC_INTR_ACTIVITY BIT(8)
0095 #define DW_IC_INTR_STOP_DET BIT(9)
0096 #define DW_IC_INTR_START_DET    BIT(10)
0097 #define DW_IC_INTR_GEN_CALL BIT(11)
0098 #define DW_IC_INTR_RESTART_DET  BIT(12)
0099 
0100 #define DW_IC_INTR_DEFAULT_MASK     (DW_IC_INTR_RX_FULL | \
0101                      DW_IC_INTR_TX_ABRT | \
0102                      DW_IC_INTR_STOP_DET)
0103 #define DW_IC_INTR_MASTER_MASK      (DW_IC_INTR_DEFAULT_MASK | \
0104                      DW_IC_INTR_TX_EMPTY)
0105 #define DW_IC_INTR_SLAVE_MASK       (DW_IC_INTR_DEFAULT_MASK | \
0106                      DW_IC_INTR_RX_DONE | \
0107                      DW_IC_INTR_RX_UNDER | \
0108                      DW_IC_INTR_RD_REQ)
0109 
0110 #define DW_IC_STATUS_ACTIVITY       BIT(0)
0111 #define DW_IC_STATUS_TFE        BIT(2)
0112 #define DW_IC_STATUS_MASTER_ACTIVITY    BIT(5)
0113 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
0114 
0115 #define DW_IC_SDA_HOLD_RX_SHIFT     16
0116 #define DW_IC_SDA_HOLD_RX_MASK      GENMASK(23, 16)
0117 
0118 #define DW_IC_ERR_TX_ABRT   0x1
0119 
0120 #define DW_IC_TAR_10BITADDR_MASTER  BIT(12)
0121 
0122 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH  (BIT(2) | BIT(3))
0123 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK  GENMASK(3, 2)
0124 
0125 /*
0126  * status codes
0127  */
0128 #define STATUS_IDLE         0x0
0129 #define STATUS_WRITE_IN_PROGRESS    0x1
0130 #define STATUS_READ_IN_PROGRESS     0x2
0131 
0132 /*
0133  * operation modes
0134  */
0135 #define DW_IC_MASTER        0
0136 #define DW_IC_SLAVE     1
0137 
0138 /*
0139  * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
0140  *
0141  * Only expected abort codes are listed here
0142  * refer to the datasheet for the full list
0143  */
0144 #define ABRT_7B_ADDR_NOACK  0
0145 #define ABRT_10ADDR1_NOACK  1
0146 #define ABRT_10ADDR2_NOACK  2
0147 #define ABRT_TXDATA_NOACK   3
0148 #define ABRT_GCALL_NOACK    4
0149 #define ABRT_GCALL_READ     5
0150 #define ABRT_SBYTE_ACKDET   7
0151 #define ABRT_SBYTE_NORSTRT  9
0152 #define ABRT_10B_RD_NORSTRT 10
0153 #define ABRT_MASTER_DIS     11
0154 #define ARB_LOST        12
0155 #define ABRT_SLAVE_FLUSH_TXFIFO 13
0156 #define ABRT_SLAVE_ARBLOST  14
0157 #define ABRT_SLAVE_RD_INTX  15
0158 
0159 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     BIT(ABRT_7B_ADDR_NOACK)
0160 #define DW_IC_TX_ABRT_10ADDR1_NOACK     BIT(ABRT_10ADDR1_NOACK)
0161 #define DW_IC_TX_ABRT_10ADDR2_NOACK     BIT(ABRT_10ADDR2_NOACK)
0162 #define DW_IC_TX_ABRT_TXDATA_NOACK      BIT(ABRT_TXDATA_NOACK)
0163 #define DW_IC_TX_ABRT_GCALL_NOACK       BIT(ABRT_GCALL_NOACK)
0164 #define DW_IC_TX_ABRT_GCALL_READ        BIT(ABRT_GCALL_READ)
0165 #define DW_IC_TX_ABRT_SBYTE_ACKDET      BIT(ABRT_SBYTE_ACKDET)
0166 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     BIT(ABRT_SBYTE_NORSTRT)
0167 #define DW_IC_TX_ABRT_10B_RD_NORSTRT        BIT(ABRT_10B_RD_NORSTRT)
0168 #define DW_IC_TX_ABRT_MASTER_DIS        BIT(ABRT_MASTER_DIS)
0169 #define DW_IC_TX_ARB_LOST           BIT(ARB_LOST)
0170 #define DW_IC_RX_ABRT_SLAVE_RD_INTX     BIT(ABRT_SLAVE_RD_INTX)
0171 #define DW_IC_RX_ABRT_SLAVE_ARBLOST     BIT(ABRT_SLAVE_ARBLOST)
0172 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO    BIT(ABRT_SLAVE_FLUSH_TXFIFO)
0173 
0174 #define DW_IC_TX_ABRT_NOACK     (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
0175                      DW_IC_TX_ABRT_10ADDR1_NOACK | \
0176                      DW_IC_TX_ABRT_10ADDR2_NOACK | \
0177                      DW_IC_TX_ABRT_TXDATA_NOACK | \
0178                      DW_IC_TX_ABRT_GCALL_NOACK)
0179 
0180 struct clk;
0181 struct device;
0182 struct reset_control;
0183 
0184 /**
0185  * struct dw_i2c_dev - private i2c-designware data
0186  * @dev: driver model device node
0187  * @map: IO registers map
0188  * @sysmap: System controller registers map
0189  * @base: IO registers pointer
0190  * @ext: Extended IO registers pointer
0191  * @cmd_complete: tx completion indicator
0192  * @clk: input reference clock
0193  * @pclk: clock required to access the registers
0194  * @rst: optional reset for the controller
0195  * @slave: represent an I2C slave device
0196  * @get_clk_rate_khz: callback to retrieve IP specific bus speed
0197  * @cmd_err: run time hadware error code
0198  * @msgs: points to an array of messages currently being transferred
0199  * @msgs_num: the number of elements in msgs
0200  * @msg_write_idx: the element index of the current tx message in the msgs array
0201  * @tx_buf_len: the length of the current tx buffer
0202  * @tx_buf: the current tx buffer
0203  * @msg_read_idx: the element index of the current rx message in the msgs array
0204  * @rx_buf_len: the length of the current rx buffer
0205  * @rx_buf: the current rx buffer
0206  * @msg_err: error status of the current transfer
0207  * @status: i2c master status, one of STATUS_*
0208  * @abort_source: copy of the TX_ABRT_SOURCE register
0209  * @irq: interrupt number for the i2c master
0210  * @flags: platform specific flags like type of IO accessors or model
0211  * @adapter: i2c subsystem adapter node
0212  * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
0213  * @master_cfg: configuration for the master device
0214  * @slave_cfg: configuration for the slave device
0215  * @tx_fifo_depth: depth of the hardware tx fifo
0216  * @rx_fifo_depth: depth of the hardware rx fifo
0217  * @rx_outstanding: current master-rx elements in tx fifo
0218  * @timings: bus clock frequency, SDA hold and other timings
0219  * @sda_hold_time: SDA hold value
0220  * @ss_hcnt: standard speed HCNT value
0221  * @ss_lcnt: standard speed LCNT value
0222  * @fs_hcnt: fast speed HCNT value
0223  * @fs_lcnt: fast speed LCNT value
0224  * @fp_hcnt: fast plus HCNT value
0225  * @fp_lcnt: fast plus LCNT value
0226  * @hs_hcnt: high speed HCNT value
0227  * @hs_lcnt: high speed LCNT value
0228  * @acquire_lock: function to acquire a hardware lock on the bus
0229  * @release_lock: function to release a hardware lock on the bus
0230  * @semaphore_idx: Index of table with semaphore type attached to the bus. It's
0231  *  -1 if there is no semaphore.
0232  * @shared_with_punit: true if this bus is shared with the SoCs PUNIT
0233  * @disable: function to disable the controller
0234  * @disable_int: function to disable all interrupts
0235  * @init: function to initialize the I2C hardware
0236  * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
0237  * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
0238  * @rinfo: I²C GPIO recovery information
0239  *
0240  * HCNT and LCNT parameters can be used if the platform knows more accurate
0241  * values than the one computed based only on the input clock frequency.
0242  * Leave them to be %0 if not used.
0243  */
0244 struct dw_i2c_dev {
0245     struct device       *dev;
0246     struct regmap       *map;
0247     struct regmap       *sysmap;
0248     void __iomem        *base;
0249     void __iomem        *ext;
0250     struct completion   cmd_complete;
0251     struct clk      *clk;
0252     struct clk      *pclk;
0253     struct reset_control    *rst;
0254     struct i2c_client   *slave;
0255     u32         (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
0256     int         cmd_err;
0257     struct i2c_msg      *msgs;
0258     int         msgs_num;
0259     int         msg_write_idx;
0260     u32         tx_buf_len;
0261     u8          *tx_buf;
0262     int         msg_read_idx;
0263     u32         rx_buf_len;
0264     u8          *rx_buf;
0265     int         msg_err;
0266     unsigned int        status;
0267     u32         abort_source;
0268     int         irq;
0269     u32         flags;
0270     struct i2c_adapter  adapter;
0271     u32         functionality;
0272     u32         master_cfg;
0273     u32         slave_cfg;
0274     unsigned int        tx_fifo_depth;
0275     unsigned int        rx_fifo_depth;
0276     int         rx_outstanding;
0277     struct i2c_timings  timings;
0278     u32         sda_hold_time;
0279     u16         ss_hcnt;
0280     u16         ss_lcnt;
0281     u16         fs_hcnt;
0282     u16         fs_lcnt;
0283     u16         fp_hcnt;
0284     u16         fp_lcnt;
0285     u16         hs_hcnt;
0286     u16         hs_lcnt;
0287     int         (*acquire_lock)(void);
0288     void            (*release_lock)(void);
0289     int         semaphore_idx;
0290     bool            shared_with_punit;
0291     void            (*disable)(struct dw_i2c_dev *dev);
0292     void            (*disable_int)(struct dw_i2c_dev *dev);
0293     int         (*init)(struct dw_i2c_dev *dev);
0294     int         (*set_sda_hold_time)(struct dw_i2c_dev *dev);
0295     int         mode;
0296     struct i2c_bus_recovery_info rinfo;
0297 };
0298 
0299 #define ACCESS_INTR_MASK    BIT(0)
0300 #define ACCESS_NO_IRQ_SUSPEND   BIT(1)
0301 #define ARBITRATION_SEMAPHORE   BIT(2)
0302 
0303 #define MODEL_MSCC_OCELOT   BIT(8)
0304 #define MODEL_BAIKAL_BT1    BIT(9)
0305 #define MODEL_AMD_NAVI_GPU  BIT(10)
0306 #define MODEL_MASK      GENMASK(11, 8)
0307 
0308 /*
0309  * Enable UCSI interrupt by writing 0xd at register
0310  * offset 0x474 specified in hardware specification.
0311  */
0312 #define AMD_UCSI_INTR_REG   0x474
0313 #define AMD_UCSI_INTR_EN    0xd
0314 
0315 struct i2c_dw_semaphore_callbacks {
0316     int (*probe)(struct dw_i2c_dev *dev);
0317     void    (*remove)(struct dw_i2c_dev *dev);
0318 };
0319 
0320 int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
0321 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
0322 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
0323 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
0324 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev);
0325 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
0326 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
0327 void i2c_dw_release_lock(struct dw_i2c_dev *dev);
0328 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
0329 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
0330 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
0331 u32 i2c_dw_func(struct i2c_adapter *adap);
0332 void i2c_dw_disable(struct dw_i2c_dev *dev);
0333 void i2c_dw_disable_int(struct dw_i2c_dev *dev);
0334 
0335 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
0336 {
0337     regmap_write(dev->map, DW_IC_ENABLE, 1);
0338 }
0339 
0340 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
0341 {
0342     regmap_write(dev->map, DW_IC_ENABLE, 0);
0343 }
0344 
0345 void __i2c_dw_disable(struct dw_i2c_dev *dev);
0346 
0347 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
0348 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
0349 
0350 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
0351 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
0352 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
0353 #else
0354 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
0355 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
0356 #endif
0357 
0358 static inline int i2c_dw_probe(struct dw_i2c_dev *dev)
0359 {
0360     switch (dev->mode) {
0361     case DW_IC_SLAVE:
0362         return i2c_dw_probe_slave(dev);
0363     case DW_IC_MASTER:
0364         return i2c_dw_probe_master(dev);
0365     default:
0366         dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
0367         return -EINVAL;
0368     }
0369 }
0370 
0371 static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
0372 {
0373     if (i2c_detect_slave_mode(dev->dev))
0374         i2c_dw_configure_slave(dev);
0375     else
0376         i2c_dw_configure_master(dev);
0377 }
0378 
0379 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
0380 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
0381 #endif
0382 
0383 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
0384 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
0385 void i2c_dw_amdpsp_remove_lock_support(struct dw_i2c_dev *dev);
0386 #endif
0387 
0388 int i2c_dw_validate_speed(struct dw_i2c_dev *dev);
0389 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev);
0390 
0391 #if IS_ENABLED(CONFIG_ACPI)
0392 int i2c_dw_acpi_configure(struct device *device);
0393 #else
0394 static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; }
0395 #endif
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