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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Synopsys DesignWare I2C adapter driver.
0004  *
0005  * Based on the TI DAVINCI I2C adapter driver.
0006  *
0007  * Copyright (C) 2006 Texas Instruments.
0008  * Copyright (C) 2007 MontaVista Software Inc.
0009  * Copyright (C) 2009 Provigent Ltd.
0010  */
0011 #include <linux/acpi.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/err.h>
0016 #include <linux/errno.h>
0017 #include <linux/export.h>
0018 #include <linux/i2c.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/io.h>
0021 #include <linux/kernel.h>
0022 #include <linux/module.h>
0023 #include <linux/pm_runtime.h>
0024 #include <linux/regmap.h>
0025 #include <linux/swab.h>
0026 #include <linux/types.h>
0027 #include <linux/units.h>
0028 
0029 #include "i2c-designware-core.h"
0030 
0031 static char *abort_sources[] = {
0032     [ABRT_7B_ADDR_NOACK] =
0033         "slave address not acknowledged (7bit mode)",
0034     [ABRT_10ADDR1_NOACK] =
0035         "first address byte not acknowledged (10bit mode)",
0036     [ABRT_10ADDR2_NOACK] =
0037         "second address byte not acknowledged (10bit mode)",
0038     [ABRT_TXDATA_NOACK] =
0039         "data not acknowledged",
0040     [ABRT_GCALL_NOACK] =
0041         "no acknowledgement for a general call",
0042     [ABRT_GCALL_READ] =
0043         "read after general call",
0044     [ABRT_SBYTE_ACKDET] =
0045         "start byte acknowledged",
0046     [ABRT_SBYTE_NORSTRT] =
0047         "trying to send start byte when restart is disabled",
0048     [ABRT_10B_RD_NORSTRT] =
0049         "trying to read when restart is disabled (10bit mode)",
0050     [ABRT_MASTER_DIS] =
0051         "trying to use disabled adapter",
0052     [ARB_LOST] =
0053         "lost arbitration",
0054     [ABRT_SLAVE_FLUSH_TXFIFO] =
0055         "read command so flush old data in the TX FIFO",
0056     [ABRT_SLAVE_ARBLOST] =
0057         "slave lost the bus while transmitting data to a remote master",
0058     [ABRT_SLAVE_RD_INTX] =
0059         "incorrect slave-transmitter mode configuration",
0060 };
0061 
0062 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
0063 {
0064     struct dw_i2c_dev *dev = context;
0065 
0066     *val = readl_relaxed(dev->base + reg);
0067 
0068     return 0;
0069 }
0070 
0071 static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
0072 {
0073     struct dw_i2c_dev *dev = context;
0074 
0075     writel_relaxed(val, dev->base + reg);
0076 
0077     return 0;
0078 }
0079 
0080 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
0081 {
0082     struct dw_i2c_dev *dev = context;
0083 
0084     *val = swab32(readl_relaxed(dev->base + reg));
0085 
0086     return 0;
0087 }
0088 
0089 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
0090 {
0091     struct dw_i2c_dev *dev = context;
0092 
0093     writel_relaxed(swab32(val), dev->base + reg);
0094 
0095     return 0;
0096 }
0097 
0098 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
0099 {
0100     struct dw_i2c_dev *dev = context;
0101 
0102     *val = readw_relaxed(dev->base + reg) |
0103         (readw_relaxed(dev->base + reg + 2) << 16);
0104 
0105     return 0;
0106 }
0107 
0108 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
0109 {
0110     struct dw_i2c_dev *dev = context;
0111 
0112     writew_relaxed(val, dev->base + reg);
0113     writew_relaxed(val >> 16, dev->base + reg + 2);
0114 
0115     return 0;
0116 }
0117 
0118 /**
0119  * i2c_dw_init_regmap() - Initialize registers map
0120  * @dev: device private data
0121  *
0122  * Autodetects needed register access mode and creates the regmap with
0123  * corresponding read/write callbacks. This must be called before doing any
0124  * other register access.
0125  */
0126 int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
0127 {
0128     struct regmap_config map_cfg = {
0129         .reg_bits = 32,
0130         .val_bits = 32,
0131         .reg_stride = 4,
0132         .disable_locking = true,
0133         .reg_read = dw_reg_read,
0134         .reg_write = dw_reg_write,
0135         .max_register = DW_IC_COMP_TYPE,
0136     };
0137     u32 reg;
0138     int ret;
0139 
0140     /*
0141      * Skip detecting the registers map configuration if the regmap has
0142      * already been provided by a higher code.
0143      */
0144     if (dev->map)
0145         return 0;
0146 
0147     ret = i2c_dw_acquire_lock(dev);
0148     if (ret)
0149         return ret;
0150 
0151     reg = readl(dev->base + DW_IC_COMP_TYPE);
0152     i2c_dw_release_lock(dev);
0153 
0154     if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
0155         map_cfg.max_register = AMD_UCSI_INTR_REG;
0156 
0157     if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
0158         map_cfg.reg_read = dw_reg_read_swab;
0159         map_cfg.reg_write = dw_reg_write_swab;
0160     } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
0161         map_cfg.reg_read = dw_reg_read_word;
0162         map_cfg.reg_write = dw_reg_write_word;
0163     } else if (reg != DW_IC_COMP_TYPE_VALUE) {
0164         dev_err(dev->dev,
0165             "Unknown Synopsys component type: 0x%08x\n", reg);
0166         return -ENODEV;
0167     }
0168 
0169     /*
0170      * Note we'll check the return value of the regmap IO accessors only
0171      * at the probe stage. The rest of the code won't do this because
0172      * basically we have MMIO-based regmap so non of the read/write methods
0173      * can fail.
0174      */
0175     dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
0176     if (IS_ERR(dev->map)) {
0177         dev_err(dev->dev, "Failed to init the registers map\n");
0178         return PTR_ERR(dev->map);
0179     }
0180 
0181     return 0;
0182 }
0183 
0184 static const u32 supported_speeds[] = {
0185     I2C_MAX_HIGH_SPEED_MODE_FREQ,
0186     I2C_MAX_FAST_MODE_PLUS_FREQ,
0187     I2C_MAX_FAST_MODE_FREQ,
0188     I2C_MAX_STANDARD_MODE_FREQ,
0189 };
0190 
0191 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
0192 {
0193     struct i2c_timings *t = &dev->timings;
0194     unsigned int i;
0195 
0196     /*
0197      * Only standard mode at 100kHz, fast mode at 400kHz,
0198      * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
0199      */
0200     for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
0201         if (t->bus_freq_hz == supported_speeds[i])
0202             return 0;
0203     }
0204 
0205     dev_err(dev->dev,
0206         "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
0207         t->bus_freq_hz);
0208 
0209     return -EINVAL;
0210 }
0211 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
0212 
0213 #ifdef CONFIG_ACPI
0214 
0215 #include <linux/dmi.h>
0216 
0217 /*
0218  * The HCNT/LCNT information coming from ACPI should be the most accurate
0219  * for given platform. However, some systems get it wrong. On such systems
0220  * we get better results by calculating those based on the input clock.
0221  */
0222 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
0223     {
0224         .ident = "Dell Inspiron 7348",
0225         .matches = {
0226             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0227             DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
0228         },
0229     },
0230     {}
0231 };
0232 
0233 static void i2c_dw_acpi_params(struct device *device, char method[],
0234                    u16 *hcnt, u16 *lcnt, u32 *sda_hold)
0235 {
0236     struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
0237     acpi_handle handle = ACPI_HANDLE(device);
0238     union acpi_object *obj;
0239 
0240     if (dmi_check_system(i2c_dw_no_acpi_params))
0241         return;
0242 
0243     if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
0244         return;
0245 
0246     obj = (union acpi_object *)buf.pointer;
0247     if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
0248         const union acpi_object *objs = obj->package.elements;
0249 
0250         *hcnt = (u16)objs[0].integer.value;
0251         *lcnt = (u16)objs[1].integer.value;
0252         *sda_hold = (u32)objs[2].integer.value;
0253     }
0254 
0255     kfree(buf.pointer);
0256 }
0257 
0258 int i2c_dw_acpi_configure(struct device *device)
0259 {
0260     struct dw_i2c_dev *dev = dev_get_drvdata(device);
0261     struct i2c_timings *t = &dev->timings;
0262     u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
0263 
0264     /*
0265      * Try to get SDA hold time and *CNT values from an ACPI method for
0266      * selected speed modes.
0267      */
0268     i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
0269     i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
0270     i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
0271     i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
0272 
0273     switch (t->bus_freq_hz) {
0274     case I2C_MAX_STANDARD_MODE_FREQ:
0275         dev->sda_hold_time = ss_ht;
0276         break;
0277     case I2C_MAX_FAST_MODE_PLUS_FREQ:
0278         dev->sda_hold_time = fp_ht;
0279         break;
0280     case I2C_MAX_HIGH_SPEED_MODE_FREQ:
0281         dev->sda_hold_time = hs_ht;
0282         break;
0283     case I2C_MAX_FAST_MODE_FREQ:
0284     default:
0285         dev->sda_hold_time = fs_ht;
0286         break;
0287     }
0288 
0289     return 0;
0290 }
0291 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
0292 
0293 static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
0294 {
0295     u32 acpi_speed;
0296     int i;
0297 
0298     acpi_speed = i2c_acpi_find_bus_speed(device);
0299     /*
0300      * Some DSTDs use a non standard speed, round down to the lowest
0301      * standard speed.
0302      */
0303     for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
0304         if (acpi_speed >= supported_speeds[i])
0305             return supported_speeds[i];
0306     }
0307 
0308     return 0;
0309 }
0310 
0311 #else   /* CONFIG_ACPI */
0312 
0313 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
0314 
0315 #endif  /* CONFIG_ACPI */
0316 
0317 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
0318 {
0319     u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
0320     struct i2c_timings *t = &dev->timings;
0321 
0322     /*
0323      * Find bus speed from the "clock-frequency" device property, ACPI
0324      * or by using fast mode if neither is set.
0325      */
0326     if (acpi_speed && t->bus_freq_hz)
0327         t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
0328     else if (acpi_speed || t->bus_freq_hz)
0329         t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
0330     else
0331         t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
0332 }
0333 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
0334 
0335 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
0336 {
0337     /*
0338      * DesignWare I2C core doesn't seem to have solid strategy to meet
0339      * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
0340      * will result in violation of the tHD;STA spec.
0341      */
0342     if (cond)
0343         /*
0344          * Conditional expression:
0345          *
0346          *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
0347          *
0348          * This is based on the DW manuals, and represents an ideal
0349          * configuration.  The resulting I2C bus speed will be
0350          * faster than any of the others.
0351          *
0352          * If your hardware is free from tHD;STA issue, try this one.
0353          */
0354         return DIV_ROUND_CLOSEST(ic_clk * tSYMBOL, MICRO) - 8 + offset;
0355     else
0356         /*
0357          * Conditional expression:
0358          *
0359          *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
0360          *
0361          * This is just experimental rule; the tHD;STA period turned
0362          * out to be proportinal to (_HCNT + 3).  With this setting,
0363          * we could meet both tHIGH and tHD;STA timing specs.
0364          *
0365          * If unsure, you'd better to take this alternative.
0366          *
0367          * The reason why we need to take into account "tf" here,
0368          * is the same as described in i2c_dw_scl_lcnt().
0369          */
0370         return DIV_ROUND_CLOSEST(ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset;
0371 }
0372 
0373 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
0374 {
0375     /*
0376      * Conditional expression:
0377      *
0378      *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
0379      *
0380      * DW I2C core starts counting the SCL CNTs for the LOW period
0381      * of the SCL clock (tLOW) as soon as it pulls the SCL line.
0382      * In order to meet the tLOW timing spec, we need to take into
0383      * account the fall time of SCL signal (tf).  Default tf value
0384      * should be 0.3 us, for safety.
0385      */
0386     return DIV_ROUND_CLOSEST(ic_clk * (tLOW + tf), MICRO) - 1 + offset;
0387 }
0388 
0389 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
0390 {
0391     u32 reg;
0392     int ret;
0393 
0394     ret = i2c_dw_acquire_lock(dev);
0395     if (ret)
0396         return ret;
0397 
0398     /* Configure SDA Hold Time if required */
0399     ret = regmap_read(dev->map, DW_IC_COMP_VERSION, &reg);
0400     if (ret)
0401         goto err_release_lock;
0402 
0403     if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
0404         if (!dev->sda_hold_time) {
0405             /* Keep previous hold time setting if no one set it */
0406             ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
0407                       &dev->sda_hold_time);
0408             if (ret)
0409                 goto err_release_lock;
0410         }
0411 
0412         /*
0413          * Workaround for avoiding TX arbitration lost in case I2C
0414          * slave pulls SDA down "too quickly" after falling edge of
0415          * SCL by enabling non-zero SDA RX hold. Specification says it
0416          * extends incoming SDA low to high transition while SCL is
0417          * high but it appears to help also above issue.
0418          */
0419         if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
0420             dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
0421 
0422         dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
0423             dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
0424             dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
0425     } else if (dev->set_sda_hold_time) {
0426         dev->set_sda_hold_time(dev);
0427     } else if (dev->sda_hold_time) {
0428         dev_warn(dev->dev,
0429             "Hardware too old to adjust SDA hold time.\n");
0430         dev->sda_hold_time = 0;
0431     }
0432 
0433 err_release_lock:
0434     i2c_dw_release_lock(dev);
0435 
0436     return ret;
0437 }
0438 
0439 void __i2c_dw_disable(struct dw_i2c_dev *dev)
0440 {
0441     int timeout = 100;
0442     u32 status;
0443 
0444     do {
0445         __i2c_dw_disable_nowait(dev);
0446         /*
0447          * The enable status register may be unimplemented, but
0448          * in that case this test reads zero and exits the loop.
0449          */
0450         regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
0451         if ((status & 1) == 0)
0452             return;
0453 
0454         /*
0455          * Wait 10 times the signaling period of the highest I2C
0456          * transfer supported by the driver (for 400KHz this is
0457          * 25us) as described in the DesignWare I2C databook.
0458          */
0459         usleep_range(25, 250);
0460     } while (timeout--);
0461 
0462     dev_warn(dev->dev, "timeout in disabling adapter\n");
0463 }
0464 
0465 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
0466 {
0467     /*
0468      * Clock is not necessary if we got LCNT/HCNT values directly from
0469      * the platform code.
0470      */
0471     if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
0472         return 0;
0473     return dev->get_clk_rate_khz(dev);
0474 }
0475 
0476 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
0477 {
0478     int ret;
0479 
0480     if (prepare) {
0481         /* Optional interface clock */
0482         ret = clk_prepare_enable(dev->pclk);
0483         if (ret)
0484             return ret;
0485 
0486         ret = clk_prepare_enable(dev->clk);
0487         if (ret)
0488             clk_disable_unprepare(dev->pclk);
0489 
0490         return ret;
0491     }
0492 
0493     clk_disable_unprepare(dev->clk);
0494     clk_disable_unprepare(dev->pclk);
0495 
0496     return 0;
0497 }
0498 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
0499 
0500 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
0501 {
0502     int ret;
0503 
0504     if (!dev->acquire_lock)
0505         return 0;
0506 
0507     ret = dev->acquire_lock();
0508     if (!ret)
0509         return 0;
0510 
0511     dev_err(dev->dev, "couldn't acquire bus ownership\n");
0512 
0513     return ret;
0514 }
0515 
0516 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
0517 {
0518     if (dev->release_lock)
0519         dev->release_lock();
0520 }
0521 
0522 /*
0523  * Waiting for bus not busy
0524  */
0525 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
0526 {
0527     u32 status;
0528     int ret;
0529 
0530     ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
0531                        !(status & DW_IC_STATUS_ACTIVITY),
0532                        1100, 20000);
0533     if (ret) {
0534         dev_warn(dev->dev, "timeout waiting for bus ready\n");
0535 
0536         i2c_recover_bus(&dev->adapter);
0537 
0538         regmap_read(dev->map, DW_IC_STATUS, &status);
0539         if (!(status & DW_IC_STATUS_ACTIVITY))
0540             ret = 0;
0541     }
0542 
0543     return ret;
0544 }
0545 
0546 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
0547 {
0548     unsigned long abort_source = dev->abort_source;
0549     int i;
0550 
0551     if (abort_source & DW_IC_TX_ABRT_NOACK) {
0552         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
0553             dev_dbg(dev->dev,
0554                 "%s: %s\n", __func__, abort_sources[i]);
0555         return -EREMOTEIO;
0556     }
0557 
0558     for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
0559         dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
0560 
0561     if (abort_source & DW_IC_TX_ARB_LOST)
0562         return -EAGAIN;
0563     else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
0564         return -EINVAL; /* wrong msgs[] data */
0565     else
0566         return -EIO;
0567 }
0568 
0569 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
0570 {
0571     u32 param, tx_fifo_depth, rx_fifo_depth;
0572     int ret;
0573 
0574     /*
0575      * Try to detect the FIFO depth if not set by interface driver,
0576      * the depth could be from 2 to 256 from HW spec.
0577      */
0578     ret = i2c_dw_acquire_lock(dev);
0579     if (ret)
0580         return ret;
0581 
0582     ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &param);
0583     i2c_dw_release_lock(dev);
0584     if (ret)
0585         return ret;
0586 
0587     tx_fifo_depth = ((param >> 16) & 0xff) + 1;
0588     rx_fifo_depth = ((param >> 8)  & 0xff) + 1;
0589     if (!dev->tx_fifo_depth) {
0590         dev->tx_fifo_depth = tx_fifo_depth;
0591         dev->rx_fifo_depth = rx_fifo_depth;
0592     } else if (tx_fifo_depth >= 2) {
0593         dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
0594                 tx_fifo_depth);
0595         dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
0596                 rx_fifo_depth);
0597     }
0598 
0599     return 0;
0600 }
0601 
0602 u32 i2c_dw_func(struct i2c_adapter *adap)
0603 {
0604     struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
0605 
0606     return dev->functionality;
0607 }
0608 
0609 void i2c_dw_disable(struct dw_i2c_dev *dev)
0610 {
0611     u32 dummy;
0612     int ret;
0613 
0614     ret = i2c_dw_acquire_lock(dev);
0615     if (ret)
0616         return;
0617 
0618     /* Disable controller */
0619     __i2c_dw_disable(dev);
0620 
0621     /* Disable all interrupts */
0622     regmap_write(dev->map, DW_IC_INTR_MASK, 0);
0623     regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
0624 
0625     i2c_dw_release_lock(dev);
0626 }
0627 
0628 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
0629 {
0630     regmap_write(dev->map, DW_IC_INTR_MASK, 0);
0631 }
0632 
0633 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
0634 MODULE_LICENSE("GPL");
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