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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * TI DAVINCI I2C adapter driver.
0004  *
0005  * Copyright (C) 2006 Texas Instruments.
0006  * Copyright (C) 2007 MontaVista Software Inc.
0007  *
0008  * Updated by Vinod & Sudhakar Feb 2005
0009  *
0010  * ----------------------------------------------------------------------------
0011  *
0012  * ----------------------------------------------------------------------------
0013  */
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/delay.h>
0017 #include <linux/i2c.h>
0018 #include <linux/clk.h>
0019 #include <linux/errno.h>
0020 #include <linux/sched.h>
0021 #include <linux/err.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/io.h>
0025 #include <linux/slab.h>
0026 #include <linux/cpufreq.h>
0027 #include <linux/gpio/consumer.h>
0028 #include <linux/of_device.h>
0029 #include <linux/platform_data/i2c-davinci.h>
0030 #include <linux/pm_runtime.h>
0031 
0032 /* ----- global defines ----------------------------------------------- */
0033 
0034 #define DAVINCI_I2C_TIMEOUT (1*HZ)
0035 #define DAVINCI_I2C_MAX_TRIES   2
0036 #define DAVINCI_I2C_OWN_ADDRESS 0x08
0037 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_SCD | \
0038                  DAVINCI_I2C_IMR_ARDY | \
0039                  DAVINCI_I2C_IMR_NACK | \
0040                  DAVINCI_I2C_IMR_AL)
0041 
0042 #define DAVINCI_I2C_OAR_REG 0x00
0043 #define DAVINCI_I2C_IMR_REG 0x04
0044 #define DAVINCI_I2C_STR_REG 0x08
0045 #define DAVINCI_I2C_CLKL_REG    0x0c
0046 #define DAVINCI_I2C_CLKH_REG    0x10
0047 #define DAVINCI_I2C_CNT_REG 0x14
0048 #define DAVINCI_I2C_DRR_REG 0x18
0049 #define DAVINCI_I2C_SAR_REG 0x1c
0050 #define DAVINCI_I2C_DXR_REG 0x20
0051 #define DAVINCI_I2C_MDR_REG 0x24
0052 #define DAVINCI_I2C_IVR_REG 0x28
0053 #define DAVINCI_I2C_EMDR_REG    0x2c
0054 #define DAVINCI_I2C_PSC_REG 0x30
0055 #define DAVINCI_I2C_FUNC_REG    0x48
0056 #define DAVINCI_I2C_DIR_REG 0x4c
0057 #define DAVINCI_I2C_DIN_REG 0x50
0058 #define DAVINCI_I2C_DOUT_REG    0x54
0059 #define DAVINCI_I2C_DSET_REG    0x58
0060 #define DAVINCI_I2C_DCLR_REG    0x5c
0061 
0062 #define DAVINCI_I2C_IVR_AAS 0x07
0063 #define DAVINCI_I2C_IVR_SCD 0x06
0064 #define DAVINCI_I2C_IVR_XRDY    0x05
0065 #define DAVINCI_I2C_IVR_RDR 0x04
0066 #define DAVINCI_I2C_IVR_ARDY    0x03
0067 #define DAVINCI_I2C_IVR_NACK    0x02
0068 #define DAVINCI_I2C_IVR_AL  0x01
0069 
0070 #define DAVINCI_I2C_STR_BB  BIT(12)
0071 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
0072 #define DAVINCI_I2C_STR_SCD BIT(5)
0073 #define DAVINCI_I2C_STR_ARDY    BIT(2)
0074 #define DAVINCI_I2C_STR_NACK    BIT(1)
0075 #define DAVINCI_I2C_STR_AL  BIT(0)
0076 
0077 #define DAVINCI_I2C_MDR_NACK    BIT(15)
0078 #define DAVINCI_I2C_MDR_STT BIT(13)
0079 #define DAVINCI_I2C_MDR_STP BIT(11)
0080 #define DAVINCI_I2C_MDR_MST BIT(10)
0081 #define DAVINCI_I2C_MDR_TRX BIT(9)
0082 #define DAVINCI_I2C_MDR_XA  BIT(8)
0083 #define DAVINCI_I2C_MDR_RM  BIT(7)
0084 #define DAVINCI_I2C_MDR_IRS BIT(5)
0085 
0086 #define DAVINCI_I2C_IMR_AAS BIT(6)
0087 #define DAVINCI_I2C_IMR_SCD BIT(5)
0088 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
0089 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
0090 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
0091 #define DAVINCI_I2C_IMR_NACK    BIT(1)
0092 #define DAVINCI_I2C_IMR_AL  BIT(0)
0093 
0094 /* set SDA and SCL as GPIO */
0095 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
0096 
0097 /* set SCL as output when used as GPIO*/
0098 #define DAVINCI_I2C_DIR_PDIR0   BIT(0)
0099 /* set SDA as output when used as GPIO*/
0100 #define DAVINCI_I2C_DIR_PDIR1   BIT(1)
0101 
0102 /* read SCL GPIO level */
0103 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
0104 /* read SDA GPIO level */
0105 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
0106 
0107 /*set the SCL GPIO high */
0108 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
0109 /*set the SDA GPIO high */
0110 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
0111 
0112 /* set the SCL GPIO low */
0113 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
0114 /* set the SDA GPIO low */
0115 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
0116 
0117 /* timeout for pm runtime autosuspend */
0118 #define DAVINCI_I2C_PM_TIMEOUT  1000    /* ms */
0119 
0120 struct davinci_i2c_dev {
0121     struct device           *dev;
0122     void __iomem        *base;
0123     struct completion   cmd_complete;
0124     struct clk              *clk;
0125     int         cmd_err;
0126     u8          *buf;
0127     size_t          buf_len;
0128     int         irq;
0129     int         stop;
0130     u8          terminate;
0131     struct i2c_adapter  adapter;
0132 #ifdef CONFIG_CPU_FREQ
0133     struct notifier_block   freq_transition;
0134 #endif
0135     struct davinci_i2c_platform_data *pdata;
0136 };
0137 
0138 /* default platform data to use if not supplied in the platform_device */
0139 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
0140     .bus_freq   = 100,
0141     .bus_delay  = 0,
0142 };
0143 
0144 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
0145                      int reg, u16 val)
0146 {
0147     writew_relaxed(val, i2c_dev->base + reg);
0148 }
0149 
0150 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
0151 {
0152     return readw_relaxed(i2c_dev->base + reg);
0153 }
0154 
0155 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
0156                                 int val)
0157 {
0158     u16 w;
0159 
0160     w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
0161     if (!val)   /* put I2C into reset */
0162         w &= ~DAVINCI_I2C_MDR_IRS;
0163     else        /* take I2C out of reset */
0164         w |= DAVINCI_I2C_MDR_IRS;
0165 
0166     davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
0167 }
0168 
0169 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
0170 {
0171     struct davinci_i2c_platform_data *pdata = dev->pdata;
0172     u16 psc;
0173     u32 clk;
0174     u32 d;
0175     u32 clkh;
0176     u32 clkl;
0177     u32 input_clock = clk_get_rate(dev->clk);
0178     struct device_node *of_node = dev->dev->of_node;
0179 
0180     /* NOTE: I2C Clock divider programming info
0181      * As per I2C specs the following formulas provide prescaler
0182      * and low/high divider values
0183      * input clk --> PSC Div -----------> ICCL/H Div --> output clock
0184      *                       module clk
0185      *
0186      * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
0187      *
0188      * Thus,
0189      * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
0190      *
0191      * where if PSC == 0, d = 7,
0192      *       if PSC == 1, d = 6
0193      *       if PSC > 1 , d = 5
0194      *
0195      * Note:
0196      * d is always 6 on Keystone I2C controller
0197      */
0198 
0199     /*
0200      * Both Davinci and current Keystone User Guides recommend a value
0201      * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
0202      * always produce enough margin between SDA and SCL transitions.
0203      * Measurements show that the higher the module clock is, the
0204      * bigger is the margin, providing more reliable communication.
0205      * So we better target for 12MHz.
0206      */
0207     psc = (input_clock / 12000000) - 1;
0208     if ((input_clock / (psc + 1)) > 12000000)
0209         psc++;  /* better to run under spec than over */
0210     d = (psc >= 2) ? 5 : 7 - psc;
0211 
0212     if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
0213         d = 6;
0214 
0215     clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
0216     /* Avoid driving the bus too fast because of rounding errors above */
0217     if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
0218         clk++;
0219     /*
0220      * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
0221      * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
0222      * to LOW ratio as 1 to 2 is more safe.
0223      */
0224     if (pdata->bus_freq > 100)
0225         clkl = (clk << 1) / 3;
0226     else
0227         clkl = (clk >> 1);
0228     /*
0229      * It's not always possible to have 1 to 2 ratio when d=7, so fall back
0230      * to minimal possible clkh in this case.
0231      *
0232      * Note:
0233      * CLKH is not allowed to be 0, in this case I2C clock is not generated
0234      * at all
0235      */
0236     if (clk > clkl + d) {
0237         clkh = clk - clkl - d;
0238         clkl -= d;
0239     } else {
0240         clkh = 1;
0241         clkl = clk - (d << 1);
0242     }
0243 
0244     davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
0245     davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
0246     davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
0247 
0248     dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
0249 }
0250 
0251 /*
0252  * This function configures I2C and brings I2C out of reset.
0253  * This function is called during I2C init function. This function
0254  * also gets called if I2C encounters any errors.
0255  */
0256 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
0257 {
0258     struct davinci_i2c_platform_data *pdata = dev->pdata;
0259 
0260     /* put I2C into reset */
0261     davinci_i2c_reset_ctrl(dev, 0);
0262 
0263     /* compute clock dividers */
0264     i2c_davinci_calc_clk_dividers(dev);
0265 
0266     /* Respond at reserved "SMBus Host" slave address" (and zero);
0267      * we seem to have no option to not respond...
0268      */
0269     davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
0270 
0271     dev_dbg(dev->dev, "PSC  = %d\n",
0272         davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
0273     dev_dbg(dev->dev, "CLKL = %d\n",
0274         davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
0275     dev_dbg(dev->dev, "CLKH = %d\n",
0276         davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
0277     dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
0278         pdata->bus_freq, pdata->bus_delay);
0279 
0280 
0281     /* Take the I2C module out of reset: */
0282     davinci_i2c_reset_ctrl(dev, 1);
0283 
0284     /* Enable interrupts */
0285     davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
0286 
0287     return 0;
0288 }
0289 
0290 /*
0291  * This routine does i2c bus recovery by using i2c_generic_scl_recovery
0292  * which is provided by I2C Bus recovery infrastructure.
0293  */
0294 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
0295 {
0296     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0297 
0298     /* Disable interrupts */
0299     davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
0300 
0301     /* put I2C into reset */
0302     davinci_i2c_reset_ctrl(dev, 0);
0303 }
0304 
0305 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
0306 {
0307     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0308 
0309     i2c_davinci_init(dev);
0310 }
0311 
0312 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
0313     .recover_bus = i2c_generic_scl_recovery,
0314     .prepare_recovery = davinci_i2c_prepare_recovery,
0315     .unprepare_recovery = davinci_i2c_unprepare_recovery,
0316 };
0317 
0318 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
0319 {
0320     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0321 
0322     if (val)
0323         davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
0324                       DAVINCI_I2C_DSET_PDSET0);
0325     else
0326         davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
0327                       DAVINCI_I2C_DCLR_PDCLR0);
0328 }
0329 
0330 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
0331 {
0332     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0333     int val;
0334 
0335     /* read the state of SCL */
0336     val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
0337     return val & DAVINCI_I2C_DIN_PDIN0;
0338 }
0339 
0340 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
0341 {
0342     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0343     int val;
0344 
0345     /* read the state of SDA */
0346     val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
0347     return val & DAVINCI_I2C_DIN_PDIN1;
0348 }
0349 
0350 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
0351 {
0352     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0353 
0354     davinci_i2c_prepare_recovery(adap);
0355 
0356     /* SCL output, SDA input */
0357     davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
0358 
0359     /* change to GPIO mode */
0360     davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
0361                   DAVINCI_I2C_FUNC_PFUNC0);
0362 }
0363 
0364 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
0365 {
0366     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0367 
0368     /* change back to I2C mode */
0369     davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
0370 
0371     davinci_i2c_unprepare_recovery(adap);
0372 }
0373 
0374 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
0375     .recover_bus = i2c_generic_scl_recovery,
0376     .set_scl = davinci_i2c_set_scl,
0377     .get_scl = davinci_i2c_get_scl,
0378     .get_sda = davinci_i2c_get_sda,
0379     .prepare_recovery = davinci_i2c_scl_prepare_recovery,
0380     .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
0381 };
0382 
0383 /*
0384  * Waiting for bus not busy
0385  */
0386 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
0387 {
0388     unsigned long timeout = jiffies + dev->adapter.timeout;
0389 
0390     do {
0391         if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
0392             return 0;
0393         schedule_timeout_uninterruptible(1);
0394     } while (time_before_eq(jiffies, timeout));
0395 
0396     dev_warn(dev->dev, "timeout waiting for bus ready\n");
0397     i2c_recover_bus(&dev->adapter);
0398 
0399     /*
0400      * if bus is still "busy" here, it's most probably a HW problem like
0401      * short-circuit
0402      */
0403     if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
0404         return -EIO;
0405 
0406     return 0;
0407 }
0408 
0409 /*
0410  * Low level master read/write transaction. This function is called
0411  * from i2c_davinci_xfer.
0412  */
0413 static int
0414 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
0415 {
0416     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0417     struct davinci_i2c_platform_data *pdata = dev->pdata;
0418     u32 flag;
0419     u16 w;
0420     unsigned long time_left;
0421 
0422     if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
0423         dev_warn(dev->dev, "transfer to own address aborted\n");
0424         return -EADDRNOTAVAIL;
0425     }
0426 
0427     /* Introduce a delay, required for some boards (e.g Davinci EVM) */
0428     if (pdata->bus_delay)
0429         udelay(pdata->bus_delay);
0430 
0431     /* set the slave address */
0432     davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
0433 
0434     dev->buf = msg->buf;
0435     dev->buf_len = msg->len;
0436     dev->stop = stop;
0437 
0438     davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
0439 
0440     reinit_completion(&dev->cmd_complete);
0441     dev->cmd_err = 0;
0442 
0443     /* Take I2C out of reset and configure it as master */
0444     flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
0445 
0446     /* if the slave address is ten bit address, enable XA bit */
0447     if (msg->flags & I2C_M_TEN)
0448         flag |= DAVINCI_I2C_MDR_XA;
0449     if (!(msg->flags & I2C_M_RD))
0450         flag |= DAVINCI_I2C_MDR_TRX;
0451     if (msg->len == 0)
0452         flag |= DAVINCI_I2C_MDR_RM;
0453 
0454     /* Enable receive or transmit interrupts */
0455     w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
0456     if (msg->flags & I2C_M_RD)
0457         w |= DAVINCI_I2C_IMR_RRDY;
0458     else
0459         w |= DAVINCI_I2C_IMR_XRDY;
0460     davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
0461 
0462     dev->terminate = 0;
0463 
0464     /*
0465      * Write mode register first as needed for correct behaviour
0466      * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
0467      * occurring before we have loaded DXR
0468      */
0469     davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
0470 
0471     /*
0472      * First byte should be set here, not after interrupt,
0473      * because transmit-data-ready interrupt can come before
0474      * NACK-interrupt during sending of previous message and
0475      * ICDXR may have wrong data
0476      * It also saves us one interrupt, slightly faster
0477      */
0478     if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
0479         davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
0480         dev->buf_len--;
0481     }
0482 
0483     /* Set STT to begin transmit now DXR is loaded */
0484     flag |= DAVINCI_I2C_MDR_STT;
0485     if (stop && msg->len != 0)
0486         flag |= DAVINCI_I2C_MDR_STP;
0487     davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
0488 
0489     time_left = wait_for_completion_timeout(&dev->cmd_complete,
0490                         dev->adapter.timeout);
0491     if (!time_left) {
0492         dev_err(dev->dev, "controller timed out\n");
0493         i2c_recover_bus(adap);
0494         dev->buf_len = 0;
0495         return -ETIMEDOUT;
0496     }
0497     if (dev->buf_len) {
0498         /* This should be 0 if all bytes were transferred
0499          * or dev->cmd_err denotes an error.
0500          */
0501         dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
0502             dev->buf_len);
0503         dev->terminate = 1;
0504         wmb();
0505         dev->buf_len = 0;
0506         return -EREMOTEIO;
0507     }
0508 
0509     /* no error */
0510     if (likely(!dev->cmd_err))
0511         return msg->len;
0512 
0513     /* We have an error */
0514     if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
0515         i2c_davinci_init(dev);
0516         return -EIO;
0517     }
0518 
0519     if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
0520         if (msg->flags & I2C_M_IGNORE_NAK)
0521             return msg->len;
0522         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
0523         w |= DAVINCI_I2C_MDR_STP;
0524         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
0525         return -EREMOTEIO;
0526     }
0527     return -EIO;
0528 }
0529 
0530 /*
0531  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
0532  */
0533 static int
0534 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0535 {
0536     struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
0537     int i;
0538     int ret;
0539 
0540     dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
0541 
0542     ret = pm_runtime_resume_and_get(dev->dev);
0543     if (ret < 0) {
0544         dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
0545         return ret;
0546     }
0547 
0548     ret = i2c_davinci_wait_bus_not_busy(dev);
0549     if (ret < 0) {
0550         dev_warn(dev->dev, "timeout waiting for bus ready\n");
0551         goto out;
0552     }
0553 
0554     for (i = 0; i < num; i++) {
0555         ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
0556         dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
0557             ret);
0558         if (ret < 0)
0559             goto out;
0560     }
0561 
0562     ret = num;
0563 
0564 out:
0565     pm_runtime_mark_last_busy(dev->dev);
0566     pm_runtime_put_autosuspend(dev->dev);
0567 
0568     return ret;
0569 }
0570 
0571 static u32 i2c_davinci_func(struct i2c_adapter *adap)
0572 {
0573     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0574 }
0575 
0576 static void terminate_read(struct davinci_i2c_dev *dev)
0577 {
0578     u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
0579     w |= DAVINCI_I2C_MDR_NACK;
0580     davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
0581 
0582     /* Throw away data */
0583     davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
0584     if (!dev->terminate)
0585         dev_err(dev->dev, "RDR IRQ while no data requested\n");
0586 }
0587 static void terminate_write(struct davinci_i2c_dev *dev)
0588 {
0589     u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
0590     w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
0591     davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
0592 
0593     if (!dev->terminate)
0594         dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
0595 }
0596 
0597 /*
0598  * Interrupt service routine. This gets called whenever an I2C interrupt
0599  * occurs.
0600  */
0601 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
0602 {
0603     struct davinci_i2c_dev *dev = dev_id;
0604     u32 stat;
0605     int count = 0;
0606     u16 w;
0607 
0608     if (pm_runtime_suspended(dev->dev))
0609         return IRQ_NONE;
0610 
0611     while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
0612         dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
0613         if (count++ == 100) {
0614             dev_warn(dev->dev, "Too much work in one IRQ\n");
0615             break;
0616         }
0617 
0618         switch (stat) {
0619         case DAVINCI_I2C_IVR_AL:
0620             /* Arbitration lost, must retry */
0621             dev->cmd_err |= DAVINCI_I2C_STR_AL;
0622             dev->buf_len = 0;
0623             complete(&dev->cmd_complete);
0624             break;
0625 
0626         case DAVINCI_I2C_IVR_NACK:
0627             dev->cmd_err |= DAVINCI_I2C_STR_NACK;
0628             dev->buf_len = 0;
0629             complete(&dev->cmd_complete);
0630             break;
0631 
0632         case DAVINCI_I2C_IVR_ARDY:
0633             davinci_i2c_write_reg(dev,
0634                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
0635             if (((dev->buf_len == 0) && (dev->stop != 0)) ||
0636                 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
0637                 w = davinci_i2c_read_reg(dev,
0638                              DAVINCI_I2C_MDR_REG);
0639                 w |= DAVINCI_I2C_MDR_STP;
0640                 davinci_i2c_write_reg(dev,
0641                               DAVINCI_I2C_MDR_REG, w);
0642             }
0643             complete(&dev->cmd_complete);
0644             break;
0645 
0646         case DAVINCI_I2C_IVR_RDR:
0647             if (dev->buf_len) {
0648                 *dev->buf++ =
0649                     davinci_i2c_read_reg(dev,
0650                              DAVINCI_I2C_DRR_REG);
0651                 dev->buf_len--;
0652                 if (dev->buf_len)
0653                     continue;
0654 
0655                 davinci_i2c_write_reg(dev,
0656                     DAVINCI_I2C_STR_REG,
0657                     DAVINCI_I2C_IMR_RRDY);
0658             } else {
0659                 /* signal can terminate transfer */
0660                 terminate_read(dev);
0661             }
0662             break;
0663 
0664         case DAVINCI_I2C_IVR_XRDY:
0665             if (dev->buf_len) {
0666                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
0667                               *dev->buf++);
0668                 dev->buf_len--;
0669                 if (dev->buf_len)
0670                     continue;
0671 
0672                 w = davinci_i2c_read_reg(dev,
0673                              DAVINCI_I2C_IMR_REG);
0674                 w &= ~DAVINCI_I2C_IMR_XRDY;
0675                 davinci_i2c_write_reg(dev,
0676                               DAVINCI_I2C_IMR_REG,
0677                               w);
0678             } else {
0679                 /* signal can terminate transfer */
0680                 terminate_write(dev);
0681             }
0682             break;
0683 
0684         case DAVINCI_I2C_IVR_SCD:
0685             davinci_i2c_write_reg(dev,
0686                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
0687             complete(&dev->cmd_complete);
0688             break;
0689 
0690         case DAVINCI_I2C_IVR_AAS:
0691             dev_dbg(dev->dev, "Address as slave interrupt\n");
0692             break;
0693 
0694         default:
0695             dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
0696             break;
0697         }
0698     }
0699 
0700     return count ? IRQ_HANDLED : IRQ_NONE;
0701 }
0702 
0703 #ifdef CONFIG_CPU_FREQ
0704 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
0705                      unsigned long val, void *data)
0706 {
0707     struct davinci_i2c_dev *dev;
0708 
0709     dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
0710 
0711     i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
0712     if (val == CPUFREQ_PRECHANGE) {
0713         davinci_i2c_reset_ctrl(dev, 0);
0714     } else if (val == CPUFREQ_POSTCHANGE) {
0715         i2c_davinci_calc_clk_dividers(dev);
0716         davinci_i2c_reset_ctrl(dev, 1);
0717     }
0718     i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
0719 
0720     return 0;
0721 }
0722 
0723 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
0724 {
0725     dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
0726 
0727     return cpufreq_register_notifier(&dev->freq_transition,
0728                      CPUFREQ_TRANSITION_NOTIFIER);
0729 }
0730 
0731 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
0732 {
0733     cpufreq_unregister_notifier(&dev->freq_transition,
0734                     CPUFREQ_TRANSITION_NOTIFIER);
0735 }
0736 #else
0737 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
0738 {
0739     return 0;
0740 }
0741 
0742 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
0743 {
0744 }
0745 #endif
0746 
0747 static const struct i2c_algorithm i2c_davinci_algo = {
0748     .master_xfer    = i2c_davinci_xfer,
0749     .functionality  = i2c_davinci_func,
0750 };
0751 
0752 static const struct of_device_id davinci_i2c_of_match[] = {
0753     {.compatible = "ti,davinci-i2c", },
0754     {.compatible = "ti,keystone-i2c", },
0755     {},
0756 };
0757 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
0758 
0759 static int davinci_i2c_probe(struct platform_device *pdev)
0760 {
0761     struct davinci_i2c_dev *dev;
0762     struct i2c_adapter *adap;
0763     struct i2c_bus_recovery_info *rinfo;
0764     int r, irq;
0765 
0766     irq = platform_get_irq(pdev, 0);
0767     if (irq <= 0) {
0768         if (!irq)
0769             irq = -ENXIO;
0770         return dev_err_probe(&pdev->dev, irq, "can't get irq resource\n");
0771     }
0772 
0773     dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
0774             GFP_KERNEL);
0775     if (!dev) {
0776         dev_err(&pdev->dev, "Memory allocation failed\n");
0777         return -ENOMEM;
0778     }
0779 
0780     init_completion(&dev->cmd_complete);
0781 
0782     dev->dev = &pdev->dev;
0783     dev->irq = irq;
0784     dev->pdata = dev_get_platdata(&pdev->dev);
0785     platform_set_drvdata(pdev, dev);
0786 
0787     if (!dev->pdata && pdev->dev.of_node) {
0788         u32 prop;
0789 
0790         dev->pdata = devm_kzalloc(&pdev->dev,
0791             sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
0792         if (!dev->pdata)
0793             return -ENOMEM;
0794 
0795         memcpy(dev->pdata, &davinci_i2c_platform_data_default,
0796             sizeof(struct davinci_i2c_platform_data));
0797         if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
0798             &prop))
0799             dev->pdata->bus_freq = prop / 1000;
0800 
0801         dev->pdata->has_pfunc =
0802             of_property_read_bool(pdev->dev.of_node,
0803                           "ti,has-pfunc");
0804     } else if (!dev->pdata) {
0805         dev->pdata = &davinci_i2c_platform_data_default;
0806     }
0807 
0808     dev->clk = devm_clk_get(&pdev->dev, NULL);
0809     if (IS_ERR(dev->clk))
0810         return PTR_ERR(dev->clk);
0811 
0812     dev->base = devm_platform_ioremap_resource(pdev, 0);
0813     if (IS_ERR(dev->base)) {
0814         return PTR_ERR(dev->base);
0815     }
0816 
0817     pm_runtime_set_autosuspend_delay(dev->dev,
0818                      DAVINCI_I2C_PM_TIMEOUT);
0819     pm_runtime_use_autosuspend(dev->dev);
0820 
0821     pm_runtime_enable(dev->dev);
0822 
0823     r = pm_runtime_resume_and_get(dev->dev);
0824     if (r < 0) {
0825         dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
0826         goto err_pm;
0827     }
0828 
0829     i2c_davinci_init(dev);
0830 
0831     r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
0832             pdev->name, dev);
0833     if (r) {
0834         dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
0835         goto err_unuse_clocks;
0836     }
0837 
0838     r = i2c_davinci_cpufreq_register(dev);
0839     if (r) {
0840         dev_err(&pdev->dev, "failed to register cpufreq\n");
0841         goto err_unuse_clocks;
0842     }
0843 
0844     adap = &dev->adapter;
0845     i2c_set_adapdata(adap, dev);
0846     adap->owner = THIS_MODULE;
0847     adap->class = I2C_CLASS_DEPRECATED;
0848     strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
0849     adap->algo = &i2c_davinci_algo;
0850     adap->dev.parent = &pdev->dev;
0851     adap->timeout = DAVINCI_I2C_TIMEOUT;
0852     adap->dev.of_node = pdev->dev.of_node;
0853 
0854     if (dev->pdata->has_pfunc)
0855         adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
0856     else if (dev->pdata->gpio_recovery) {
0857         rinfo =  &davinci_i2c_gpio_recovery_info;
0858         adap->bus_recovery_info = rinfo;
0859         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
0860                           GPIOD_OUT_HIGH_OPEN_DRAIN);
0861         if (IS_ERR(rinfo->scl_gpiod)) {
0862             r = PTR_ERR(rinfo->scl_gpiod);
0863             goto err_unuse_clocks;
0864         }
0865         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
0866         if (IS_ERR(rinfo->sda_gpiod)) {
0867             r = PTR_ERR(rinfo->sda_gpiod);
0868             goto err_unuse_clocks;
0869         }
0870     }
0871 
0872     adap->nr = pdev->id;
0873     r = i2c_add_numbered_adapter(adap);
0874     if (r)
0875         goto err_unuse_clocks;
0876 
0877     pm_runtime_mark_last_busy(dev->dev);
0878     pm_runtime_put_autosuspend(dev->dev);
0879 
0880     return 0;
0881 
0882 err_unuse_clocks:
0883     pm_runtime_dont_use_autosuspend(dev->dev);
0884     pm_runtime_put_sync(dev->dev);
0885 err_pm:
0886     pm_runtime_disable(dev->dev);
0887 
0888     return r;
0889 }
0890 
0891 static int davinci_i2c_remove(struct platform_device *pdev)
0892 {
0893     struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
0894     int ret;
0895 
0896     i2c_davinci_cpufreq_deregister(dev);
0897 
0898     i2c_del_adapter(&dev->adapter);
0899 
0900     ret = pm_runtime_resume_and_get(&pdev->dev);
0901     if (ret < 0)
0902         return ret;
0903 
0904     davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
0905 
0906     pm_runtime_dont_use_autosuspend(dev->dev);
0907     pm_runtime_put_sync(dev->dev);
0908     pm_runtime_disable(dev->dev);
0909 
0910     return 0;
0911 }
0912 
0913 #ifdef CONFIG_PM
0914 static int davinci_i2c_suspend(struct device *dev)
0915 {
0916     struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
0917 
0918     /* put I2C into reset */
0919     davinci_i2c_reset_ctrl(i2c_dev, 0);
0920 
0921     return 0;
0922 }
0923 
0924 static int davinci_i2c_resume(struct device *dev)
0925 {
0926     struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
0927 
0928     /* take I2C out of reset */
0929     davinci_i2c_reset_ctrl(i2c_dev, 1);
0930 
0931     return 0;
0932 }
0933 
0934 static const struct dev_pm_ops davinci_i2c_pm = {
0935     .suspend        = davinci_i2c_suspend,
0936     .resume         = davinci_i2c_resume,
0937     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0938                       pm_runtime_force_resume)
0939 };
0940 
0941 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
0942 #else
0943 #define davinci_i2c_pm_ops NULL
0944 #endif
0945 
0946 /* work with hotplug and coldplug */
0947 MODULE_ALIAS("platform:i2c_davinci");
0948 
0949 static struct platform_driver davinci_i2c_driver = {
0950     .probe      = davinci_i2c_probe,
0951     .remove     = davinci_i2c_remove,
0952     .driver     = {
0953         .name   = "i2c_davinci",
0954         .pm = davinci_i2c_pm_ops,
0955         .of_match_table = davinci_i2c_of_match,
0956     },
0957 };
0958 
0959 /* I2C may be needed to bring up other drivers */
0960 static int __init davinci_i2c_init_driver(void)
0961 {
0962     return platform_driver_register(&davinci_i2c_driver);
0963 }
0964 subsys_initcall(davinci_i2c_init_driver);
0965 
0966 static void __exit davinci_i2c_exit_driver(void)
0967 {
0968     platform_driver_unregister(&davinci_i2c_driver);
0969 }
0970 module_exit(davinci_i2c_exit_driver);
0971 
0972 MODULE_AUTHOR("Texas Instruments India");
0973 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
0974 MODULE_LICENSE("GPL");
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