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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale CPM1/CPM2 I2C interface.
0004  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
0005  *
0006  * moved into proper i2c interface;
0007  * Brad Parker (brad@heeltoe.com)
0008  *
0009  * Parts from dbox2_i2c.c (cvs.tuxbox.org)
0010  * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
0011  *
0012  * (C) 2007 Montavista Software, Inc.
0013  * Vitaly Bordug <vitb@kernel.crashing.org>
0014  *
0015  * Converted to of_platform_device. Renamed to i2c-cpm.c.
0016  * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/delay.h>
0022 #include <linux/slab.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/errno.h>
0025 #include <linux/stddef.h>
0026 #include <linux/i2c.h>
0027 #include <linux/io.h>
0028 #include <linux/dma-mapping.h>
0029 #include <linux/of_address.h>
0030 #include <linux/of_device.h>
0031 #include <linux/of_irq.h>
0032 #include <linux/of_platform.h>
0033 #include <sysdev/fsl_soc.h>
0034 #include <asm/cpm.h>
0035 
0036 /* Try to define this if you have an older CPU (earlier than rev D4) */
0037 /* However, better use a GPIO based bitbang driver in this case :/   */
0038 #undef  I2C_CHIP_ERRATA
0039 
0040 #define CPM_MAX_READ    513
0041 #define CPM_MAXBD       4
0042 
0043 #define I2C_EB          (0x10) /* Big endian mode */
0044 #define I2C_EB_CPM2     (0x30) /* Big endian mode, memory snoop */
0045 
0046 #define DPRAM_BASE      ((u8 __iomem __force *)cpm_muram_addr(0))
0047 
0048 /* I2C parameter RAM. */
0049 struct i2c_ram {
0050     ushort  rbase;      /* Rx Buffer descriptor base address */
0051     ushort  tbase;      /* Tx Buffer descriptor base address */
0052     u_char  rfcr;       /* Rx function code */
0053     u_char  tfcr;       /* Tx function code */
0054     ushort  mrblr;      /* Max receive buffer length */
0055     uint    rstate;     /* Internal */
0056     uint    rdp;        /* Internal */
0057     ushort  rbptr;      /* Rx Buffer descriptor pointer */
0058     ushort  rbc;        /* Internal */
0059     uint    rxtmp;      /* Internal */
0060     uint    tstate;     /* Internal */
0061     uint    tdp;        /* Internal */
0062     ushort  tbptr;      /* Tx Buffer descriptor pointer */
0063     ushort  tbc;        /* Internal */
0064     uint    txtmp;      /* Internal */
0065     char    res1[4];    /* Reserved */
0066     ushort  rpbase;     /* Relocation pointer */
0067     char    res2[2];    /* Reserved */
0068     /* The following elements are only for CPM2 */
0069     char    res3[4];    /* Reserved */
0070     uint    sdmatmp;    /* Internal */
0071 };
0072 
0073 #define I2COM_START 0x80
0074 #define I2COM_MASTER    0x01
0075 #define I2CER_TXE   0x10
0076 #define I2CER_BUSY  0x04
0077 #define I2CER_TXB   0x02
0078 #define I2CER_RXB   0x01
0079 #define I2MOD_EN    0x01
0080 
0081 /* I2C Registers */
0082 struct i2c_reg {
0083     u8  i2mod;
0084     u8  res1[3];
0085     u8  i2add;
0086     u8  res2[3];
0087     u8  i2brg;
0088     u8  res3[3];
0089     u8  i2com;
0090     u8  res4[3];
0091     u8  i2cer;
0092     u8  res5[3];
0093     u8  i2cmr;
0094 };
0095 
0096 struct cpm_i2c {
0097     char *base;
0098     struct platform_device *ofdev;
0099     struct i2c_adapter adap;
0100     uint dp_addr;
0101     int version; /* CPM1=1, CPM2=2 */
0102     int irq;
0103     int cp_command;
0104     int freq;
0105     struct i2c_reg __iomem *i2c_reg;
0106     struct i2c_ram __iomem *i2c_ram;
0107     u16 i2c_addr;
0108     wait_queue_head_t i2c_wait;
0109     cbd_t __iomem *tbase;
0110     cbd_t __iomem *rbase;
0111     u_char *txbuf[CPM_MAXBD];
0112     u_char *rxbuf[CPM_MAXBD];
0113     dma_addr_t txdma[CPM_MAXBD];
0114     dma_addr_t rxdma[CPM_MAXBD];
0115 };
0116 
0117 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
0118 {
0119     struct cpm_i2c *cpm;
0120     struct i2c_reg __iomem *i2c_reg;
0121     struct i2c_adapter *adap = dev_id;
0122     int i;
0123 
0124     cpm = i2c_get_adapdata(dev_id);
0125     i2c_reg = cpm->i2c_reg;
0126 
0127     /* Clear interrupt. */
0128     i = in_8(&i2c_reg->i2cer);
0129     out_8(&i2c_reg->i2cer, i);
0130 
0131     dev_dbg(&adap->dev, "Interrupt: %x\n", i);
0132 
0133     wake_up(&cpm->i2c_wait);
0134 
0135     return i ? IRQ_HANDLED : IRQ_NONE;
0136 }
0137 
0138 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
0139 {
0140     struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
0141 
0142     /* Set up the I2C parameters in the parameter ram. */
0143     out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
0144     out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
0145 
0146     if (cpm->version == 1) {
0147         out_8(&i2c_ram->tfcr, I2C_EB);
0148         out_8(&i2c_ram->rfcr, I2C_EB);
0149     } else {
0150         out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
0151         out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
0152     }
0153 
0154     out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
0155 
0156     out_be32(&i2c_ram->rstate, 0);
0157     out_be32(&i2c_ram->rdp, 0);
0158     out_be16(&i2c_ram->rbptr, 0);
0159     out_be16(&i2c_ram->rbc, 0);
0160     out_be32(&i2c_ram->rxtmp, 0);
0161     out_be32(&i2c_ram->tstate, 0);
0162     out_be32(&i2c_ram->tdp, 0);
0163     out_be16(&i2c_ram->tbptr, 0);
0164     out_be16(&i2c_ram->tbc, 0);
0165     out_be32(&i2c_ram->txtmp, 0);
0166 }
0167 
0168 static void cpm_i2c_force_close(struct i2c_adapter *adap)
0169 {
0170     struct cpm_i2c *cpm = i2c_get_adapdata(adap);
0171     struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
0172 
0173     dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
0174 
0175     cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
0176 
0177     out_8(&i2c_reg->i2cmr, 0x00);   /* Disable all interrupts */
0178     out_8(&i2c_reg->i2cer, 0xff);
0179 }
0180 
0181 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
0182     struct i2c_msg *pmsg, int num, int tx, int rx)
0183 {
0184     cbd_t __iomem *tbdf;
0185     cbd_t __iomem *rbdf;
0186     u_char addr;
0187     u_char *tb;
0188     u_char *rb;
0189     struct cpm_i2c *cpm = i2c_get_adapdata(adap);
0190 
0191     tbdf = cpm->tbase + tx;
0192     rbdf = cpm->rbase + rx;
0193 
0194     addr = i2c_8bit_addr_from_msg(pmsg);
0195 
0196     tb = cpm->txbuf[tx];
0197     rb = cpm->rxbuf[rx];
0198 
0199     /* Align read buffer */
0200     rb = (u_char *) (((ulong) rb + 1) & ~1);
0201 
0202     tb[0] = addr;       /* Device address byte w/rw flag */
0203 
0204     out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
0205     out_be16(&tbdf->cbd_sc, 0);
0206 
0207     if (!(pmsg->flags & I2C_M_NOSTART))
0208         setbits16(&tbdf->cbd_sc, BD_I2C_START);
0209 
0210     if (tx + 1 == num)
0211         setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
0212 
0213     if (pmsg->flags & I2C_M_RD) {
0214         /*
0215          * To read, we need an empty buffer of the proper length.
0216          * All that is used is the first byte for address, the remainder
0217          * is just used for timing (and doesn't really have to exist).
0218          */
0219 
0220         dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
0221 
0222         out_be16(&rbdf->cbd_datlen, 0);
0223         out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
0224 
0225         if (rx + 1 == CPM_MAXBD)
0226             setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
0227 
0228         eieio();
0229         setbits16(&tbdf->cbd_sc, BD_SC_READY);
0230     } else {
0231         dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
0232 
0233         memcpy(tb+1, pmsg->buf, pmsg->len);
0234 
0235         eieio();
0236         setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
0237     }
0238 }
0239 
0240 static int cpm_i2c_check_message(struct i2c_adapter *adap,
0241     struct i2c_msg *pmsg, int tx, int rx)
0242 {
0243     cbd_t __iomem *tbdf;
0244     cbd_t __iomem *rbdf;
0245     u_char *tb;
0246     u_char *rb;
0247     struct cpm_i2c *cpm = i2c_get_adapdata(adap);
0248 
0249     tbdf = cpm->tbase + tx;
0250     rbdf = cpm->rbase + rx;
0251 
0252     tb = cpm->txbuf[tx];
0253     rb = cpm->rxbuf[rx];
0254 
0255     /* Align read buffer */
0256     rb = (u_char *) (((uint) rb + 1) & ~1);
0257 
0258     eieio();
0259     if (pmsg->flags & I2C_M_RD) {
0260         dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
0261             in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
0262 
0263         if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
0264             dev_dbg(&adap->dev, "I2C read; No ack\n");
0265             return -ENXIO;
0266         }
0267         if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
0268             dev_err(&adap->dev,
0269                 "I2C read; complete but rbuf empty\n");
0270             return -EREMOTEIO;
0271         }
0272         if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
0273             dev_err(&adap->dev, "I2C read; Overrun\n");
0274             return -EREMOTEIO;
0275         }
0276         memcpy(pmsg->buf, rb, pmsg->len);
0277     } else {
0278         dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
0279             in_be16(&tbdf->cbd_sc));
0280 
0281         if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
0282             dev_dbg(&adap->dev, "I2C write; No ack\n");
0283             return -ENXIO;
0284         }
0285         if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
0286             dev_err(&adap->dev, "I2C write; Underrun\n");
0287             return -EIO;
0288         }
0289         if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
0290             dev_err(&adap->dev, "I2C write; Collision\n");
0291             return -EIO;
0292         }
0293     }
0294     return 0;
0295 }
0296 
0297 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0298 {
0299     struct cpm_i2c *cpm = i2c_get_adapdata(adap);
0300     struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
0301     struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
0302     struct i2c_msg *pmsg;
0303     int ret;
0304     int tptr;
0305     int rptr;
0306     cbd_t __iomem *tbdf;
0307     cbd_t __iomem *rbdf;
0308 
0309     /* Reset to use first buffer */
0310     out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
0311     out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
0312 
0313     tbdf = cpm->tbase;
0314     rbdf = cpm->rbase;
0315 
0316     tptr = 0;
0317     rptr = 0;
0318 
0319     /*
0320      * If there was a collision in the last i2c transaction,
0321      * Set I2COM_MASTER as it was cleared during collision.
0322      */
0323     if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
0324         out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
0325     }
0326 
0327     while (tptr < num) {
0328         pmsg = &msgs[tptr];
0329         dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
0330 
0331         cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
0332         if (pmsg->flags & I2C_M_RD)
0333             rptr++;
0334         tptr++;
0335     }
0336     /* Start transfer now */
0337     /* Enable RX/TX/Error interupts */
0338     out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
0339     out_8(&i2c_reg->i2cer, 0xff);   /* Clear interrupt status */
0340     /* Chip bug, set enable here */
0341     setbits8(&i2c_reg->i2mod, I2MOD_EN);    /* Enable */
0342     /* Begin transmission */
0343     setbits8(&i2c_reg->i2com, I2COM_START);
0344 
0345     tptr = 0;
0346     rptr = 0;
0347 
0348     while (tptr < num) {
0349         /* Check for outstanding messages */
0350         dev_dbg(&adap->dev, "test ready.\n");
0351         pmsg = &msgs[tptr];
0352         if (pmsg->flags & I2C_M_RD)
0353             ret = wait_event_timeout(cpm->i2c_wait,
0354                 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
0355                 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
0356                 1 * HZ);
0357         else
0358             ret = wait_event_timeout(cpm->i2c_wait,
0359                 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
0360                 1 * HZ);
0361         if (ret == 0) {
0362             ret = -EREMOTEIO;
0363             dev_err(&adap->dev, "I2C transfer: timeout\n");
0364             goto out_err;
0365         }
0366         if (ret > 0) {
0367             dev_dbg(&adap->dev, "ready.\n");
0368             ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
0369             tptr++;
0370             if (pmsg->flags & I2C_M_RD)
0371                 rptr++;
0372             if (ret)
0373                 goto out_err;
0374         }
0375     }
0376 #ifdef I2C_CHIP_ERRATA
0377     /*
0378      * Chip errata, clear enable. This is not needed on rev D4 CPUs.
0379      * Disabling I2C too early may cause too short stop condition
0380      */
0381     udelay(4);
0382     clrbits8(&i2c_reg->i2mod, I2MOD_EN);
0383 #endif
0384     return (num);
0385 
0386 out_err:
0387     cpm_i2c_force_close(adap);
0388 #ifdef I2C_CHIP_ERRATA
0389     /*
0390      * Chip errata, clear enable. This is not needed on rev D4 CPUs.
0391      */
0392     clrbits8(&i2c_reg->i2mod, I2MOD_EN);
0393 #endif
0394     return ret;
0395 }
0396 
0397 static u32 cpm_i2c_func(struct i2c_adapter *adap)
0398 {
0399     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
0400 }
0401 
0402 /* -----exported algorithm data: -------------------------------------  */
0403 
0404 static const struct i2c_algorithm cpm_i2c_algo = {
0405     .master_xfer = cpm_i2c_xfer,
0406     .functionality = cpm_i2c_func,
0407 };
0408 
0409 /* CPM_MAX_READ is also limiting writes according to the code! */
0410 static const struct i2c_adapter_quirks cpm_i2c_quirks = {
0411     .max_num_msgs = CPM_MAXBD,
0412     .max_read_len = CPM_MAX_READ,
0413     .max_write_len = CPM_MAX_READ,
0414 };
0415 
0416 static const struct i2c_adapter cpm_ops = {
0417     .owner      = THIS_MODULE,
0418     .name       = "i2c-cpm",
0419     .algo       = &cpm_i2c_algo,
0420     .quirks     = &cpm_i2c_quirks,
0421 };
0422 
0423 static int cpm_i2c_setup(struct cpm_i2c *cpm)
0424 {
0425     struct platform_device *ofdev = cpm->ofdev;
0426     const u32 *data;
0427     int len, ret, i;
0428     void __iomem *i2c_base;
0429     cbd_t __iomem *tbdf;
0430     cbd_t __iomem *rbdf;
0431     unsigned char brg;
0432 
0433     dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
0434 
0435     init_waitqueue_head(&cpm->i2c_wait);
0436 
0437     cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
0438     if (!cpm->irq)
0439         return -EINVAL;
0440 
0441     /* Install interrupt handler. */
0442     ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
0443               &cpm->adap);
0444     if (ret)
0445         return ret;
0446 
0447     /* I2C parameter RAM */
0448     i2c_base = of_iomap(ofdev->dev.of_node, 1);
0449     if (i2c_base == NULL) {
0450         ret = -EINVAL;
0451         goto out_irq;
0452     }
0453 
0454     if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
0455 
0456         /* Check for and use a microcode relocation patch. */
0457         cpm->i2c_ram = i2c_base;
0458         cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
0459 
0460         /*
0461          * Maybe should use cpm_muram_alloc instead of hardcoding
0462          * this in micropatch.c
0463          */
0464         if (cpm->i2c_addr) {
0465             cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
0466             iounmap(i2c_base);
0467         }
0468 
0469         cpm->version = 1;
0470 
0471     } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
0472         cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
0473         cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
0474         out_be16(i2c_base, cpm->i2c_addr);
0475         iounmap(i2c_base);
0476 
0477         cpm->version = 2;
0478 
0479     } else {
0480         iounmap(i2c_base);
0481         ret = -EINVAL;
0482         goto out_irq;
0483     }
0484 
0485     /* I2C control/status registers */
0486     cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
0487     if (cpm->i2c_reg == NULL) {
0488         ret = -EINVAL;
0489         goto out_ram;
0490     }
0491 
0492     data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
0493     if (!data || len != 4) {
0494         ret = -EINVAL;
0495         goto out_reg;
0496     }
0497     cpm->cp_command = *data;
0498 
0499     data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
0500     if (data && len == 4)
0501         cpm->adap.class = *data;
0502 
0503     data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
0504     if (data && len == 4)
0505         cpm->freq = *data;
0506     else
0507         cpm->freq = 60000; /* use 60kHz i2c clock by default */
0508 
0509     /*
0510      * Allocate space for CPM_MAXBD transmit and receive buffer
0511      * descriptors in the DP ram.
0512      */
0513     cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
0514     if (!cpm->dp_addr) {
0515         ret = -ENOMEM;
0516         goto out_reg;
0517     }
0518 
0519     cpm->tbase = cpm_muram_addr(cpm->dp_addr);
0520     cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
0521 
0522     /* Allocate TX and RX buffers */
0523 
0524     tbdf = cpm->tbase;
0525     rbdf = cpm->rbase;
0526 
0527     for (i = 0; i < CPM_MAXBD; i++) {
0528         cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
0529                            CPM_MAX_READ + 1,
0530                            &cpm->rxdma[i], GFP_KERNEL);
0531         if (!cpm->rxbuf[i]) {
0532             ret = -ENOMEM;
0533             goto out_muram;
0534         }
0535         out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
0536 
0537         cpm->txbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
0538                            CPM_MAX_READ + 1,
0539                            &cpm->txdma[i], GFP_KERNEL);
0540         if (!cpm->txbuf[i]) {
0541             ret = -ENOMEM;
0542             goto out_muram;
0543         }
0544         out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
0545     }
0546 
0547     /* Initialize Tx/Rx parameters. */
0548 
0549     cpm_reset_i2c_params(cpm);
0550 
0551     dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
0552         cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
0553     dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
0554         (u8 __iomem *)cpm->tbase - DPRAM_BASE,
0555         (u8 __iomem *)cpm->rbase - DPRAM_BASE);
0556 
0557     cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
0558 
0559     /*
0560      * Select an invalid address. Just make sure we don't use loopback mode
0561      */
0562     out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
0563 
0564     /*
0565      * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
0566      * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
0567      * the actual i2c bus frequency.
0568      */
0569     brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
0570     out_8(&cpm->i2c_reg->i2brg, brg);
0571 
0572     out_8(&cpm->i2c_reg->i2mod, 0x00);
0573     out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);  /* Master mode */
0574 
0575     /* Disable interrupts. */
0576     out_8(&cpm->i2c_reg->i2cmr, 0);
0577     out_8(&cpm->i2c_reg->i2cer, 0xff);
0578 
0579     return 0;
0580 
0581 out_muram:
0582     for (i = 0; i < CPM_MAXBD; i++) {
0583         if (cpm->rxbuf[i])
0584             dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
0585                 cpm->rxbuf[i], cpm->rxdma[i]);
0586         if (cpm->txbuf[i])
0587             dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
0588                 cpm->txbuf[i], cpm->txdma[i]);
0589     }
0590     cpm_muram_free(cpm->dp_addr);
0591 out_reg:
0592     iounmap(cpm->i2c_reg);
0593 out_ram:
0594     if ((cpm->version == 1) && (!cpm->i2c_addr))
0595         iounmap(cpm->i2c_ram);
0596     if (cpm->version == 2)
0597         cpm_muram_free(cpm->i2c_addr);
0598 out_irq:
0599     free_irq(cpm->irq, &cpm->adap);
0600     return ret;
0601 }
0602 
0603 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
0604 {
0605     int i;
0606 
0607     /* Shut down I2C. */
0608     clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
0609 
0610     /* Disable interrupts */
0611     out_8(&cpm->i2c_reg->i2cmr, 0);
0612     out_8(&cpm->i2c_reg->i2cer, 0xff);
0613 
0614     free_irq(cpm->irq, &cpm->adap);
0615 
0616     /* Free all memory */
0617     for (i = 0; i < CPM_MAXBD; i++) {
0618         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
0619             cpm->rxbuf[i], cpm->rxdma[i]);
0620         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
0621             cpm->txbuf[i], cpm->txdma[i]);
0622     }
0623 
0624     cpm_muram_free(cpm->dp_addr);
0625     iounmap(cpm->i2c_reg);
0626 
0627     if ((cpm->version == 1) && (!cpm->i2c_addr))
0628         iounmap(cpm->i2c_ram);
0629     if (cpm->version == 2)
0630         cpm_muram_free(cpm->i2c_addr);
0631 }
0632 
0633 static int cpm_i2c_probe(struct platform_device *ofdev)
0634 {
0635     int result, len;
0636     struct cpm_i2c *cpm;
0637     const u32 *data;
0638 
0639     cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
0640     if (!cpm)
0641         return -ENOMEM;
0642 
0643     cpm->ofdev = ofdev;
0644 
0645     platform_set_drvdata(ofdev, cpm);
0646 
0647     cpm->adap = cpm_ops;
0648     i2c_set_adapdata(&cpm->adap, cpm);
0649     cpm->adap.dev.parent = &ofdev->dev;
0650     cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
0651 
0652     result = cpm_i2c_setup(cpm);
0653     if (result) {
0654         dev_err(&ofdev->dev, "Unable to init hardware\n");
0655         goto out_free;
0656     }
0657 
0658     /* register new adapter to i2c module... */
0659 
0660     data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
0661     cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
0662     result = i2c_add_numbered_adapter(&cpm->adap);
0663 
0664     if (result < 0)
0665         goto out_shut;
0666 
0667     dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
0668         cpm->adap.name);
0669 
0670     return 0;
0671 out_shut:
0672     cpm_i2c_shutdown(cpm);
0673 out_free:
0674     kfree(cpm);
0675 
0676     return result;
0677 }
0678 
0679 static int cpm_i2c_remove(struct platform_device *ofdev)
0680 {
0681     struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
0682 
0683     i2c_del_adapter(&cpm->adap);
0684 
0685     cpm_i2c_shutdown(cpm);
0686 
0687     kfree(cpm);
0688 
0689     return 0;
0690 }
0691 
0692 static const struct of_device_id cpm_i2c_match[] = {
0693     {
0694         .compatible = "fsl,cpm1-i2c",
0695     },
0696     {
0697         .compatible = "fsl,cpm2-i2c",
0698     },
0699     {},
0700 };
0701 
0702 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
0703 
0704 static struct platform_driver cpm_i2c_driver = {
0705     .probe      = cpm_i2c_probe,
0706     .remove     = cpm_i2c_remove,
0707     .driver = {
0708         .name = "fsl-i2c-cpm",
0709         .of_match_table = cpm_i2c_match,
0710     },
0711 };
0712 
0713 module_platform_driver(cpm_i2c_driver);
0714 
0715 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
0716 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
0717 MODULE_LICENSE("GPL");
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