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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2014 Broadcom Corporation
0003 
0004 #include <linux/clk.h>
0005 #include <linux/delay.h>
0006 #include <linux/device.h>
0007 #include <linux/i2c.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/sched.h>
0014 #include <linux/slab.h>
0015 
0016 #define N_DATA_REGS                 8
0017 
0018 /*
0019  * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
0020  * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
0021  * data register whereas STB SoCs use 4 byte per data register transfer,
0022  * account for this difference in total count per transaction and mask to
0023  * use.
0024  */
0025 #define BSC_CNT_REG1_MASK(nb)   (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
0026 #define BSC_CNT_REG1_SHIFT  0
0027 
0028 /* BSC CTL register field definitions */
0029 #define BSC_CTL_REG_DTF_MASK                0x00000003
0030 #define BSC_CTL_REG_SCL_SEL_MASK            0x00000030
0031 #define BSC_CTL_REG_SCL_SEL_SHIFT           4
0032 #define BSC_CTL_REG_INT_EN_MASK             0x00000040
0033 #define BSC_CTL_REG_INT_EN_SHIFT            6
0034 #define BSC_CTL_REG_DIV_CLK_MASK            0x00000080
0035 
0036 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
0037 #define BSC_IIC_EN_RESTART_MASK             0x00000040
0038 #define BSC_IIC_EN_NOSTART_MASK             0x00000020
0039 #define BSC_IIC_EN_NOSTOP_MASK              0x00000010
0040 #define BSC_IIC_EN_NOACK_MASK               0x00000004
0041 #define BSC_IIC_EN_INTRP_MASK               0x00000002
0042 #define BSC_IIC_EN_ENABLE_MASK              0x00000001
0043 
0044 /* BSC_CTLHI control register field definitions */
0045 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK    0x00000080
0046 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK         0x00000040
0047 #define BSC_CTLHI_REG_IGNORE_ACK_MASK           0x00000002
0048 #define BSC_CTLHI_REG_WAIT_DIS_MASK         0x00000001
0049 
0050 #define I2C_TIMEOUT                 100 /* msecs */
0051 
0052 /* Condition mask used for non combined transfer */
0053 #define COND_RESTART        BSC_IIC_EN_RESTART_MASK
0054 #define COND_NOSTART        BSC_IIC_EN_NOSTART_MASK
0055 #define COND_NOSTOP     BSC_IIC_EN_NOSTOP_MASK
0056 #define COND_START_STOP     (COND_RESTART | COND_NOSTART | COND_NOSTOP)
0057 
0058 /* BSC data transfer direction */
0059 #define DTF_WR_MASK     0x00000000
0060 #define DTF_RD_MASK     0x00000001
0061 /* BSC data transfer direction combined format */
0062 #define DTF_RD_WR_MASK      0x00000002
0063 #define DTF_WR_RD_MASK      0x00000003
0064 
0065 #define INT_ENABLE      true
0066 #define INT_DISABLE     false
0067 
0068 /* BSC block register map structure to cache fields to be written */
0069 struct bsc_regs {
0070     u32 chip_address;           /* slave address */
0071     u32 data_in[N_DATA_REGS];   /* tx data buffer*/
0072     u32 cnt_reg;        /* rx/tx data length */
0073     u32 ctl_reg;        /* control register */
0074     u32 iic_enable;     /* xfer enable and status */
0075     u32 data_out[N_DATA_REGS];  /* rx data buffer */
0076     u32 ctlhi_reg;      /* more control fields */
0077     u32 scl_param;      /* reserved */
0078 };
0079 
0080 struct bsc_clk_param {
0081     u32 hz;
0082     u32 scl_mask;
0083     u32 div_mask;
0084 };
0085 
0086 enum bsc_xfer_cmd {
0087     CMD_WR,
0088     CMD_RD,
0089     CMD_WR_NOACK,
0090     CMD_RD_NOACK,
0091 };
0092 
0093 static char const *cmd_string[] = {
0094     [CMD_WR] = "WR",
0095     [CMD_RD] = "RD",
0096     [CMD_WR_NOACK] = "WR NOACK",
0097     [CMD_RD_NOACK] = "RD NOACK",
0098 };
0099 
0100 enum bus_speeds {
0101     SPD_375K,
0102     SPD_390K,
0103     SPD_187K,
0104     SPD_200K,
0105     SPD_93K,
0106     SPD_97K,
0107     SPD_46K,
0108     SPD_50K
0109 };
0110 
0111 static const struct bsc_clk_param bsc_clk[] = {
0112     [SPD_375K] = {
0113         .hz = 375000,
0114         .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
0115         .div_mask = 0
0116     },
0117     [SPD_390K] = {
0118         .hz = 390000,
0119         .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
0120         .div_mask = 0
0121     },
0122     [SPD_187K] = {
0123         .hz = 187500,
0124         .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
0125         .div_mask = 0
0126     },
0127     [SPD_200K] = {
0128         .hz = 200000,
0129         .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
0130         .div_mask = 0
0131     },
0132     [SPD_93K]  = {
0133         .hz = 93750,
0134         .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
0135         .div_mask = BSC_CTL_REG_DIV_CLK_MASK
0136     },
0137     [SPD_97K]  = {
0138         .hz = 97500,
0139         .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
0140         .div_mask = BSC_CTL_REG_DIV_CLK_MASK
0141     },
0142     [SPD_46K]  = {
0143         .hz = 46875,
0144         .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
0145         .div_mask = BSC_CTL_REG_DIV_CLK_MASK
0146     },
0147     [SPD_50K]  = {
0148         .hz = 50000,
0149         .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
0150         .div_mask = BSC_CTL_REG_DIV_CLK_MASK
0151     }
0152 };
0153 
0154 struct brcmstb_i2c_dev {
0155     struct device *device;
0156     void __iomem *base;
0157     int irq;
0158     struct bsc_regs *bsc_regmap;
0159     struct i2c_adapter adapter;
0160     struct completion done;
0161     u32 clk_freq_hz;
0162     int data_regsz;
0163 };
0164 
0165 /* register accessors for both be and le cpu arch */
0166 #ifdef CONFIG_CPU_BIG_ENDIAN
0167 #define __bsc_readl(_reg) ioread32be(_reg)
0168 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
0169 #else
0170 #define __bsc_readl(_reg) ioread32(_reg)
0171 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
0172 #endif
0173 
0174 #define bsc_readl(_dev, _reg)                       \
0175     __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
0176 
0177 #define bsc_writel(_dev, _val, _reg)                    \
0178     __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
0179 
0180 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
0181 {
0182     return (N_DATA_REGS * dev->data_regsz);
0183 }
0184 
0185 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
0186 {
0187     return dev->data_regsz;
0188 }
0189 
0190 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
0191                        bool int_en)
0192 {
0193 
0194     if (int_en)
0195         /* Enable BSC  CTL interrupt line */
0196         dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
0197     else
0198         /* Disable BSC CTL interrupt line */
0199         dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
0200 
0201     barrier();
0202     bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
0203 }
0204 
0205 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
0206 {
0207     struct brcmstb_i2c_dev *dev = devid;
0208     u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
0209     u32 status_iic_intrp = bsc_readl(dev, iic_enable);
0210 
0211     dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
0212         status_bsc_ctl, status_iic_intrp);
0213 
0214     if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
0215         return IRQ_NONE;
0216 
0217     brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
0218     complete(&dev->done);
0219 
0220     dev_dbg(dev->device, "isr handled");
0221     return IRQ_HANDLED;
0222 }
0223 
0224 /* Wait for device to be ready */
0225 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
0226 {
0227     unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
0228 
0229     while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
0230         if (time_after(jiffies, timeout))
0231             return -ETIMEDOUT;
0232         cpu_relax();
0233     }
0234     return 0;
0235 }
0236 
0237 /* i2c xfer completion function, handles both irq and polling mode */
0238 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
0239 {
0240     int ret = 0;
0241     unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
0242 
0243     if (dev->irq >= 0) {
0244         if (!wait_for_completion_timeout(&dev->done, timeout))
0245             ret = -ETIMEDOUT;
0246     } else {
0247         /* we are in polling mode */
0248         u32 bsc_intrp;
0249         unsigned long time_left = jiffies + timeout;
0250 
0251         do {
0252             bsc_intrp = bsc_readl(dev, iic_enable) &
0253                 BSC_IIC_EN_INTRP_MASK;
0254             if (time_after(jiffies, time_left)) {
0255                 ret = -ETIMEDOUT;
0256                 break;
0257             }
0258             cpu_relax();
0259         } while (!bsc_intrp);
0260     }
0261 
0262     if (dev->irq < 0 || ret == -ETIMEDOUT)
0263         brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
0264 
0265     return ret;
0266 }
0267 
0268 /* Set xfer START/STOP conditions for subsequent transfer */
0269 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
0270                        u32 cond_flag)
0271 {
0272     u32 regval = dev->bsc_regmap->iic_enable;
0273 
0274     dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
0275 }
0276 
0277 /* Send I2C request check completion */
0278 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
0279                 enum bsc_xfer_cmd cmd)
0280 {
0281     int rc = 0;
0282     struct bsc_regs *pi2creg = dev->bsc_regmap;
0283 
0284     /* Make sure the hardware is ready */
0285     rc = brcmstb_i2c_wait_if_busy(dev);
0286     if (rc < 0)
0287         return rc;
0288 
0289     /* only if we are in interrupt mode */
0290     if (dev->irq >= 0)
0291         reinit_completion(&dev->done);
0292 
0293     /* enable BSC CTL interrupt line */
0294     brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
0295 
0296     /* initiate transfer by setting iic_enable */
0297     pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
0298     bsc_writel(dev, pi2creg->iic_enable, iic_enable);
0299 
0300     /* Wait for transaction to finish or timeout */
0301     rc = brcmstb_i2c_wait_for_completion(dev);
0302     if (rc) {
0303         dev_dbg(dev->device, "intr timeout for cmd %s\n",
0304             cmd_string[cmd]);
0305         goto cmd_out;
0306     }
0307 
0308     if ((cmd == CMD_RD || cmd == CMD_WR) &&
0309         bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
0310         rc = -EREMOTEIO;
0311         dev_dbg(dev->device, "controller received NOACK intr for %s\n",
0312             cmd_string[cmd]);
0313     }
0314 
0315 cmd_out:
0316     bsc_writel(dev, 0, cnt_reg);
0317     bsc_writel(dev, 0, iic_enable);
0318 
0319     return rc;
0320 }
0321 
0322 /* Actual data transfer through the BSC master */
0323 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
0324                      u8 *buf, unsigned int len,
0325                      struct i2c_msg *pmsg)
0326 {
0327     int cnt, byte, i, rc;
0328     enum bsc_xfer_cmd cmd;
0329     u32 ctl_reg;
0330     struct bsc_regs *pi2creg = dev->bsc_regmap;
0331     int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
0332     int data_regsz = brcmstb_i2c_get_data_regsz(dev);
0333 
0334     /* see if the transaction needs to check NACK conditions */
0335     if (no_ack) {
0336         cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
0337             : CMD_WR_NOACK;
0338         pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
0339     } else {
0340         cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
0341         pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
0342     }
0343     bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
0344 
0345     /* set data transfer direction */
0346     ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
0347     if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
0348         pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
0349     else
0350         pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
0351 
0352     /* set the read/write length */
0353     bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
0354            (len << BSC_CNT_REG1_SHIFT), cnt_reg);
0355 
0356     /* Write data into data_in register */
0357 
0358     if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
0359         for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
0360             u32 word = 0;
0361 
0362             for (byte = 0; byte < data_regsz; byte++) {
0363                 word >>= BITS_PER_BYTE;
0364                 if ((cnt + byte) < len)
0365                     word |= buf[cnt + byte] <<
0366                     (BITS_PER_BYTE * (data_regsz - 1));
0367             }
0368             bsc_writel(dev, word, data_in[i]);
0369         }
0370     }
0371 
0372     /* Initiate xfer, the function will return on completion */
0373     rc = brcmstb_send_i2c_cmd(dev, cmd);
0374 
0375     if (rc != 0) {
0376         dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
0377         return rc;
0378     }
0379 
0380     /* Read data from data_out register */
0381     if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
0382         for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
0383             u32 data = bsc_readl(dev, data_out[i]);
0384 
0385             for (byte = 0; byte < data_regsz &&
0386                      (byte + cnt) < len; byte++) {
0387                 buf[cnt + byte] = data & 0xff;
0388                 data >>= BITS_PER_BYTE;
0389             }
0390         }
0391     }
0392 
0393     return 0;
0394 }
0395 
0396 /* Write a single byte of data to the i2c bus */
0397 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
0398                        u8 *buf, unsigned int nak_expected)
0399 {
0400     enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
0401 
0402     bsc_writel(dev, 1, cnt_reg);
0403     bsc_writel(dev, *buf, data_in);
0404 
0405     return brcmstb_send_i2c_cmd(dev, cmd);
0406 }
0407 
0408 /* Send i2c address */
0409 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
0410                    struct i2c_msg *msg)
0411 {
0412     unsigned char addr;
0413 
0414     if (msg->flags & I2C_M_TEN) {
0415         /* First byte is 11110XX0 where XX is upper 2 bits */
0416         addr = 0xF0 | ((msg->addr & 0x300) >> 7);
0417         bsc_writel(dev, addr, chip_address);
0418 
0419         /* Second byte is the remaining 8 bits */
0420         addr = msg->addr & 0xFF;
0421         if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
0422             return -EREMOTEIO;
0423 
0424         if (msg->flags & I2C_M_RD) {
0425             /* For read, send restart without stop condition */
0426             brcmstb_set_i2c_start_stop(dev, COND_RESTART
0427                            | COND_NOSTOP);
0428             /* Then re-send the first byte with the read bit set */
0429             addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
0430             if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
0431                 return -EREMOTEIO;
0432 
0433         }
0434     } else {
0435         addr = i2c_8bit_addr_from_msg(msg);
0436 
0437         bsc_writel(dev, addr, chip_address);
0438     }
0439 
0440     return 0;
0441 }
0442 
0443 /* Master transfer function */
0444 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
0445                 struct i2c_msg msgs[], int num)
0446 {
0447     struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
0448     struct i2c_msg *pmsg;
0449     int rc = 0;
0450     int i;
0451     int bytes_to_xfer;
0452     u8 *tmp_buf;
0453     int len = 0;
0454     int xfersz = brcmstb_i2c_get_xfersz(dev);
0455     u32 cond, cond_per_msg;
0456 
0457     /* Loop through all messages */
0458     for (i = 0; i < num; i++) {
0459         pmsg = &msgs[i];
0460         len = pmsg->len;
0461         tmp_buf = pmsg->buf;
0462 
0463         dev_dbg(dev->device,
0464             "msg# %d/%d flg %x buf %x len %d\n", i,
0465             num - 1, pmsg->flags,
0466             pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
0467 
0468         if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
0469             cond = ~COND_START_STOP;
0470         else
0471             cond = COND_RESTART | COND_NOSTOP;
0472 
0473         brcmstb_set_i2c_start_stop(dev, cond);
0474 
0475         /* Send slave address */
0476         if (!(pmsg->flags & I2C_M_NOSTART)) {
0477             rc = brcmstb_i2c_do_addr(dev, pmsg);
0478             if (rc < 0) {
0479                 dev_dbg(dev->device,
0480                     "NACK for addr %2.2x msg#%d rc = %d\n",
0481                     pmsg->addr, i, rc);
0482                 goto out;
0483             }
0484         }
0485 
0486         cond_per_msg = cond;
0487 
0488         /* Perform data transfer */
0489         while (len) {
0490             bytes_to_xfer = min(len, xfersz);
0491 
0492             if (len <= xfersz) {
0493                 if (i == (num - 1))
0494                     cond_per_msg = cond_per_msg &
0495                         ~(COND_RESTART | COND_NOSTOP);
0496                 else
0497                     cond_per_msg = cond;
0498             } else {
0499                 cond_per_msg = (cond_per_msg & ~COND_RESTART) |
0500                     COND_NOSTOP;
0501             }
0502 
0503             brcmstb_set_i2c_start_stop(dev, cond_per_msg);
0504 
0505             rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
0506                                bytes_to_xfer, pmsg);
0507             if (rc < 0)
0508                 goto out;
0509 
0510             len -=  bytes_to_xfer;
0511             tmp_buf += bytes_to_xfer;
0512 
0513             cond_per_msg = COND_NOSTART | COND_NOSTOP;
0514         }
0515     }
0516 
0517     rc = num;
0518 out:
0519     return rc;
0520 
0521 }
0522 
0523 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
0524 {
0525     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
0526         | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
0527 }
0528 
0529 static const struct i2c_algorithm brcmstb_i2c_algo = {
0530     .master_xfer = brcmstb_i2c_xfer,
0531     .functionality = brcmstb_i2c_functionality,
0532 };
0533 
0534 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
0535 {
0536     int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
0537     u32 clk_freq_hz = dev->clk_freq_hz;
0538 
0539     for (i = 0; i < num_speeds; i++) {
0540         if (bsc_clk[i].hz == clk_freq_hz) {
0541             dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
0542                         | BSC_CTL_REG_DIV_CLK_MASK);
0543             dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
0544                              bsc_clk[i].div_mask);
0545             bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
0546             break;
0547         }
0548     }
0549 
0550     /* in case we did not get find a valid speed */
0551     if (i == num_speeds) {
0552         i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
0553             BSC_CTL_REG_SCL_SEL_SHIFT;
0554         dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
0555             bsc_clk[i].hz);
0556     }
0557 }
0558 
0559 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
0560 {
0561     if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
0562         /* set 4 byte data in/out xfers  */
0563         dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
0564     else
0565         dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
0566 
0567     bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
0568     /* set bus speed */
0569     brcmstb_i2c_set_bus_speed(dev);
0570 }
0571 
0572 #define AUTOI2C_CTRL0       0x26c
0573 #define AUTOI2C_CTRL0_RELEASE_BSC   BIT(1)
0574 
0575 static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev)
0576 {
0577     struct platform_device *pdev = to_platform_device(dev->device);
0578     struct resource *iomem;
0579     void __iomem *autoi2c;
0580 
0581     /* Map hardware registers */
0582     iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "auto-i2c");
0583     autoi2c = devm_ioremap_resource(&pdev->dev, iomem);
0584     if (IS_ERR(autoi2c))
0585         return PTR_ERR(autoi2c);
0586 
0587     writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
0588     devm_iounmap(&pdev->dev, autoi2c);
0589 
0590     /* We need to reset the controller after the release */
0591     dev->bsc_regmap->iic_enable = 0;
0592     bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable);
0593 
0594     return 0;
0595 }
0596 
0597 static int brcmstb_i2c_probe(struct platform_device *pdev)
0598 {
0599     int rc = 0;
0600     struct brcmstb_i2c_dev *dev;
0601     struct i2c_adapter *adap;
0602     struct resource *iomem;
0603     const char *int_name;
0604 
0605     /* Allocate memory for private data structure */
0606     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0607     if (!dev)
0608         return -ENOMEM;
0609 
0610     dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
0611     if (!dev->bsc_regmap)
0612         return -ENOMEM;
0613 
0614     platform_set_drvdata(pdev, dev);
0615     dev->device = &pdev->dev;
0616     init_completion(&dev->done);
0617 
0618     /* Map hardware registers */
0619     iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0620     dev->base = devm_ioremap_resource(dev->device, iomem);
0621     if (IS_ERR(dev->base)) {
0622         rc = -ENOMEM;
0623         goto probe_errorout;
0624     }
0625 
0626     if (of_device_is_compatible(dev->device->of_node,
0627                     "brcm,bcm2711-hdmi-i2c")) {
0628         rc = bcm2711_release_bsc(dev);
0629         if (rc)
0630             goto probe_errorout;
0631     }
0632 
0633     rc = of_property_read_string(dev->device->of_node, "interrupt-names",
0634                      &int_name);
0635     if (rc < 0)
0636         int_name = NULL;
0637 
0638     /* Get the interrupt number */
0639     dev->irq = platform_get_irq_optional(pdev, 0);
0640 
0641     /* disable the bsc interrupt line */
0642     brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
0643 
0644     /* register the ISR handler */
0645     if (dev->irq >= 0) {
0646         rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
0647                       IRQF_SHARED,
0648                       int_name ? int_name : pdev->name,
0649                       dev);
0650 
0651         if (rc) {
0652             dev_dbg(dev->device, "falling back to polling mode");
0653             dev->irq = -1;
0654         }
0655     }
0656 
0657     if (of_property_read_u32(dev->device->of_node,
0658                  "clock-frequency", &dev->clk_freq_hz)) {
0659         dev_warn(dev->device, "setting clock-frequency@%dHz\n",
0660              bsc_clk[0].hz);
0661         dev->clk_freq_hz = bsc_clk[0].hz;
0662     }
0663 
0664     /* set the data in/out register size for compatible SoCs */
0665     if (of_device_is_compatible(dev->device->of_node,
0666                     "brcm,brcmper-i2c"))
0667         dev->data_regsz = sizeof(u8);
0668     else
0669         dev->data_regsz = sizeof(u32);
0670 
0671     brcmstb_i2c_set_bsc_reg_defaults(dev);
0672 
0673     /* Add the i2c adapter */
0674     adap = &dev->adapter;
0675     i2c_set_adapdata(adap, dev);
0676     adap->owner = THIS_MODULE;
0677     strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
0678     adap->algo = &brcmstb_i2c_algo;
0679     adap->dev.parent = &pdev->dev;
0680     adap->dev.of_node = pdev->dev.of_node;
0681     rc = i2c_add_adapter(adap);
0682     if (rc)
0683         goto probe_errorout;
0684 
0685     dev_info(dev->device, "%s@%dhz registered in %s mode\n",
0686          int_name ? int_name : " ", dev->clk_freq_hz,
0687          (dev->irq >= 0) ? "interrupt" : "polling");
0688 
0689     return 0;
0690 
0691 probe_errorout:
0692     return rc;
0693 }
0694 
0695 static int brcmstb_i2c_remove(struct platform_device *pdev)
0696 {
0697     struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
0698 
0699     i2c_del_adapter(&dev->adapter);
0700     return 0;
0701 }
0702 
0703 #ifdef CONFIG_PM_SLEEP
0704 static int brcmstb_i2c_suspend(struct device *dev)
0705 {
0706     struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
0707 
0708     i2c_mark_adapter_suspended(&i2c_dev->adapter);
0709     return 0;
0710 }
0711 
0712 static int brcmstb_i2c_resume(struct device *dev)
0713 {
0714     struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
0715 
0716     brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
0717     i2c_mark_adapter_resumed(&i2c_dev->adapter);
0718 
0719     return 0;
0720 }
0721 #endif
0722 
0723 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
0724              brcmstb_i2c_resume);
0725 
0726 static const struct of_device_id brcmstb_i2c_of_match[] = {
0727     {.compatible = "brcm,brcmstb-i2c"},
0728     {.compatible = "brcm,brcmper-i2c"},
0729     {.compatible = "brcm,bcm2711-hdmi-i2c"},
0730     {},
0731 };
0732 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
0733 
0734 static struct platform_driver brcmstb_i2c_driver = {
0735     .driver = {
0736            .name = "brcmstb-i2c",
0737            .of_match_table = brcmstb_i2c_of_match,
0738            .pm = &brcmstb_i2c_pm,
0739            },
0740     .probe = brcmstb_i2c_probe,
0741     .remove = brcmstb_i2c_remove,
0742 };
0743 module_platform_driver(brcmstb_i2c_driver);
0744 
0745 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
0746 MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
0747 MODULE_LICENSE("GPL v2");
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