i2c/busses/i2c-bcm2835.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * BCM2835 master mode driver
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/clkdev.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/completion.h>
0010 #include <linux/err.h>
0011 #include <linux/i2c.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018
0019 #define BCM2835_I2C_C       0x0
0020 #define BCM2835_I2C_S       0x4
0021 #define BCM2835_I2C_DLEN    0x8
0022 #define BCM2835_I2C_A       0xc
0023 #define BCM2835_I2C_FIFO    0x10
0024 #define BCM2835_I2C_DIV     0x14
0025 #define BCM2835_I2C_DEL     0x18
0026 /*
0027  * 16-bit field for the number of SCL cycles to wait after rising SCL
0028  * before deciding the slave is not responding. 0 disables the
0029  * timeout detection.
0030  */
0031 #define BCM2835_I2C_CLKT    0x1c
0032
0033 #define BCM2835_I2C_C_READ  BIT(0)
0034 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
0035 #define BCM2835_I2C_C_ST    BIT(7)
0036 #define BCM2835_I2C_C_INTD  BIT(8)
0037 #define BCM2835_I2C_C_INTT  BIT(9)
0038 #define BCM2835_I2C_C_INTR  BIT(10)
0039 #define BCM2835_I2C_C_I2CEN BIT(15)
0040
0041 #define BCM2835_I2C_S_TA    BIT(0)
0042 #define BCM2835_I2C_S_DONE  BIT(1)
0043 #define BCM2835_I2C_S_TXW   BIT(2)
0044 #define BCM2835_I2C_S_RXR   BIT(3)
0045 #define BCM2835_I2C_S_TXD   BIT(4)
0046 #define BCM2835_I2C_S_RXD   BIT(5)
0047 #define BCM2835_I2C_S_TXE   BIT(6)
0048 #define BCM2835_I2C_S_RXF   BIT(7)
0049 #define BCM2835_I2C_S_ERR   BIT(8)
0050 #define BCM2835_I2C_S_CLKT  BIT(9)
0051 #define BCM2835_I2C_S_LEN   BIT(10) /* Fake bit for SW error reporting */
0052
0053 #define BCM2835_I2C_FEDL_SHIFT  16
0054 #define BCM2835_I2C_REDL_SHIFT  0
0055
0056 #define BCM2835_I2C_CDIV_MIN    0x0002
0057 #define BCM2835_I2C_CDIV_MAX    0xFFFE
0058
0059 struct bcm2835_i2c_dev {
0060     struct device *dev;
0061     void __iomem *regs;
0062     int irq;
0063     struct i2c_adapter adapter;
0064     struct completion completion;
0065     struct i2c_msg *curr_msg;
0066     struct clk *bus_clk;
0067     int num_msgs;
0068     u32 msg_err;
0069     u8 *msg_buf;
0070     size_t msg_buf_remaining;
0071 };
0072
0073 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
0074                       u32 reg, u32 val)
0075 {
0076     writel(val, i2c_dev->regs + reg);
0077 }
0078
0079 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
0080 {
0081     return readl(i2c_dev->regs + reg);
0082 }
0083
0084 #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
0085 struct clk_bcm2835_i2c {
0086     struct clk_hw hw;
0087     struct bcm2835_i2c_dev *i2c_dev;
0088 };
0089
0090 static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
0091                 unsigned long parent_rate)
0092 {
0093     u32 divider = DIV_ROUND_UP(parent_rate, rate);
0094
0095     /*
0096      * Per the datasheet, the register is always interpreted as an even
0097      * number, by rounding down. In other words, the LSB is ignored. So,
0098      * if the LSB is set, increment the divider to avoid any issue.
0099      */
0100     if (divider & 1)
0101         divider++;
0102     if ((divider < BCM2835_I2C_CDIV_MIN) ||
0103         (divider > BCM2835_I2C_CDIV_MAX))
0104         return -EINVAL;
0105
0106     return divider;
0107 }
0108
0109 static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
0110                 unsigned long parent_rate)
0111 {
0112     struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
0113     u32 redl, fedl;
0114     u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
0115
0116     if (divider == -EINVAL)
0117         return -EINVAL;
0118
0119     bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
0120
0121     /*
0122      * Number of core clocks to wait after falling edge before
0123      * outputting the next data bit.  Note that both FEDL and REDL
0124      * can't be greater than CDIV/2.
0125      */
0126     fedl = max(divider / 16, 1u);
0127
0128     /*
0129      * Number of core clocks to wait after rising edge before
0130      * sampling the next incoming data bit.
0131      */
0132     redl = max(divider / 4, 1u);
0133
0134     bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
0135                (fedl << BCM2835_I2C_FEDL_SHIFT) |
0136                (redl << BCM2835_I2C_REDL_SHIFT));
0137     return 0;
0138 }
0139
0140 static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
0141                 unsigned long *parent_rate)
0142 {
0143     u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
0144
0145     return DIV_ROUND_UP(*parent_rate, divider);
0146 }
0147
0148 static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
0149                         unsigned long parent_rate)
0150 {
0151     struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
0152     u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
0153
0154     return DIV_ROUND_UP(parent_rate, divider);
0155 }
0156
0157 static const struct clk_ops clk_bcm2835_i2c_ops = {
0158     .set_rate = clk_bcm2835_i2c_set_rate,
0159     .round_rate = clk_bcm2835_i2c_round_rate,
0160     .recalc_rate = clk_bcm2835_i2c_recalc_rate,
0161 };
0162
0163 static struct clk *bcm2835_i2c_register_div(struct device *dev,
0164                     struct clk *mclk,
0165                     struct bcm2835_i2c_dev *i2c_dev)
0166 {
0167     struct clk_init_data init;
0168     struct clk_bcm2835_i2c *priv;
0169     char name[32];
0170     const char *mclk_name;
0171
0172     snprintf(name, sizeof(name), "%s_div", dev_name(dev));
0173
0174     mclk_name = __clk_get_name(mclk);
0175
0176     init.ops = &clk_bcm2835_i2c_ops;
0177     init.name = name;
0178     init.parent_names = (const char* []) { mclk_name };
0179     init.num_parents = 1;
0180     init.flags = 0;
0181
0182     priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
0183     if (priv == NULL)
0184         return ERR_PTR(-ENOMEM);
0185
0186     priv->hw.init = &init;
0187     priv->i2c_dev = i2c_dev;
0188
0189     clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
0190     return devm_clk_register(dev, &priv->hw);
0191 }
0192
0193 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
0194 {
0195     u32 val;
0196
0197     while (i2c_dev->msg_buf_remaining) {
0198         val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
0199         if (!(val & BCM2835_I2C_S_TXD))
0200             break;
0201         bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
0202                    *i2c_dev->msg_buf);
0203         i2c_dev->msg_buf++;
0204         i2c_dev->msg_buf_remaining--;
0205     }
0206 }
0207
0208 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
0209 {
0210     u32 val;
0211
0212     while (i2c_dev->msg_buf_remaining) {
0213         val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
0214         if (!(val & BCM2835_I2C_S_RXD))
0215             break;
0216         *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
0217                               BCM2835_I2C_FIFO);
0218         i2c_dev->msg_buf++;
0219         i2c_dev->msg_buf_remaining--;
0220     }
0221 }
0222
0223 /*
0224  * Repeated Start Condition (Sr)
0225  * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
0226  * talks about reading from a slave with 10 bit address. This is achieved by
0227  * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
0228  * issue a read.
0229  * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
0230  * firmware actually does it using polling and says that it's a workaround for
0231  * a problem in the state machine.
0232  * It turns out that it is possible to use the TXW interrupt to know when the
0233  * transfer is active, provided the FIFO has not been prefilled.
0234  */
0235
0236 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
0237 {
0238     u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
0239     struct i2c_msg *msg = i2c_dev->curr_msg;
0240     bool last_msg = (i2c_dev->num_msgs == 1);
0241
0242     if (!i2c_dev->num_msgs)
0243         return;
0244
0245     i2c_dev->num_msgs--;
0246     i2c_dev->msg_buf = msg->buf;
0247     i2c_dev->msg_buf_remaining = msg->len;
0248
0249     if (msg->flags & I2C_M_RD)
0250         c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
0251     else
0252         c |= BCM2835_I2C_C_INTT;
0253
0254     if (last_msg)
0255         c |= BCM2835_I2C_C_INTD;
0256
0257     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
0258     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
0259     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
0260 }
0261
0262 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
0263 {
0264     i2c_dev->curr_msg = NULL;
0265     i2c_dev->num_msgs = 0;
0266
0267     i2c_dev->msg_buf = NULL;
0268     i2c_dev->msg_buf_remaining = 0;
0269 }
0270
0271 /*
0272  * Note about I2C_C_CLEAR on error:
0273  * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
0274  * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
0275  * the state machine to send a NACK and a STOP. Since we're setting CLEAR
0276  * without I2CEN, that NACK will be hanging around queued up for next time
0277  * we start the engine.
0278  */
0279
0280 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
0281 {
0282     struct bcm2835_i2c_dev *i2c_dev = data;
0283     u32 val, err;
0284
0285     val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
0286
0287     err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
0288     if (err) {
0289         i2c_dev->msg_err = err;
0290         goto complete;
0291     }
0292
0293     if (val & BCM2835_I2C_S_DONE) {
0294         if (!i2c_dev->curr_msg) {
0295             dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
0296         } else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
0297             bcm2835_drain_rxfifo(i2c_dev);
0298             val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
0299         }
0300
0301         if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
0302             i2c_dev->msg_err = BCM2835_I2C_S_LEN;
0303         else
0304             i2c_dev->msg_err = 0;
0305         goto complete;
0306     }
0307
0308     if (val & BCM2835_I2C_S_TXW) {
0309         if (!i2c_dev->msg_buf_remaining) {
0310             i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
0311             goto complete;
0312         }
0313
0314         bcm2835_fill_txfifo(i2c_dev);
0315
0316         if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
0317             i2c_dev->curr_msg++;
0318             bcm2835_i2c_start_transfer(i2c_dev);
0319         }
0320
0321         return IRQ_HANDLED;
0322     }
0323
0324     if (val & BCM2835_I2C_S_RXR) {
0325         if (!i2c_dev->msg_buf_remaining) {
0326             i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
0327             goto complete;
0328         }
0329
0330         bcm2835_drain_rxfifo(i2c_dev);
0331         return IRQ_HANDLED;
0332     }
0333
0334     return IRQ_NONE;
0335
0336 complete:
0337     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
0338     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
0339                BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
0340     complete(&i2c_dev->completion);
0341
0342     return IRQ_HANDLED;
0343 }
0344
0345 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
0346                 int num)
0347 {
0348     struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
0349     unsigned long time_left;
0350     int i;
0351
0352     for (i = 0; i < (num - 1); i++)
0353         if (msgs[i].flags & I2C_M_RD) {
0354             dev_warn_once(i2c_dev->dev,
0355                       "only one read message supported, has to be last\n");
0356             return -EOPNOTSUPP;
0357         }
0358
0359     i2c_dev->curr_msg = msgs;
0360     i2c_dev->num_msgs = num;
0361     reinit_completion(&i2c_dev->completion);
0362
0363     bcm2835_i2c_start_transfer(i2c_dev);
0364
0365     time_left = wait_for_completion_timeout(&i2c_dev->completion,
0366                         adap->timeout);
0367
0368     bcm2835_i2c_finish_transfer(i2c_dev);
0369
0370     if (!time_left) {
0371         bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
0372                    BCM2835_I2C_C_CLEAR);
0373         dev_err(i2c_dev->dev, "i2c transfer timed out\n");
0374         return -ETIMEDOUT;
0375     }
0376
0377     if (!i2c_dev->msg_err)
0378         return num;
0379
0380     dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
0381
0382     if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
0383         return -EREMOTEIO;
0384
0385     return -EIO;
0386 }
0387
0388 static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
0389 {
0390     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0391 }
0392
0393 static const struct i2c_algorithm bcm2835_i2c_algo = {
0394     .master_xfer    = bcm2835_i2c_xfer,
0395     .functionality  = bcm2835_i2c_func,
0396 };
0397
0398 /*
0399  * The BCM2835 was reported to have problems with clock stretching:
0400  * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
0401  * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
0402  */
0403 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
0404     .flags = I2C_AQ_NO_CLK_STRETCH,
0405 };
0406
0407 static int bcm2835_i2c_probe(struct platform_device *pdev)
0408 {
0409     struct bcm2835_i2c_dev *i2c_dev;
0410     struct resource *mem;
0411     int ret;
0412     struct i2c_adapter *adap;
0413     struct clk *mclk;
0414     u32 bus_clk_rate;
0415
0416     i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
0417     if (!i2c_dev)
0418         return -ENOMEM;
0419     platform_set_drvdata(pdev, i2c_dev);
0420     i2c_dev->dev = &pdev->dev;
0421     init_completion(&i2c_dev->completion);
0422
0423     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0424     i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
0425     if (IS_ERR(i2c_dev->regs))
0426         return PTR_ERR(i2c_dev->regs);
0427
0428     mclk = devm_clk_get(&pdev->dev, NULL);
0429     if (IS_ERR(mclk))
0430         return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
0431                      "Could not get clock\n");
0432
0433     i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
0434
0435     if (IS_ERR(i2c_dev->bus_clk)) {
0436         dev_err(&pdev->dev, "Could not register clock\n");
0437         return PTR_ERR(i2c_dev->bus_clk);
0438     }
0439
0440     ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
0441                    &bus_clk_rate);
0442     if (ret < 0) {
0443         dev_warn(&pdev->dev,
0444              "Could not read clock-frequency property\n");
0445         bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
0446     }
0447
0448     ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
0449     if (ret < 0) {
0450         dev_err(&pdev->dev, "Could not set clock frequency\n");
0451         return ret;
0452     }
0453
0454     ret = clk_prepare_enable(i2c_dev->bus_clk);
0455     if (ret) {
0456         dev_err(&pdev->dev, "Couldn't prepare clock");
0457         goto err_put_exclusive_rate;
0458     }
0459
0460     i2c_dev->irq = platform_get_irq(pdev, 0);
0461     if (i2c_dev->irq < 0) {
0462         ret = i2c_dev->irq;
0463         goto err_disable_unprepare_clk;
0464     }
0465
0466     ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
0467               dev_name(&pdev->dev), i2c_dev);
0468     if (ret) {
0469         dev_err(&pdev->dev, "Could not request IRQ\n");
0470         goto err_disable_unprepare_clk;
0471     }
0472
0473     adap = &i2c_dev->adapter;
0474     i2c_set_adapdata(adap, i2c_dev);
0475     adap->owner = THIS_MODULE;
0476     adap->class = I2C_CLASS_DEPRECATED;
0477     snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
0478          of_node_full_name(pdev->dev.of_node));
0479     adap->algo = &bcm2835_i2c_algo;
0480     adap->dev.parent = &pdev->dev;
0481     adap->dev.of_node = pdev->dev.of_node;
0482     adap->quirks = of_device_get_match_data(&pdev->dev);
0483
0484     /*
0485      * Disable the hardware clock stretching timeout. SMBUS
0486      * specifies a limit for how long the device can stretch the
0487      * clock, but core I2C doesn't.
0488      */
0489     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
0490     bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
0491
0492     ret = i2c_add_adapter(adap);
0493     if (ret)
0494         goto err_free_irq;
0495
0496     return 0;
0497
0498 err_free_irq:
0499     free_irq(i2c_dev->irq, i2c_dev);
0500 err_disable_unprepare_clk:
0501     clk_disable_unprepare(i2c_dev->bus_clk);
0502 err_put_exclusive_rate:
0503     clk_rate_exclusive_put(i2c_dev->bus_clk);
0504
0505     return ret;
0506 }
0507
0508 static int bcm2835_i2c_remove(struct platform_device *pdev)
0509 {
0510     struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
0511
0512     clk_rate_exclusive_put(i2c_dev->bus_clk);
0513     clk_disable_unprepare(i2c_dev->bus_clk);
0514
0515     free_irq(i2c_dev->irq, i2c_dev);
0516     i2c_del_adapter(&i2c_dev->adapter);
0517
0518     return 0;
0519 }
0520
0521 static const struct of_device_id bcm2835_i2c_of_match[] = {
0522     { .compatible = "brcm,bcm2711-i2c" },
0523     { .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
0524     {},
0525 };
0526 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
0527
0528 static struct platform_driver bcm2835_i2c_driver = {
0529     .probe      = bcm2835_i2c_probe,
0530     .remove     = bcm2835_i2c_remove,
0531     .driver     = {
0532         .name   = "i2c-bcm2835",
0533         .of_match_table = bcm2835_i2c_of_match,
0534     },
0535 };
0536 module_platform_driver(bcm2835_i2c_driver);
0537
0538 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
0539 MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
0540 MODULE_LICENSE("GPL v2");
0541 MODULE_ALIAS("platform:i2c-bcm2835");