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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2013 Broadcom Corporation
0003 
0004 #include <linux/device.h>
0005 #include <linux/kernel.h>
0006 #include <linux/module.h>
0007 #include <linux/sched.h>
0008 #include <linux/i2c.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/clk.h>
0012 #include <linux/io.h>
0013 #include <linux/slab.h>
0014 
0015 /* Hardware register offsets and field defintions */
0016 #define CS_OFFSET               0x00000020
0017 #define CS_ACK_SHIFT                3
0018 #define CS_ACK_MASK             0x00000008
0019 #define CS_ACK_CMD_GEN_START            0x00000000
0020 #define CS_ACK_CMD_GEN_RESTART          0x00000001
0021 #define CS_CMD_SHIFT                1
0022 #define CS_CMD_CMD_NO_ACTION            0x00000000
0023 #define CS_CMD_CMD_START_RESTART        0x00000001
0024 #define CS_CMD_CMD_STOP             0x00000002
0025 #define CS_EN_SHIFT             0
0026 #define CS_EN_CMD_ENABLE_BSC            0x00000001
0027 
0028 #define TIM_OFFSET              0x00000024
0029 #define TIM_PRESCALE_SHIFT          6
0030 #define TIM_P_SHIFT             3
0031 #define TIM_NO_DIV_SHIFT            2
0032 #define TIM_DIV_SHIFT               0
0033 
0034 #define DAT_OFFSET              0x00000028
0035 
0036 #define TOUT_OFFSET             0x0000002c
0037 
0038 #define TXFCR_OFFSET                0x0000003c
0039 #define TXFCR_FIFO_FLUSH_MASK           0x00000080
0040 #define TXFCR_FIFO_EN_MASK          0x00000040
0041 
0042 #define IER_OFFSET              0x00000044
0043 #define IER_READ_COMPLETE_INT_MASK      0x00000010
0044 #define IER_I2C_INT_EN_MASK         0x00000008
0045 #define IER_FIFO_INT_EN_MASK            0x00000002
0046 #define IER_NOACK_EN_MASK           0x00000001
0047 
0048 #define ISR_OFFSET              0x00000048
0049 #define ISR_RESERVED_MASK           0xffffff60
0050 #define ISR_CMDBUSY_MASK            0x00000080
0051 #define ISR_READ_COMPLETE_MASK          0x00000010
0052 #define ISR_SES_DONE_MASK           0x00000008
0053 #define ISR_ERR_MASK                0x00000004
0054 #define ISR_TXFIFOEMPTY_MASK            0x00000002
0055 #define ISR_NOACK_MASK              0x00000001
0056 
0057 #define CLKEN_OFFSET                0x0000004C
0058 #define CLKEN_AUTOSENSE_OFF_MASK        0x00000080
0059 #define CLKEN_M_SHIFT               4
0060 #define CLKEN_N_SHIFT               1
0061 #define CLKEN_CLKEN_MASK            0x00000001
0062 
0063 #define FIFO_STATUS_OFFSET          0x00000054
0064 #define FIFO_STATUS_RXFIFO_EMPTY_MASK       0x00000004
0065 #define FIFO_STATUS_TXFIFO_EMPTY_MASK       0x00000010
0066 
0067 #define HSTIM_OFFSET                0x00000058
0068 #define HSTIM_HS_MODE_MASK          0x00008000
0069 #define HSTIM_HS_HOLD_SHIFT         10
0070 #define HSTIM_HS_HIGH_PHASE_SHIFT       5
0071 #define HSTIM_HS_SETUP_SHIFT            0
0072 
0073 #define PADCTL_OFFSET               0x0000005c
0074 #define PADCTL_PAD_OUT_EN_MASK          0x00000004
0075 
0076 #define RXFCR_OFFSET                0x00000068
0077 #define RXFCR_NACK_EN_SHIFT         7
0078 #define RXFCR_READ_COUNT_SHIFT          0
0079 #define RXFIFORDOUT_OFFSET          0x0000006c
0080 
0081 /* Locally used constants */
0082 #define MAX_RX_FIFO_SIZE        64U /* bytes */
0083 #define MAX_TX_FIFO_SIZE        64U /* bytes */
0084 
0085 #define STD_EXT_CLK_FREQ        13000000UL
0086 #define HS_EXT_CLK_FREQ         104000000UL
0087 
0088 #define MASTERCODE          0x08 /* Mastercodes are 0000_1xxxb */
0089 
0090 #define I2C_TIMEOUT         100 /* msecs */
0091 
0092 /* Operations that can be commanded to the controller */
0093 enum bcm_kona_cmd_t {
0094     BCM_CMD_NOACTION = 0,
0095     BCM_CMD_START,
0096     BCM_CMD_RESTART,
0097     BCM_CMD_STOP,
0098 };
0099 
0100 enum bus_speed_index {
0101     BCM_SPD_100K = 0,
0102     BCM_SPD_400K,
0103     BCM_SPD_1MHZ,
0104 };
0105 
0106 enum hs_bus_speed_index {
0107     BCM_SPD_3P4MHZ = 0,
0108 };
0109 
0110 /* Internal divider settings for standard mode, fast mode and fast mode plus */
0111 struct bus_speed_cfg {
0112     uint8_t time_m;     /* Number of cycles for setup time */
0113     uint8_t time_n;     /* Number of cycles for hold time */
0114     uint8_t prescale;   /* Prescale divider */
0115     uint8_t time_p;     /* Timing coefficient */
0116     uint8_t no_div;     /* Disable clock divider */
0117     uint8_t time_div;   /* Post-prescale divider */
0118 };
0119 
0120 /* Internal divider settings for high-speed mode */
0121 struct hs_bus_speed_cfg {
0122     uint8_t hs_hold;    /* Number of clock cycles SCL stays low until
0123                    the end of bit period */
0124     uint8_t hs_high_phase;  /* Number of clock cycles SCL stays high
0125                    before it falls */
0126     uint8_t hs_setup;   /* Number of clock cycles SCL stays low
0127                    before it rises  */
0128     uint8_t prescale;   /* Prescale divider */
0129     uint8_t time_p;     /* Timing coefficient */
0130     uint8_t no_div;     /* Disable clock divider */
0131     uint8_t time_div;   /* Post-prescale divider */
0132 };
0133 
0134 static const struct bus_speed_cfg std_cfg_table[] = {
0135     [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
0136     [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
0137     [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
0138 };
0139 
0140 static const struct hs_bus_speed_cfg hs_cfg_table[] = {
0141     [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
0142 };
0143 
0144 struct bcm_kona_i2c_dev {
0145     struct device *device;
0146 
0147     void __iomem *base;
0148     int irq;
0149     struct clk *external_clk;
0150 
0151     struct i2c_adapter adapter;
0152 
0153     struct completion done;
0154 
0155     const struct bus_speed_cfg *std_cfg;
0156     const struct hs_bus_speed_cfg *hs_cfg;
0157 };
0158 
0159 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
0160                       enum bcm_kona_cmd_t cmd)
0161 {
0162     dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
0163 
0164     switch (cmd) {
0165     case BCM_CMD_NOACTION:
0166         writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
0167                (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
0168                dev->base + CS_OFFSET);
0169         break;
0170 
0171     case BCM_CMD_START:
0172         writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
0173                (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
0174                (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
0175                dev->base + CS_OFFSET);
0176         break;
0177 
0178     case BCM_CMD_RESTART:
0179         writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
0180                (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
0181                (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
0182                dev->base + CS_OFFSET);
0183         break;
0184 
0185     case BCM_CMD_STOP:
0186         writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
0187                (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
0188                dev->base + CS_OFFSET);
0189         break;
0190 
0191     default:
0192         dev_err(dev->device, "Unknown command %d\n", cmd);
0193     }
0194 }
0195 
0196 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
0197 {
0198     writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
0199            dev->base + CLKEN_OFFSET);
0200 }
0201 
0202 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
0203 {
0204     writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
0205            dev->base + CLKEN_OFFSET);
0206 }
0207 
0208 static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid)
0209 {
0210     struct bcm_kona_i2c_dev *dev = devid;
0211     uint32_t status = readl(dev->base + ISR_OFFSET);
0212 
0213     if ((status & ~ISR_RESERVED_MASK) == 0)
0214         return IRQ_NONE;
0215 
0216     /* Must flush the TX FIFO when NAK detected */
0217     if (status & ISR_NOACK_MASK)
0218         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
0219                dev->base + TXFCR_OFFSET);
0220 
0221     writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
0222     complete(&dev->done);
0223 
0224     return IRQ_HANDLED;
0225 }
0226 
0227 /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */
0228 static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev)
0229 {
0230     unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
0231 
0232     while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)
0233         if (time_after(jiffies, timeout)) {
0234             dev_err(dev->device, "CMDBUSY timeout\n");
0235             return -ETIMEDOUT;
0236         }
0237 
0238     return 0;
0239 }
0240 
0241 /* Send command to I2C bus */
0242 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
0243                  enum bcm_kona_cmd_t cmd)
0244 {
0245     int rc;
0246     unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
0247 
0248     /* Make sure the hardware is ready */
0249     rc = bcm_kona_i2c_wait_if_busy(dev);
0250     if (rc < 0)
0251         return rc;
0252 
0253     /* Unmask the session done interrupt */
0254     writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
0255 
0256     /* Mark as incomplete before sending the command */
0257     reinit_completion(&dev->done);
0258 
0259     /* Send the command */
0260     bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
0261 
0262     /* Wait for transaction to finish or timeout */
0263     time_left = wait_for_completion_timeout(&dev->done, time_left);
0264 
0265     /* Mask all interrupts */
0266     writel(0, dev->base + IER_OFFSET);
0267 
0268     if (!time_left) {
0269         dev_err(dev->device, "controller timed out\n");
0270         rc = -ETIMEDOUT;
0271     }
0272 
0273     /* Clear command */
0274     bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
0275 
0276     return rc;
0277 }
0278 
0279 /* Read a single RX FIFO worth of data from the i2c bus */
0280 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
0281                      uint8_t *buf, unsigned int len,
0282                      unsigned int last_byte_nak)
0283 {
0284     unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
0285 
0286     /* Mark as incomplete before starting the RX FIFO */
0287     reinit_completion(&dev->done);
0288 
0289     /* Unmask the read complete interrupt */
0290     writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
0291 
0292     /* Start the RX FIFO */
0293     writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
0294            (len << RXFCR_READ_COUNT_SHIFT),
0295         dev->base + RXFCR_OFFSET);
0296 
0297     /* Wait for FIFO read to complete */
0298     time_left = wait_for_completion_timeout(&dev->done, time_left);
0299 
0300     /* Mask all interrupts */
0301     writel(0, dev->base + IER_OFFSET);
0302 
0303     if (!time_left) {
0304         dev_err(dev->device, "RX FIFO time out\n");
0305         return -EREMOTEIO;
0306     }
0307 
0308     /* Read data from FIFO */
0309     for (; len > 0; len--, buf++)
0310         *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
0311 
0312     return 0;
0313 }
0314 
0315 /* Read any amount of data using the RX FIFO from the i2c bus */
0316 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
0317                   struct i2c_msg *msg)
0318 {
0319     unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
0320     unsigned int last_byte_nak = 0;
0321     unsigned int bytes_read = 0;
0322     int rc;
0323 
0324     uint8_t *tmp_buf = msg->buf;
0325 
0326     while (bytes_read < msg->len) {
0327         if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
0328             last_byte_nak = 1; /* NAK last byte of transfer */
0329             bytes_to_read = msg->len - bytes_read;
0330         }
0331 
0332         rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
0333                            last_byte_nak);
0334         if (rc < 0)
0335             return -EREMOTEIO;
0336 
0337         bytes_read += bytes_to_read;
0338         tmp_buf += bytes_to_read;
0339     }
0340 
0341     return 0;
0342 }
0343 
0344 /* Write a single byte of data to the i2c bus */
0345 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
0346                    unsigned int nak_expected)
0347 {
0348     int rc;
0349     unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
0350     unsigned int nak_received;
0351 
0352     /* Make sure the hardware is ready */
0353     rc = bcm_kona_i2c_wait_if_busy(dev);
0354     if (rc < 0)
0355         return rc;
0356 
0357     /* Clear pending session done interrupt */
0358     writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
0359 
0360     /* Unmask the session done interrupt */
0361     writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
0362 
0363     /* Mark as incomplete before sending the data */
0364     reinit_completion(&dev->done);
0365 
0366     /* Send one byte of data */
0367     writel(data, dev->base + DAT_OFFSET);
0368 
0369     /* Wait for byte to be written */
0370     time_left = wait_for_completion_timeout(&dev->done, time_left);
0371 
0372     /* Mask all interrupts */
0373     writel(0, dev->base + IER_OFFSET);
0374 
0375     if (!time_left) {
0376         dev_dbg(dev->device, "controller timed out\n");
0377         return -ETIMEDOUT;
0378     }
0379 
0380     nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
0381 
0382     if (nak_received ^ nak_expected) {
0383         dev_dbg(dev->device, "unexpected NAK/ACK\n");
0384         return -EREMOTEIO;
0385     }
0386 
0387     return 0;
0388 }
0389 
0390 /* Write a single TX FIFO worth of data to the i2c bus */
0391 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
0392                       uint8_t *buf, unsigned int len)
0393 {
0394     int k;
0395     unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
0396     unsigned int fifo_status;
0397 
0398     /* Mark as incomplete before sending data to the TX FIFO */
0399     reinit_completion(&dev->done);
0400 
0401     /* Unmask the fifo empty and nak interrupt */
0402     writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
0403            dev->base + IER_OFFSET);
0404 
0405     /* Disable IRQ to load a FIFO worth of data without interruption */
0406     disable_irq(dev->irq);
0407 
0408     /* Write data into FIFO */
0409     for (k = 0; k < len; k++)
0410         writel(buf[k], (dev->base + DAT_OFFSET));
0411 
0412     /* Enable IRQ now that data has been loaded */
0413     enable_irq(dev->irq);
0414 
0415     /* Wait for FIFO to empty */
0416     do {
0417         time_left = wait_for_completion_timeout(&dev->done, time_left);
0418         fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
0419     } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
0420 
0421     /* Mask all interrupts */
0422     writel(0, dev->base + IER_OFFSET);
0423 
0424     /* Check if there was a NAK */
0425     if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
0426         dev_err(dev->device, "unexpected NAK\n");
0427         return -EREMOTEIO;
0428     }
0429 
0430     /* Check if a timeout occured */
0431     if (!time_left) {
0432         dev_err(dev->device, "completion timed out\n");
0433         return -EREMOTEIO;
0434     }
0435 
0436     return 0;
0437 }
0438 
0439 
0440 /* Write any amount of data using TX FIFO to the i2c bus */
0441 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
0442                    struct i2c_msg *msg)
0443 {
0444     unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
0445     unsigned int bytes_written = 0;
0446     int rc;
0447 
0448     uint8_t *tmp_buf = msg->buf;
0449 
0450     while (bytes_written < msg->len) {
0451         if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
0452             bytes_to_write = msg->len - bytes_written;
0453 
0454         rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
0455                             bytes_to_write);
0456         if (rc < 0)
0457             return -EREMOTEIO;
0458 
0459         bytes_written += bytes_to_write;
0460         tmp_buf += bytes_to_write;
0461     }
0462 
0463     return 0;
0464 }
0465 
0466 /* Send i2c address */
0467 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
0468                      struct i2c_msg *msg)
0469 {
0470     unsigned char addr;
0471 
0472     if (msg->flags & I2C_M_TEN) {
0473         /* First byte is 11110XX0 where XX is upper 2 bits */
0474         addr = 0xF0 | ((msg->addr & 0x300) >> 7);
0475         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
0476             return -EREMOTEIO;
0477 
0478         /* Second byte is the remaining 8 bits */
0479         addr = msg->addr & 0xFF;
0480         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
0481             return -EREMOTEIO;
0482 
0483         if (msg->flags & I2C_M_RD) {
0484             /* For read, send restart command */
0485             if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
0486                 return -EREMOTEIO;
0487 
0488             /* Then re-send the first byte with the read bit set */
0489             addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
0490             if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
0491                 return -EREMOTEIO;
0492         }
0493     } else {
0494         addr = i2c_8bit_addr_from_msg(msg);
0495 
0496         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
0497             return -EREMOTEIO;
0498     }
0499 
0500     return 0;
0501 }
0502 
0503 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
0504 {
0505     writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
0506            dev->base + CLKEN_OFFSET);
0507 }
0508 
0509 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
0510 {
0511     writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
0512            dev->base + HSTIM_OFFSET);
0513 
0514     writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
0515            (dev->std_cfg->time_p << TIM_P_SHIFT) |
0516            (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
0517            (dev->std_cfg->time_div  << TIM_DIV_SHIFT),
0518            dev->base + TIM_OFFSET);
0519 
0520     writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
0521            (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
0522            CLKEN_CLKEN_MASK,
0523            dev->base + CLKEN_OFFSET);
0524 }
0525 
0526 static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
0527 {
0528     writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
0529            (dev->hs_cfg->time_p << TIM_P_SHIFT) |
0530            (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) |
0531            (dev->hs_cfg->time_div << TIM_DIV_SHIFT),
0532            dev->base + TIM_OFFSET);
0533 
0534     writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
0535            (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) |
0536            (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT),
0537            dev->base + HSTIM_OFFSET);
0538 
0539     writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
0540            dev->base + HSTIM_OFFSET);
0541 }
0542 
0543 static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
0544 {
0545     int rc;
0546 
0547     /* Send mastercode at standard speed */
0548     rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
0549     if (rc < 0) {
0550         pr_err("High speed handshake failed\n");
0551         return rc;
0552     }
0553 
0554     /* Configure external clock to higher frequency */
0555     rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ);
0556     if (rc) {
0557         dev_err(dev->device, "%s: clk_set_rate returned %d\n",
0558             __func__, rc);
0559         return rc;
0560     }
0561 
0562     /* Reconfigure internal dividers */
0563     bcm_kona_i2c_config_timing_hs(dev);
0564 
0565     /* Send a restart command */
0566     rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
0567     if (rc < 0)
0568         dev_err(dev->device, "High speed restart command failed\n");
0569 
0570     return rc;
0571 }
0572 
0573 static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev)
0574 {
0575     int rc;
0576 
0577     /* Reconfigure internal dividers */
0578     bcm_kona_i2c_config_timing(dev);
0579 
0580     /* Configure external clock to lower frequency */
0581     rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
0582     if (rc) {
0583         dev_err(dev->device, "%s: clk_set_rate returned %d\n",
0584             __func__, rc);
0585     }
0586 
0587     return rc;
0588 }
0589 
0590 /* Master transfer function */
0591 static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter,
0592                  struct i2c_msg msgs[], int num)
0593 {
0594     struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter);
0595     struct i2c_msg *pmsg;
0596     int rc = 0;
0597     int i;
0598 
0599     rc = clk_prepare_enable(dev->external_clk);
0600     if (rc) {
0601         dev_err(dev->device, "%s: peri clock enable failed. err %d\n",
0602             __func__, rc);
0603         return rc;
0604     }
0605 
0606     /* Enable pad output */
0607     writel(0, dev->base + PADCTL_OFFSET);
0608 
0609     /* Enable internal clocks */
0610     bcm_kona_i2c_enable_clock(dev);
0611 
0612     /* Send start command */
0613     rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
0614     if (rc < 0) {
0615         dev_err(dev->device, "Start command failed rc = %d\n", rc);
0616         goto xfer_disable_pad;
0617     }
0618 
0619     /* Switch to high speed if applicable */
0620     if (dev->hs_cfg) {
0621         rc = bcm_kona_i2c_switch_to_hs(dev);
0622         if (rc < 0)
0623             goto xfer_send_stop;
0624     }
0625 
0626     /* Loop through all messages */
0627     for (i = 0; i < num; i++) {
0628         pmsg = &msgs[i];
0629 
0630         /* Send restart for subsequent messages */
0631         if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
0632             rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
0633             if (rc < 0) {
0634                 dev_err(dev->device,
0635                     "restart cmd failed rc = %d\n", rc);
0636                 goto xfer_send_stop;
0637             }
0638         }
0639 
0640         /* Send slave address */
0641         if (!(pmsg->flags & I2C_M_NOSTART)) {
0642             rc = bcm_kona_i2c_do_addr(dev, pmsg);
0643             if (rc < 0) {
0644                 dev_err(dev->device,
0645                     "NAK from addr %2.2x msg#%d rc = %d\n",
0646                     pmsg->addr, i, rc);
0647                 goto xfer_send_stop;
0648             }
0649         }
0650 
0651         /* Perform data transfer */
0652         if (pmsg->flags & I2C_M_RD) {
0653             rc = bcm_kona_i2c_read_fifo(dev, pmsg);
0654             if (rc < 0) {
0655                 dev_err(dev->device, "read failure\n");
0656                 goto xfer_send_stop;
0657             }
0658         } else {
0659             rc = bcm_kona_i2c_write_fifo(dev, pmsg);
0660             if (rc < 0) {
0661                 dev_err(dev->device, "write failure");
0662                 goto xfer_send_stop;
0663             }
0664         }
0665     }
0666 
0667     rc = num;
0668 
0669 xfer_send_stop:
0670     /* Send a STOP command */
0671     bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
0672 
0673     /* Return from high speed if applicable */
0674     if (dev->hs_cfg) {
0675         int hs_rc = bcm_kona_i2c_switch_to_std(dev);
0676 
0677         if (hs_rc)
0678             rc = hs_rc;
0679     }
0680 
0681 xfer_disable_pad:
0682     /* Disable pad output */
0683     writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
0684 
0685     /* Stop internal clock */
0686     bcm_kona_i2c_disable_clock(dev);
0687 
0688     clk_disable_unprepare(dev->external_clk);
0689 
0690     return rc;
0691 }
0692 
0693 static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap)
0694 {
0695     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
0696         I2C_FUNC_NOSTART;
0697 }
0698 
0699 static const struct i2c_algorithm bcm_algo = {
0700     .master_xfer = bcm_kona_i2c_xfer,
0701     .functionality = bcm_kona_i2c_functionality,
0702 };
0703 
0704 static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev)
0705 {
0706     unsigned int bus_speed;
0707     int ret = of_property_read_u32(dev->device->of_node, "clock-frequency",
0708                        &bus_speed);
0709     if (ret < 0) {
0710         dev_err(dev->device, "missing clock-frequency property\n");
0711         return -ENODEV;
0712     }
0713 
0714     switch (bus_speed) {
0715     case I2C_MAX_STANDARD_MODE_FREQ:
0716         dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
0717         break;
0718     case I2C_MAX_FAST_MODE_FREQ:
0719         dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
0720         break;
0721     case I2C_MAX_FAST_MODE_PLUS_FREQ:
0722         dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
0723         break;
0724     case I2C_MAX_HIGH_SPEED_MODE_FREQ:
0725         /* Send mastercode at 100k */
0726         dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
0727         dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ];
0728         break;
0729     default:
0730         pr_err("%d hz bus speed not supported\n", bus_speed);
0731         pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n");
0732         return -EINVAL;
0733     }
0734 
0735     return 0;
0736 }
0737 
0738 static int bcm_kona_i2c_probe(struct platform_device *pdev)
0739 {
0740     int rc = 0;
0741     struct bcm_kona_i2c_dev *dev;
0742     struct i2c_adapter *adap;
0743 
0744     /* Allocate memory for private data structure */
0745     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0746     if (!dev)
0747         return -ENOMEM;
0748 
0749     platform_set_drvdata(pdev, dev);
0750     dev->device = &pdev->dev;
0751     init_completion(&dev->done);
0752 
0753     /* Map hardware registers */
0754     dev->base = devm_platform_ioremap_resource(pdev, 0);
0755     if (IS_ERR(dev->base))
0756         return PTR_ERR(dev->base);
0757 
0758     /* Get and enable external clock */
0759     dev->external_clk = devm_clk_get(dev->device, NULL);
0760     if (IS_ERR(dev->external_clk)) {
0761         dev_err(dev->device, "couldn't get clock\n");
0762         return -ENODEV;
0763     }
0764 
0765     rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
0766     if (rc) {
0767         dev_err(dev->device, "%s: clk_set_rate returned %d\n",
0768             __func__, rc);
0769         return rc;
0770     }
0771 
0772     rc = clk_prepare_enable(dev->external_clk);
0773     if (rc) {
0774         dev_err(dev->device, "couldn't enable clock\n");
0775         return rc;
0776     }
0777 
0778     /* Parse bus speed */
0779     rc = bcm_kona_i2c_assign_bus_speed(dev);
0780     if (rc)
0781         goto probe_disable_clk;
0782 
0783     /* Enable internal clocks */
0784     bcm_kona_i2c_enable_clock(dev);
0785 
0786     /* Configure internal dividers */
0787     bcm_kona_i2c_config_timing(dev);
0788 
0789     /* Disable timeout */
0790     writel(0, dev->base + TOUT_OFFSET);
0791 
0792     /* Enable autosense */
0793     bcm_kona_i2c_enable_autosense(dev);
0794 
0795     /* Enable TX FIFO */
0796     writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
0797            dev->base + TXFCR_OFFSET);
0798 
0799     /* Mask all interrupts */
0800     writel(0, dev->base + IER_OFFSET);
0801 
0802     /* Clear all pending interrupts */
0803     writel(ISR_CMDBUSY_MASK |
0804            ISR_READ_COMPLETE_MASK |
0805            ISR_SES_DONE_MASK |
0806            ISR_ERR_MASK |
0807            ISR_TXFIFOEMPTY_MASK |
0808            ISR_NOACK_MASK,
0809            dev->base + ISR_OFFSET);
0810 
0811     /* Get the interrupt number */
0812     dev->irq = platform_get_irq(pdev, 0);
0813     if (dev->irq < 0) {
0814         rc = dev->irq;
0815         goto probe_disable_clk;
0816     }
0817 
0818     /* register the ISR handler */
0819     rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr,
0820                   IRQF_SHARED, pdev->name, dev);
0821     if (rc) {
0822         dev_err(dev->device, "failed to request irq %i\n", dev->irq);
0823         goto probe_disable_clk;
0824     }
0825 
0826     /* Enable the controller but leave it idle */
0827     bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
0828 
0829     /* Disable pad output */
0830     writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
0831 
0832     /* Disable internal clock */
0833     bcm_kona_i2c_disable_clock(dev);
0834 
0835     /* Disable external clock */
0836     clk_disable_unprepare(dev->external_clk);
0837 
0838     /* Add the i2c adapter */
0839     adap = &dev->adapter;
0840     i2c_set_adapdata(adap, dev);
0841     adap->owner = THIS_MODULE;
0842     strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
0843     adap->algo = &bcm_algo;
0844     adap->dev.parent = &pdev->dev;
0845     adap->dev.of_node = pdev->dev.of_node;
0846 
0847     rc = i2c_add_adapter(adap);
0848     if (rc)
0849         return rc;
0850 
0851     dev_info(dev->device, "device registered successfully\n");
0852 
0853     return 0;
0854 
0855 probe_disable_clk:
0856     bcm_kona_i2c_disable_clock(dev);
0857     clk_disable_unprepare(dev->external_clk);
0858 
0859     return rc;
0860 }
0861 
0862 static int bcm_kona_i2c_remove(struct platform_device *pdev)
0863 {
0864     struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev);
0865 
0866     i2c_del_adapter(&dev->adapter);
0867 
0868     return 0;
0869 }
0870 
0871 static const struct of_device_id bcm_kona_i2c_of_match[] = {
0872     {.compatible = "brcm,kona-i2c",},
0873     {},
0874 };
0875 MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match);
0876 
0877 static struct platform_driver bcm_kona_i2c_driver = {
0878     .driver = {
0879            .name = "bcm-kona-i2c",
0880            .of_match_table = bcm_kona_i2c_of_match,
0881            },
0882     .probe = bcm_kona_i2c_probe,
0883     .remove = bcm_kona_i2c_remove,
0884 };
0885 module_platform_driver(bcm_kona_i2c_driver);
0886 
0887 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
0888 MODULE_DESCRIPTION("Broadcom Kona I2C Driver");
0889 MODULE_LICENSE("GPL v2");
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