i2c/busses/i2c-axxia.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This driver implements I2C master functionality using the LSI API2C
0004  * controller.
0005  *
0006  * NOTE: The controller has a limitation in that it can only do transfers of
0007  * maximum 255 bytes at a time. If a larger transfer is attempted, error code
0008  * (-EINVAL) is returned.
0009  */
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/delay.h>
0013 #include <linux/err.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/module.h>
0018 #include <linux/io.h>
0019 #include <linux/kernel.h>
0020 #include <linux/platform_device.h>
0021
0022 #define SCL_WAIT_TIMEOUT_NS 25000000
0023 #define I2C_XFER_TIMEOUT    (msecs_to_jiffies(250))
0024 #define I2C_STOP_TIMEOUT    (msecs_to_jiffies(100))
0025 #define FIFO_SIZE           8
0026 #define SEQ_LEN             2
0027
0028 #define GLOBAL_CONTROL      0x00
0029 #define   GLOBAL_MST_EN         BIT(0)
0030 #define   GLOBAL_SLV_EN         BIT(1)
0031 #define   GLOBAL_IBML_EN        BIT(2)
0032 #define INTERRUPT_STATUS    0x04
0033 #define INTERRUPT_ENABLE    0x08
0034 #define   INT_SLV               BIT(1)
0035 #define   INT_MST               BIT(0)
0036 #define WAIT_TIMER_CONTROL  0x0c
0037 #define   WT_EN         BIT(15)
0038 #define   WT_VALUE(_x)      ((_x) & 0x7fff)
0039 #define IBML_TIMEOUT        0x10
0040 #define IBML_LOW_MEXT       0x14
0041 #define IBML_LOW_SEXT       0x18
0042 #define TIMER_CLOCK_DIV     0x1c
0043 #define I2C_BUS_MONITOR     0x20
0044 #define   BM_SDAC       BIT(3)
0045 #define   BM_SCLC       BIT(2)
0046 #define   BM_SDAS       BIT(1)
0047 #define   BM_SCLS       BIT(0)
0048 #define SOFT_RESET      0x24
0049 #define MST_COMMAND     0x28
0050 #define   CMD_BUSY      (1<<3)
0051 #define   CMD_MANUAL        (0x00 | CMD_BUSY)
0052 #define   CMD_AUTO      (0x01 | CMD_BUSY)
0053 #define   CMD_SEQUENCE      (0x02 | CMD_BUSY)
0054 #define MST_RX_XFER     0x2c
0055 #define MST_TX_XFER     0x30
0056 #define MST_ADDR_1      0x34
0057 #define MST_ADDR_2      0x38
0058 #define MST_DATA        0x3c
0059 #define MST_TX_FIFO     0x40
0060 #define MST_RX_FIFO     0x44
0061 #define MST_INT_ENABLE      0x48
0062 #define MST_INT_STATUS      0x4c
0063 #define   MST_STATUS_RFL    (1 << 13) /* RX FIFO serivce */
0064 #define   MST_STATUS_TFL    (1 << 12) /* TX FIFO service */
0065 #define   MST_STATUS_SNS    (1 << 11) /* Manual mode done */
0066 #define   MST_STATUS_SS     (1 << 10) /* Automatic mode done */
0067 #define   MST_STATUS_SCC    (1 << 9)  /* Stop complete */
0068 #define   MST_STATUS_IP     (1 << 8)  /* Invalid parameter */
0069 #define   MST_STATUS_TSS    (1 << 7)  /* Timeout */
0070 #define   MST_STATUS_AL     (1 << 6)  /* Arbitration lost */
0071 #define   MST_STATUS_ND     (1 << 5)  /* NAK on data phase */
0072 #define   MST_STATUS_NA     (1 << 4)  /* NAK on address phase */
0073 #define   MST_STATUS_NAK    (MST_STATUS_NA | \
0074                  MST_STATUS_ND)
0075 #define   MST_STATUS_ERR    (MST_STATUS_NAK | \
0076                  MST_STATUS_AL  | \
0077                  MST_STATUS_IP)
0078 #define MST_TX_BYTES_XFRD   0x50
0079 #define MST_RX_BYTES_XFRD   0x54
0080 #define SLV_ADDR_DEC_CTL    0x58
0081 #define   SLV_ADDR_DEC_GCE  BIT(0)  /* ACK to General Call Address from own master (loopback) */
0082 #define   SLV_ADDR_DEC_OGCE BIT(1)  /* ACK to General Call Address from external masters */
0083 #define   SLV_ADDR_DEC_SA1E BIT(2)  /* ACK to addr_1 enabled */
0084 #define   SLV_ADDR_DEC_SA1M BIT(3)  /* 10-bit addressing for addr_1 enabled */
0085 #define   SLV_ADDR_DEC_SA2E BIT(4)  /* ACK to addr_2 enabled */
0086 #define   SLV_ADDR_DEC_SA2M BIT(5)  /* 10-bit addressing for addr_2 enabled */
0087 #define SLV_ADDR_1      0x5c
0088 #define SLV_ADDR_2      0x60
0089 #define SLV_RX_CTL      0x64
0090 #define   SLV_RX_ACSA1      BIT(0)  /* Generate ACK for writes to addr_1 */
0091 #define   SLV_RX_ACSA2      BIT(1)  /* Generate ACK for writes to addr_2 */
0092 #define   SLV_RX_ACGCA      BIT(2)  /* ACK data phase transfers to General Call Address */
0093 #define SLV_DATA        0x68
0094 #define SLV_RX_FIFO     0x6c
0095 #define   SLV_FIFO_DV1      BIT(0)  /* Data Valid for addr_1 */
0096 #define   SLV_FIFO_DV2      BIT(1)  /* Data Valid for addr_2 */
0097 #define   SLV_FIFO_AS       BIT(2)  /* (N)ACK Sent */
0098 #define   SLV_FIFO_TNAK     BIT(3)  /* Timeout NACK */
0099 #define   SLV_FIFO_STRC     BIT(4)  /* First byte after start condition received */
0100 #define   SLV_FIFO_RSC      BIT(5)  /* Repeated Start Condition */
0101 #define   SLV_FIFO_STPC     BIT(6)  /* Stop Condition */
0102 #define   SLV_FIFO_DV       (SLV_FIFO_DV1 | SLV_FIFO_DV2)
0103 #define SLV_INT_ENABLE      0x70
0104 #define SLV_INT_STATUS      0x74
0105 #define   SLV_STATUS_RFH    BIT(0)  /* FIFO service */
0106 #define   SLV_STATUS_WTC    BIT(1)  /* Write transfer complete */
0107 #define   SLV_STATUS_SRS1   BIT(2)  /* Slave read from addr 1 */
0108 #define   SLV_STATUS_SRRS1  BIT(3)  /* Repeated start from addr 1 */
0109 #define   SLV_STATUS_SRND1  BIT(4)  /* Read request not following start condition */
0110 #define   SLV_STATUS_SRC1   BIT(5)  /* Read canceled */
0111 #define   SLV_STATUS_SRAT1  BIT(6)  /* Slave Read timed out */
0112 #define   SLV_STATUS_SRDRE1 BIT(7)  /* Data written after timed out */
0113 #define SLV_READ_DUMMY      0x78
0114 #define SCL_HIGH_PERIOD     0x80
0115 #define SCL_LOW_PERIOD      0x84
0116 #define SPIKE_FLTR_LEN      0x88
0117 #define SDA_SETUP_TIME      0x8c
0118 #define SDA_HOLD_TIME       0x90
0119
0120 /**
0121  * axxia_i2c_dev - I2C device context
0122  * @base: pointer to register struct
0123  * @msg: pointer to current message
0124  * @msg_r: pointer to current read message (sequence transfer)
0125  * @msg_xfrd: number of bytes transferred in tx_fifo
0126  * @msg_xfrd_r: number of bytes transferred in rx_fifo
0127  * @msg_err: error code for completed message
0128  * @msg_complete: xfer completion object
0129  * @dev: device reference
0130  * @adapter: core i2c abstraction
0131  * @i2c_clk: clock reference for i2c input clock
0132  * @bus_clk_rate: current i2c bus clock rate
0133  * @last: a flag indicating is this is last message in transfer
0134  */
0135 struct axxia_i2c_dev {
0136     void __iomem *base;
0137     struct i2c_msg *msg;
0138     struct i2c_msg *msg_r;
0139     size_t msg_xfrd;
0140     size_t msg_xfrd_r;
0141     int msg_err;
0142     struct completion msg_complete;
0143     struct device *dev;
0144     struct i2c_adapter adapter;
0145     struct clk *i2c_clk;
0146     u32 bus_clk_rate;
0147     bool last;
0148     struct i2c_client *slave;
0149     int irq;
0150 };
0151
0152 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
0153 {
0154     u32 int_en;
0155
0156     int_en = readl(idev->base + MST_INT_ENABLE);
0157     writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
0158 }
0159
0160 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
0161 {
0162     u32 int_en;
0163
0164     int_en = readl(idev->base + MST_INT_ENABLE);
0165     writel(int_en | mask, idev->base + MST_INT_ENABLE);
0166 }
0167
0168 /**
0169  * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
0170  */
0171 static u32 ns_to_clk(u64 ns, u32 clk_mhz)
0172 {
0173     return div_u64(ns * clk_mhz, 1000);
0174 }
0175
0176 static int axxia_i2c_init(struct axxia_i2c_dev *idev)
0177 {
0178     u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
0179     u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
0180     u32 t_setup;
0181     u32 t_high, t_low;
0182     u32 tmo_clk;
0183     u32 prescale;
0184     unsigned long timeout;
0185
0186     dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
0187         idev->bus_clk_rate, clk_mhz, divisor);
0188
0189     /* Reset controller */
0190     writel(0x01, idev->base + SOFT_RESET);
0191     timeout = jiffies + msecs_to_jiffies(100);
0192     while (readl(idev->base + SOFT_RESET) & 1) {
0193         if (time_after(jiffies, timeout)) {
0194             dev_warn(idev->dev, "Soft reset failed\n");
0195             break;
0196         }
0197     }
0198
0199     /* Enable Master Mode */
0200     writel(0x1, idev->base + GLOBAL_CONTROL);
0201
0202     if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
0203         /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
0204         t_high = divisor * 1 / 2;
0205         t_low = divisor * 1 / 2;
0206         t_setup = ns_to_clk(250, clk_mhz);
0207     } else {
0208         /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
0209         t_high = divisor * 1 / 3;
0210         t_low = divisor * 2 / 3;
0211         t_setup = ns_to_clk(100, clk_mhz);
0212     }
0213
0214     /* SCL High Time */
0215     writel(t_high, idev->base + SCL_HIGH_PERIOD);
0216     /* SCL Low Time */
0217     writel(t_low, idev->base + SCL_LOW_PERIOD);
0218     /* SDA Setup Time */
0219     writel(t_setup, idev->base + SDA_SETUP_TIME);
0220     /* SDA Hold Time, 300ns */
0221     writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
0222     /* Filter <50ns spikes */
0223     writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
0224
0225     /* Configure Time-Out Registers */
0226     tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
0227
0228     /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
0229     for (prescale = 0; prescale < 15; ++prescale) {
0230         if (tmo_clk <= 0x7fff)
0231             break;
0232         tmo_clk >>= 1;
0233     }
0234     if (tmo_clk > 0x7fff)
0235         tmo_clk = 0x7fff;
0236
0237     /* Prescale divider (log2) */
0238     writel(prescale, idev->base + TIMER_CLOCK_DIV);
0239     /* Timeout in divided clocks */
0240     writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
0241
0242     /* Mask all master interrupt bits */
0243     i2c_int_disable(idev, ~0);
0244
0245     /* Interrupt enable */
0246     writel(0x01, idev->base + INTERRUPT_ENABLE);
0247
0248     return 0;
0249 }
0250
0251 static int i2c_m_rd(const struct i2c_msg *msg)
0252 {
0253     return (msg->flags & I2C_M_RD) != 0;
0254 }
0255
0256 static int i2c_m_ten(const struct i2c_msg *msg)
0257 {
0258     return (msg->flags & I2C_M_TEN) != 0;
0259 }
0260
0261 static int i2c_m_recv_len(const struct i2c_msg *msg)
0262 {
0263     return (msg->flags & I2C_M_RECV_LEN) != 0;
0264 }
0265
0266 /**
0267  * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
0268  * transfer length if this is the first byte of such a transfer.
0269  */
0270 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
0271 {
0272     struct i2c_msg *msg = idev->msg_r;
0273     size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
0274     int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
0275
0276     while (bytes_to_transfer-- > 0) {
0277         int c = readl(idev->base + MST_DATA);
0278
0279         if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
0280             /*
0281              * Check length byte for SMBus block read
0282              */
0283             if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
0284                 idev->msg_err = -EPROTO;
0285                 i2c_int_disable(idev, ~MST_STATUS_TSS);
0286                 complete(&idev->msg_complete);
0287                 break;
0288             }
0289             msg->len = 1 + c;
0290             writel(msg->len, idev->base + MST_RX_XFER);
0291         }
0292         msg->buf[idev->msg_xfrd_r++] = c;
0293     }
0294
0295     return 0;
0296 }
0297
0298 /**
0299  * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
0300  * @return: Number of bytes left to transfer.
0301  */
0302 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
0303 {
0304     struct i2c_msg *msg = idev->msg;
0305     size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
0306     int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
0307     int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
0308
0309     while (bytes_to_transfer-- > 0)
0310         writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
0311
0312     return ret;
0313 }
0314
0315 static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
0316 {
0317     u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
0318     u8 val;
0319
0320     dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
0321
0322     if (fifo_status & SLV_FIFO_DV1) {
0323         if (fifo_status & SLV_FIFO_STRC)
0324             i2c_slave_event(idev->slave,
0325                     I2C_SLAVE_WRITE_REQUESTED, &val);
0326
0327         val = readl(idev->base + SLV_DATA);
0328         i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
0329     }
0330     if (fifo_status & SLV_FIFO_STPC) {
0331         readl(idev->base + SLV_DATA); /* dummy read */
0332         i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
0333     }
0334     if (fifo_status & SLV_FIFO_RSC)
0335         readl(idev->base + SLV_DATA); /* dummy read */
0336 }
0337
0338 static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
0339 {
0340     u32 status = readl(idev->base + SLV_INT_STATUS);
0341     u8 val;
0342
0343     dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
0344
0345     if (status & SLV_STATUS_RFH)
0346         axxia_i2c_slv_fifo_event(idev);
0347     if (status & SLV_STATUS_SRS1) {
0348         i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
0349         writel(val, idev->base + SLV_DATA);
0350     }
0351     if (status & SLV_STATUS_SRND1) {
0352         i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
0353         writel(val, idev->base + SLV_DATA);
0354     }
0355     if (status & SLV_STATUS_SRC1)
0356         i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
0357
0358     writel(INT_SLV, idev->base + INTERRUPT_STATUS);
0359     return IRQ_HANDLED;
0360 }
0361
0362 static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
0363 {
0364     struct axxia_i2c_dev *idev = _dev;
0365     irqreturn_t ret = IRQ_NONE;
0366     u32 status;
0367
0368     status = readl(idev->base + INTERRUPT_STATUS);
0369
0370     if (status & INT_SLV)
0371         ret = axxia_i2c_slv_isr(idev);
0372     if (!(status & INT_MST))
0373         return ret;
0374
0375     /* Read interrupt status bits */
0376     status = readl(idev->base + MST_INT_STATUS);
0377
0378     if (!idev->msg) {
0379         dev_warn(idev->dev, "unexpected interrupt\n");
0380         goto out;
0381     }
0382
0383     /* RX FIFO needs service? */
0384     if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
0385         axxia_i2c_empty_rx_fifo(idev);
0386
0387     /* TX FIFO needs service? */
0388     if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
0389         if (axxia_i2c_fill_tx_fifo(idev) == 0)
0390             i2c_int_disable(idev, MST_STATUS_TFL);
0391     }
0392
0393     if (unlikely(status & MST_STATUS_ERR)) {
0394         /* Transfer error */
0395         i2c_int_disable(idev, ~0);
0396         if (status & MST_STATUS_AL)
0397             idev->msg_err = -EAGAIN;
0398         else if (status & MST_STATUS_NAK)
0399             idev->msg_err = -ENXIO;
0400         else
0401             idev->msg_err = -EIO;
0402         dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
0403             status,
0404             idev->msg->addr,
0405             readl(idev->base + MST_RX_BYTES_XFRD),
0406             readl(idev->base + MST_RX_XFER),
0407             readl(idev->base + MST_TX_BYTES_XFRD),
0408             readl(idev->base + MST_TX_XFER));
0409         complete(&idev->msg_complete);
0410     } else if (status & MST_STATUS_SCC) {
0411         /* Stop completed */
0412         i2c_int_disable(idev, ~MST_STATUS_TSS);
0413         complete(&idev->msg_complete);
0414     } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
0415         /* Transfer done */
0416         int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
0417
0418         i2c_int_disable(idev, mask);
0419         if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
0420             axxia_i2c_empty_rx_fifo(idev);
0421         complete(&idev->msg_complete);
0422     } else if (status & MST_STATUS_TSS) {
0423         /* Transfer timeout */
0424         idev->msg_err = -ETIMEDOUT;
0425         i2c_int_disable(idev, ~MST_STATUS_TSS);
0426         complete(&idev->msg_complete);
0427     }
0428
0429 out:
0430     /* Clear interrupt */
0431     writel(INT_MST, idev->base + INTERRUPT_STATUS);
0432
0433     return IRQ_HANDLED;
0434 }
0435
0436 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
0437 {
0438     u32 addr_1, addr_2;
0439
0440     if (i2c_m_ten(msg)) {
0441         /* 10-bit address
0442          *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
0443          *   addr_2: addr[7:0]
0444          */
0445         addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
0446         if (i2c_m_rd(msg))
0447             addr_1 |= 1;    /* Set the R/nW bit of the address */
0448         addr_2 = msg->addr & 0xFF;
0449     } else {
0450         /* 7-bit address
0451          *   addr_1: addr[6:0] | (R/nW)
0452          *   addr_2: dont care
0453          */
0454         addr_1 = i2c_8bit_addr_from_msg(msg);
0455         addr_2 = 0;
0456     }
0457
0458     writel(addr_1, idev->base + MST_ADDR_1);
0459     writel(addr_2, idev->base + MST_ADDR_2);
0460 }
0461
0462 /* The NAK interrupt will be sent _before_ issuing STOP command
0463  * so the controller might still be busy processing it. No
0464  * interrupt will be sent at the end so we have to poll for it
0465  */
0466 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
0467 {
0468     unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
0469
0470     do {
0471         if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
0472             return 0;
0473         usleep_range(1, 100);
0474     } while (time_before(jiffies, timeout));
0475
0476     return -ETIMEDOUT;
0477 }
0478
0479 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
0480 {
0481     u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
0482     u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
0483     unsigned long time_left;
0484
0485     axxia_i2c_set_addr(idev, &msgs[0]);
0486
0487     writel(msgs[0].len, idev->base + MST_TX_XFER);
0488     writel(rlen, idev->base + MST_RX_XFER);
0489
0490     idev->msg = &msgs[0];
0491     idev->msg_r = &msgs[1];
0492     idev->msg_xfrd = 0;
0493     idev->msg_xfrd_r = 0;
0494     idev->last = true;
0495     axxia_i2c_fill_tx_fifo(idev);
0496
0497     writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
0498
0499     reinit_completion(&idev->msg_complete);
0500     i2c_int_enable(idev, int_mask);
0501
0502     time_left = wait_for_completion_timeout(&idev->msg_complete,
0503                         I2C_XFER_TIMEOUT);
0504
0505     if (idev->msg_err == -ENXIO) {
0506         if (axxia_i2c_handle_seq_nak(idev))
0507             axxia_i2c_init(idev);
0508     } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
0509         dev_warn(idev->dev, "busy after xfer\n");
0510     }
0511
0512     if (time_left == 0) {
0513         idev->msg_err = -ETIMEDOUT;
0514         i2c_recover_bus(&idev->adapter);
0515         axxia_i2c_init(idev);
0516     }
0517
0518     if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
0519         axxia_i2c_init(idev);
0520
0521     return idev->msg_err;
0522 }
0523
0524 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
0525                   bool last)
0526 {
0527     u32 int_mask = MST_STATUS_ERR;
0528     u32 rx_xfer, tx_xfer;
0529     unsigned long time_left;
0530     unsigned int wt_value;
0531
0532     idev->msg = msg;
0533     idev->msg_r = msg;
0534     idev->msg_xfrd = 0;
0535     idev->msg_xfrd_r = 0;
0536     idev->last = last;
0537     reinit_completion(&idev->msg_complete);
0538
0539     axxia_i2c_set_addr(idev, msg);
0540
0541     if (i2c_m_rd(msg)) {
0542         /* I2C read transfer */
0543         rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
0544         tx_xfer = 0;
0545     } else {
0546         /* I2C write transfer */
0547         rx_xfer = 0;
0548         tx_xfer = msg->len;
0549     }
0550
0551     writel(rx_xfer, idev->base + MST_RX_XFER);
0552     writel(tx_xfer, idev->base + MST_TX_XFER);
0553
0554     if (i2c_m_rd(msg))
0555         int_mask |= MST_STATUS_RFL;
0556     else if (axxia_i2c_fill_tx_fifo(idev) != 0)
0557         int_mask |= MST_STATUS_TFL;
0558
0559     wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
0560     /* Disable wait timer temporarly */
0561     writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
0562     /* Check if timeout error happened */
0563     if (idev->msg_err)
0564         goto out;
0565
0566     if (!last) {
0567         writel(CMD_MANUAL, idev->base + MST_COMMAND);
0568         int_mask |= MST_STATUS_SNS;
0569     } else {
0570         writel(CMD_AUTO, idev->base + MST_COMMAND);
0571         int_mask |= MST_STATUS_SS;
0572     }
0573
0574     writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
0575
0576     i2c_int_enable(idev, int_mask);
0577
0578     time_left = wait_for_completion_timeout(&idev->msg_complete,
0579                           I2C_XFER_TIMEOUT);
0580
0581     i2c_int_disable(idev, int_mask);
0582
0583     if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
0584         dev_warn(idev->dev, "busy after xfer\n");
0585
0586     if (time_left == 0) {
0587         idev->msg_err = -ETIMEDOUT;
0588         i2c_recover_bus(&idev->adapter);
0589         axxia_i2c_init(idev);
0590     }
0591
0592 out:
0593     if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
0594             idev->msg_err != -ETIMEDOUT)
0595         axxia_i2c_init(idev);
0596
0597     return idev->msg_err;
0598 }
0599
0600 /* This function checks if the msgs[] array contains messages compatible with
0601  * Sequence mode of operation. This mode assumes there will be exactly one
0602  * write of non-zero length followed by exactly one read of non-zero length,
0603  * both targeted at the same client device.
0604  */
0605 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
0606 {
0607     return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
0608            msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
0609            msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
0610 }
0611
0612 static int
0613 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0614 {
0615     struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
0616     int i;
0617     int ret = 0;
0618
0619     idev->msg_err = 0;
0620
0621     if (axxia_i2c_sequence_ok(msgs, num)) {
0622         ret = axxia_i2c_xfer_seq(idev, msgs);
0623         return ret ? : SEQ_LEN;
0624     }
0625
0626     i2c_int_enable(idev, MST_STATUS_TSS);
0627
0628     for (i = 0; ret == 0 && i < num; ++i)
0629         ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
0630
0631     return ret ? : i;
0632 }
0633
0634 static int axxia_i2c_get_scl(struct i2c_adapter *adap)
0635 {
0636     struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
0637
0638     return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
0639 }
0640
0641 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
0642 {
0643     struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
0644     u32 tmp;
0645
0646     /* Preserve SDA Control */
0647     tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
0648     if (!val)
0649         tmp |= BM_SCLC;
0650     writel(tmp, idev->base + I2C_BUS_MONITOR);
0651 }
0652
0653 static int axxia_i2c_get_sda(struct i2c_adapter *adap)
0654 {
0655     struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
0656
0657     return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
0658 }
0659
0660 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
0661     .recover_bus = i2c_generic_scl_recovery,
0662     .get_scl = axxia_i2c_get_scl,
0663     .set_scl = axxia_i2c_set_scl,
0664     .get_sda = axxia_i2c_get_sda,
0665 };
0666
0667 static u32 axxia_i2c_func(struct i2c_adapter *adap)
0668 {
0669     u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
0670             I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
0671     return caps;
0672 }
0673
0674 static int axxia_i2c_reg_slave(struct i2c_client *slave)
0675 {
0676     struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
0677     u32 slv_int_mask = SLV_STATUS_RFH;
0678     u32 dec_ctl;
0679
0680     if (idev->slave)
0681         return -EBUSY;
0682
0683     idev->slave = slave;
0684
0685     /* Enable slave mode as well */
0686     writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
0687     writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
0688
0689     /* Set slave address */
0690     dec_ctl = SLV_ADDR_DEC_SA1E;
0691     if (slave->flags & I2C_CLIENT_TEN)
0692         dec_ctl |= SLV_ADDR_DEC_SA1M;
0693
0694     writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
0695     writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
0696     writel(slave->addr, idev->base + SLV_ADDR_1);
0697
0698     /* Enable interrupts */
0699     slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1;
0700     slv_int_mask |= SLV_STATUS_SRC1;
0701     writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
0702
0703     return 0;
0704 }
0705
0706 static int axxia_i2c_unreg_slave(struct i2c_client *slave)
0707 {
0708     struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
0709
0710     /* Disable slave mode */
0711     writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
0712     writel(INT_MST, idev->base + INTERRUPT_ENABLE);
0713
0714     synchronize_irq(idev->irq);
0715
0716     idev->slave = NULL;
0717
0718     return 0;
0719 }
0720
0721 static const struct i2c_algorithm axxia_i2c_algo = {
0722     .master_xfer = axxia_i2c_xfer,
0723     .functionality = axxia_i2c_func,
0724     .reg_slave = axxia_i2c_reg_slave,
0725     .unreg_slave = axxia_i2c_unreg_slave,
0726 };
0727
0728 static const struct i2c_adapter_quirks axxia_i2c_quirks = {
0729     .max_read_len = 255,
0730     .max_write_len = 255,
0731 };
0732
0733 static int axxia_i2c_probe(struct platform_device *pdev)
0734 {
0735     struct device_node *np = pdev->dev.of_node;
0736     struct axxia_i2c_dev *idev = NULL;
0737     void __iomem *base;
0738     int ret = 0;
0739
0740     idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
0741     if (!idev)
0742         return -ENOMEM;
0743
0744     base = devm_platform_ioremap_resource(pdev, 0);
0745     if (IS_ERR(base))
0746         return PTR_ERR(base);
0747
0748     idev->irq = platform_get_irq(pdev, 0);
0749     if (idev->irq < 0)
0750         return idev->irq;
0751
0752     idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
0753     if (IS_ERR(idev->i2c_clk)) {
0754         dev_err(&pdev->dev, "missing clock\n");
0755         return PTR_ERR(idev->i2c_clk);
0756     }
0757
0758     idev->base = base;
0759     idev->dev = &pdev->dev;
0760     init_completion(&idev->msg_complete);
0761
0762     of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
0763     if (idev->bus_clk_rate == 0)
0764         idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;    /* default clock rate */
0765
0766     ret = clk_prepare_enable(idev->i2c_clk);
0767     if (ret) {
0768         dev_err(&pdev->dev, "failed to enable clock\n");
0769         return ret;
0770     }
0771
0772     ret = axxia_i2c_init(idev);
0773     if (ret) {
0774         dev_err(&pdev->dev, "failed to initialize\n");
0775         goto error_disable_clk;
0776     }
0777
0778     ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
0779                    pdev->name, idev);
0780     if (ret) {
0781         dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
0782         goto error_disable_clk;
0783     }
0784
0785     i2c_set_adapdata(&idev->adapter, idev);
0786     strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
0787     idev->adapter.owner = THIS_MODULE;
0788     idev->adapter.algo = &axxia_i2c_algo;
0789     idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
0790     idev->adapter.quirks = &axxia_i2c_quirks;
0791     idev->adapter.dev.parent = &pdev->dev;
0792     idev->adapter.dev.of_node = pdev->dev.of_node;
0793
0794     platform_set_drvdata(pdev, idev);
0795
0796     ret = i2c_add_adapter(&idev->adapter);
0797     if (ret)
0798         goto error_disable_clk;
0799
0800     return 0;
0801
0802 error_disable_clk:
0803     clk_disable_unprepare(idev->i2c_clk);
0804     return ret;
0805 }
0806
0807 static int axxia_i2c_remove(struct platform_device *pdev)
0808 {
0809     struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
0810
0811     clk_disable_unprepare(idev->i2c_clk);
0812     i2c_del_adapter(&idev->adapter);
0813
0814     return 0;
0815 }
0816
0817 /* Match table for of_platform binding */
0818 static const struct of_device_id axxia_i2c_of_match[] = {
0819     { .compatible = "lsi,api2c", },
0820     {},
0821 };
0822
0823 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
0824
0825 static struct platform_driver axxia_i2c_driver = {
0826     .probe = axxia_i2c_probe,
0827     .remove = axxia_i2c_remove,
0828     .driver = {
0829         .name = "axxia-i2c",
0830         .of_match_table = axxia_i2c_of_match,
0831     },
0832 };
0833
0834 module_platform_driver(axxia_i2c_driver);
0835
0836 MODULE_DESCRIPTION("Axxia I2C Bus driver");
0837 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
0838 MODULE_LICENSE("GPL v2");