i2c/busses/i2c-at91.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
0004  *
0005  *  Copyright (C) 2011 Weinmann Medical GmbH
0006  *  Author: Nikolaus Voss <n.voss@weinmann.de>
0007  *
0008  *  Evolved from original work by:
0009  *  Copyright (C) 2004 Rick Bronson
0010  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
0011  *
0012  *  Borrowed heavily from original work by:
0013  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
0014  */
0015
0016 #include <linux/clk.h>
0017 #include <linux/completion.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/dmaengine.h>
0020 #include <linux/i2c.h>
0021 #include <linux/platform_device.h>
0022
0023 #define AT91_I2C_TIMEOUT    msecs_to_jiffies(100)   /* transfer timeout */
0024 #define AT91_I2C_DMA_THRESHOLD  8           /* enable DMA if transfer size is bigger than this threshold */
0025 #define AUTOSUSPEND_TIMEOUT     2000
0026 #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE  256
0027
0028 /* AT91 TWI register definitions */
0029 #define AT91_TWI_CR     0x0000  /* Control Register */
0030 #define AT91_TWI_START      BIT(0)  /* Send a Start Condition */
0031 #define AT91_TWI_STOP       BIT(1)  /* Send a Stop Condition */
0032 #define AT91_TWI_MSEN       BIT(2)  /* Master Transfer Enable */
0033 #define AT91_TWI_MSDIS      BIT(3)  /* Master Transfer Disable */
0034 #define AT91_TWI_SVEN       BIT(4)  /* Slave Transfer Enable */
0035 #define AT91_TWI_SVDIS      BIT(5)  /* Slave Transfer Disable */
0036 #define AT91_TWI_QUICK      BIT(6)  /* SMBus quick command */
0037 #define AT91_TWI_SWRST      BIT(7)  /* Software Reset */
0038 #define AT91_TWI_CLEAR      BIT(15) /* Bus clear command */
0039 #define AT91_TWI_ACMEN      BIT(16) /* Alternative Command Mode Enable */
0040 #define AT91_TWI_ACMDIS     BIT(17) /* Alternative Command Mode Disable */
0041 #define AT91_TWI_THRCLR     BIT(24) /* Transmit Holding Register Clear */
0042 #define AT91_TWI_RHRCLR     BIT(25) /* Receive Holding Register Clear */
0043 #define AT91_TWI_LOCKCLR    BIT(26) /* Lock Clear */
0044 #define AT91_TWI_FIFOEN     BIT(28) /* FIFO Enable */
0045 #define AT91_TWI_FIFODIS    BIT(29) /* FIFO Disable */
0046
0047 #define AT91_TWI_MMR        0x0004  /* Master Mode Register */
0048 #define AT91_TWI_IADRSZ_1   0x0100  /* Internal Device Address Size */
0049 #define AT91_TWI_MREAD      BIT(12) /* Master Read Direction */
0050
0051 #define AT91_TWI_SMR        0x0008  /* Slave Mode Register */
0052 #define AT91_TWI_SMR_SADR_MAX   0x007f
0053 #define AT91_TWI_SMR_SADR(x)    (((x) & AT91_TWI_SMR_SADR_MAX) << 16)
0054
0055 #define AT91_TWI_IADR       0x000c  /* Internal Address Register */
0056
0057 #define AT91_TWI_CWGR       0x0010  /* Clock Waveform Generator Reg */
0058 #define AT91_TWI_CWGR_HOLD_MAX  0x1f
0059 #define AT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
0060
0061 #define AT91_TWI_SR     0x0020  /* Status Register */
0062 #define AT91_TWI_TXCOMP     BIT(0)  /* Transmission Complete */
0063 #define AT91_TWI_RXRDY      BIT(1)  /* Receive Holding Register Ready */
0064 #define AT91_TWI_TXRDY      BIT(2)  /* Transmit Holding Register Ready */
0065 #define AT91_TWI_SVREAD     BIT(3)  /* Slave Read */
0066 #define AT91_TWI_SVACC      BIT(4)  /* Slave Access */
0067 #define AT91_TWI_OVRE       BIT(6)  /* Overrun Error */
0068 #define AT91_TWI_UNRE       BIT(7)  /* Underrun Error */
0069 #define AT91_TWI_NACK       BIT(8)  /* Not Acknowledged */
0070 #define AT91_TWI_EOSACC     BIT(11) /* End Of Slave Access */
0071 #define AT91_TWI_LOCK       BIT(23) /* TWI Lock due to Frame Errors */
0072 #define AT91_TWI_SCL        BIT(24) /* TWI SCL status */
0073 #define AT91_TWI_SDA        BIT(25) /* TWI SDA status */
0074
0075 #define AT91_TWI_INT_MASK \
0076     (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
0077     | AT91_TWI_SVACC | AT91_TWI_EOSACC)
0078
0079 #define AT91_TWI_IER        0x0024  /* Interrupt Enable Register */
0080 #define AT91_TWI_IDR        0x0028  /* Interrupt Disable Register */
0081 #define AT91_TWI_IMR        0x002c  /* Interrupt Mask Register */
0082 #define AT91_TWI_RHR        0x0030  /* Receive Holding Register */
0083 #define AT91_TWI_THR        0x0034  /* Transmit Holding Register */
0084
0085 #define AT91_TWI_ACR        0x0040  /* Alternative Command Register */
0086 #define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0)
0087 #define AT91_TWI_ACR_DATAL(len) ((len) & AT91_TWI_ACR_DATAL_MASK)
0088 #define AT91_TWI_ACR_DIR    BIT(8)
0089
0090 #define AT91_TWI_FILTR      0x0044
0091 #define AT91_TWI_FILTR_FILT BIT(0)
0092 #define AT91_TWI_FILTR_PADFEN   BIT(1)
0093 #define AT91_TWI_FILTR_THRES(v)     ((v) << 8)
0094 #define AT91_TWI_FILTR_THRES_MAX    7
0095 #define AT91_TWI_FILTR_THRES_MASK   GENMASK(10, 8)
0096
0097 #define AT91_TWI_FMR        0x0050  /* FIFO Mode Register */
0098 #define AT91_TWI_FMR_TXRDYM(mode)   (((mode) & 0x3) << 0)
0099 #define AT91_TWI_FMR_TXRDYM_MASK    (0x3 << 0)
0100 #define AT91_TWI_FMR_RXRDYM(mode)   (((mode) & 0x3) << 4)
0101 #define AT91_TWI_FMR_RXRDYM_MASK    (0x3 << 4)
0102 #define AT91_TWI_ONE_DATA   0x0
0103 #define AT91_TWI_TWO_DATA   0x1
0104 #define AT91_TWI_FOUR_DATA  0x2
0105
0106 #define AT91_TWI_FLR        0x0054  /* FIFO Level Register */
0107
0108 #define AT91_TWI_FSR        0x0060  /* FIFO Status Register */
0109 #define AT91_TWI_FIER       0x0064  /* FIFO Interrupt Enable Register */
0110 #define AT91_TWI_FIDR       0x0068  /* FIFO Interrupt Disable Register */
0111 #define AT91_TWI_FIMR       0x006c  /* FIFO Interrupt Mask Register */
0112
0113 #define AT91_TWI_VER        0x00fc  /* Version Register */
0114
0115 struct at91_twi_pdata {
0116     unsigned clk_max_div;
0117     unsigned clk_offset;
0118     bool has_unre_flag;
0119     bool has_alt_cmd;
0120     bool has_hold_field;
0121     bool has_dig_filtr;
0122     bool has_adv_dig_filtr;
0123     bool has_ana_filtr;
0124     bool has_clear_cmd;
0125 };
0126
0127 struct at91_twi_dma {
0128     struct dma_chan *chan_rx;
0129     struct dma_chan *chan_tx;
0130     struct scatterlist sg[2];
0131     struct dma_async_tx_descriptor *data_desc;
0132     enum dma_data_direction direction;
0133     bool buf_mapped;
0134     bool xfer_in_progress;
0135 };
0136
0137 struct at91_twi_dev {
0138     struct device *dev;
0139     void __iomem *base;
0140     struct completion cmd_complete;
0141     struct clk *clk;
0142     u8 *buf;
0143     size_t buf_len;
0144     struct i2c_msg *msg;
0145     int irq;
0146     unsigned imr;
0147     unsigned transfer_status;
0148     struct i2c_adapter adapter;
0149     unsigned twi_cwgr_reg;
0150     struct at91_twi_pdata *pdata;
0151     bool use_dma;
0152     bool use_alt_cmd;
0153     bool recv_len_abort;
0154     u32 fifo_size;
0155     struct at91_twi_dma dma;
0156     bool slave_detected;
0157     struct i2c_bus_recovery_info rinfo;
0158 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
0159     unsigned smr;
0160     struct i2c_client *slave;
0161 #endif
0162     bool enable_dig_filt;
0163     bool enable_ana_filt;
0164     u32 filter_width;
0165 };
0166
0167 unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
0168 void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
0169 void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
0170 void at91_twi_irq_save(struct at91_twi_dev *dev);
0171 void at91_twi_irq_restore(struct at91_twi_dev *dev);
0172 void at91_init_twi_bus(struct at91_twi_dev *dev);
0173
0174 void at91_init_twi_bus_master(struct at91_twi_dev *dev);
0175 int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
0176               struct at91_twi_dev *dev);
0177
0178 #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
0179 void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
0180 int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
0181              struct at91_twi_dev *dev);
0182
0183 #else
0184 static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
0185 static inline int at91_twi_probe_slave(struct platform_device *pdev,
0186                        u32 phy_addr, struct at91_twi_dev *dev)
0187 {
0188     return -EINVAL;
0189 }
0190
0191 #endif