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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Aspeed 24XX/25XX I2C Controller.
0004  *
0005  *  Copyright (C) 2012-2017 ASPEED Technology Inc.
0006  *  Copyright 2017 IBM Corporation
0007  *  Copyright 2017 Google, Inc.
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/err.h>
0013 #include <linux/errno.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/irq.h>
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_irq.h>
0023 #include <linux/of_platform.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/reset.h>
0026 #include <linux/slab.h>
0027 
0028 /* I2C Register */
0029 #define ASPEED_I2C_FUN_CTRL_REG             0x00
0030 #define ASPEED_I2C_AC_TIMING_REG1           0x04
0031 #define ASPEED_I2C_AC_TIMING_REG2           0x08
0032 #define ASPEED_I2C_INTR_CTRL_REG            0x0c
0033 #define ASPEED_I2C_INTR_STS_REG             0x10
0034 #define ASPEED_I2C_CMD_REG              0x14
0035 #define ASPEED_I2C_DEV_ADDR_REG             0x18
0036 #define ASPEED_I2C_BYTE_BUF_REG             0x20
0037 
0038 /* Global Register Definition */
0039 /* 0x00 : I2C Interrupt Status Register  */
0040 /* 0x08 : I2C Interrupt Target Assignment  */
0041 
0042 /* Device Register Definition */
0043 /* 0x00 : I2CD Function Control Register  */
0044 #define ASPEED_I2CD_MULTI_MASTER_DIS            BIT(15)
0045 #define ASPEED_I2CD_SDA_DRIVE_1T_EN         BIT(8)
0046 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN           BIT(7)
0047 #define ASPEED_I2CD_M_HIGH_SPEED_EN         BIT(6)
0048 #define ASPEED_I2CD_SLAVE_EN                BIT(1)
0049 #define ASPEED_I2CD_MASTER_EN               BIT(0)
0050 
0051 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
0052 #define ASPEED_I2CD_TIME_TBUF_MASK          GENMASK(31, 28)
0053 #define ASPEED_I2CD_TIME_THDSTA_MASK            GENMASK(27, 24)
0054 #define ASPEED_I2CD_TIME_TACST_MASK         GENMASK(23, 20)
0055 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT         16
0056 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK          GENMASK(19, 16)
0057 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT          12
0058 #define ASPEED_I2CD_TIME_SCL_LOW_MASK           GENMASK(15, 12)
0059 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK      GENMASK(3, 0)
0060 #define ASPEED_I2CD_TIME_SCL_REG_MAX            GENMASK(3, 0)
0061 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
0062 #define ASPEED_NO_TIMEOUT_CTRL              0
0063 
0064 /* 0x0c : I2CD Interrupt Control Register &
0065  * 0x10 : I2CD Interrupt Status Register
0066  *
0067  * These share bit definitions, so use the same values for the enable &
0068  * status bits.
0069  */
0070 #define ASPEED_I2CD_INTR_RECV_MASK          0xf000ffff
0071 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT         BIT(14)
0072 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE       BIT(13)
0073 #define ASPEED_I2CD_INTR_SLAVE_MATCH            BIT(7)
0074 #define ASPEED_I2CD_INTR_SCL_TIMEOUT            BIT(6)
0075 #define ASPEED_I2CD_INTR_ABNORMAL           BIT(5)
0076 #define ASPEED_I2CD_INTR_NORMAL_STOP            BIT(4)
0077 #define ASPEED_I2CD_INTR_ARBIT_LOSS         BIT(3)
0078 #define ASPEED_I2CD_INTR_RX_DONE            BIT(2)
0079 #define ASPEED_I2CD_INTR_TX_NAK             BIT(1)
0080 #define ASPEED_I2CD_INTR_TX_ACK             BIT(0)
0081 #define ASPEED_I2CD_INTR_MASTER_ERRORS                         \
0082         (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |                 \
0083          ASPEED_I2CD_INTR_SCL_TIMEOUT |                    \
0084          ASPEED_I2CD_INTR_ABNORMAL |                       \
0085          ASPEED_I2CD_INTR_ARBIT_LOSS)
0086 #define ASPEED_I2CD_INTR_ALL                               \
0087         (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |                 \
0088          ASPEED_I2CD_INTR_BUS_RECOVER_DONE |                   \
0089          ASPEED_I2CD_INTR_SCL_TIMEOUT |                    \
0090          ASPEED_I2CD_INTR_ABNORMAL |                       \
0091          ASPEED_I2CD_INTR_NORMAL_STOP |                    \
0092          ASPEED_I2CD_INTR_ARBIT_LOSS |                     \
0093          ASPEED_I2CD_INTR_RX_DONE |                    \
0094          ASPEED_I2CD_INTR_TX_NAK |                     \
0095          ASPEED_I2CD_INTR_TX_ACK)
0096 
0097 /* 0x14 : I2CD Command/Status Register   */
0098 #define ASPEED_I2CD_SCL_LINE_STS            BIT(18)
0099 #define ASPEED_I2CD_SDA_LINE_STS            BIT(17)
0100 #define ASPEED_I2CD_BUS_BUSY_STS            BIT(16)
0101 #define ASPEED_I2CD_BUS_RECOVER_CMD         BIT(11)
0102 
0103 /* Command Bit */
0104 #define ASPEED_I2CD_M_STOP_CMD              BIT(5)
0105 #define ASPEED_I2CD_M_S_RX_CMD_LAST         BIT(4)
0106 #define ASPEED_I2CD_M_RX_CMD                BIT(3)
0107 #define ASPEED_I2CD_S_TX_CMD                BIT(2)
0108 #define ASPEED_I2CD_M_TX_CMD                BIT(1)
0109 #define ASPEED_I2CD_M_START_CMD             BIT(0)
0110 #define ASPEED_I2CD_MASTER_CMDS_MASK                           \
0111         (ASPEED_I2CD_M_STOP_CMD |                      \
0112          ASPEED_I2CD_M_S_RX_CMD_LAST |                     \
0113          ASPEED_I2CD_M_RX_CMD |                        \
0114          ASPEED_I2CD_M_TX_CMD |                        \
0115          ASPEED_I2CD_M_START_CMD)
0116 
0117 /* 0x18 : I2CD Slave Device Address Register   */
0118 #define ASPEED_I2CD_DEV_ADDR_MASK           GENMASK(6, 0)
0119 
0120 enum aspeed_i2c_master_state {
0121     ASPEED_I2C_MASTER_INACTIVE,
0122     ASPEED_I2C_MASTER_PENDING,
0123     ASPEED_I2C_MASTER_START,
0124     ASPEED_I2C_MASTER_TX_FIRST,
0125     ASPEED_I2C_MASTER_TX,
0126     ASPEED_I2C_MASTER_RX_FIRST,
0127     ASPEED_I2C_MASTER_RX,
0128     ASPEED_I2C_MASTER_STOP,
0129 };
0130 
0131 enum aspeed_i2c_slave_state {
0132     ASPEED_I2C_SLAVE_INACTIVE,
0133     ASPEED_I2C_SLAVE_START,
0134     ASPEED_I2C_SLAVE_READ_REQUESTED,
0135     ASPEED_I2C_SLAVE_READ_PROCESSED,
0136     ASPEED_I2C_SLAVE_WRITE_REQUESTED,
0137     ASPEED_I2C_SLAVE_WRITE_RECEIVED,
0138     ASPEED_I2C_SLAVE_STOP,
0139 };
0140 
0141 struct aspeed_i2c_bus {
0142     struct i2c_adapter      adap;
0143     struct device           *dev;
0144     void __iomem            *base;
0145     struct reset_control        *rst;
0146     /* Synchronizes I/O mem access to base. */
0147     spinlock_t          lock;
0148     struct completion       cmd_complete;
0149     u32             (*get_clk_reg_val)(struct device *dev,
0150                                u32 divisor);
0151     unsigned long           parent_clk_frequency;
0152     u32             bus_frequency;
0153     /* Transaction state. */
0154     enum aspeed_i2c_master_state    master_state;
0155     struct i2c_msg          *msgs;
0156     size_t              buf_index;
0157     size_t              msgs_index;
0158     size_t              msgs_count;
0159     bool                send_stop;
0160     int             cmd_err;
0161     /* Protected only by i2c_lock_bus */
0162     int             master_xfer_result;
0163     /* Multi-master */
0164     bool                multi_master;
0165 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0166     struct i2c_client       *slave;
0167     enum aspeed_i2c_slave_state slave_state;
0168 #endif /* CONFIG_I2C_SLAVE */
0169 };
0170 
0171 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
0172 
0173 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
0174 {
0175     unsigned long time_left, flags;
0176     int ret = 0;
0177     u32 command;
0178 
0179     spin_lock_irqsave(&bus->lock, flags);
0180     command = readl(bus->base + ASPEED_I2C_CMD_REG);
0181 
0182     if (command & ASPEED_I2CD_SDA_LINE_STS) {
0183         /* Bus is idle: no recovery needed. */
0184         if (command & ASPEED_I2CD_SCL_LINE_STS)
0185             goto out;
0186         dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
0187             command);
0188 
0189         reinit_completion(&bus->cmd_complete);
0190         writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
0191         spin_unlock_irqrestore(&bus->lock, flags);
0192 
0193         time_left = wait_for_completion_timeout(
0194                 &bus->cmd_complete, bus->adap.timeout);
0195 
0196         spin_lock_irqsave(&bus->lock, flags);
0197         if (time_left == 0)
0198             goto reset_out;
0199         else if (bus->cmd_err)
0200             goto reset_out;
0201         /* Recovery failed. */
0202         else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
0203                ASPEED_I2CD_SCL_LINE_STS))
0204             goto reset_out;
0205     /* Bus error. */
0206     } else {
0207         dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
0208             command);
0209 
0210         reinit_completion(&bus->cmd_complete);
0211         /* Writes 1 to 8 SCL clock cycles until SDA is released. */
0212         writel(ASPEED_I2CD_BUS_RECOVER_CMD,
0213                bus->base + ASPEED_I2C_CMD_REG);
0214         spin_unlock_irqrestore(&bus->lock, flags);
0215 
0216         time_left = wait_for_completion_timeout(
0217                 &bus->cmd_complete, bus->adap.timeout);
0218 
0219         spin_lock_irqsave(&bus->lock, flags);
0220         if (time_left == 0)
0221             goto reset_out;
0222         else if (bus->cmd_err)
0223             goto reset_out;
0224         /* Recovery failed. */
0225         else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
0226                ASPEED_I2CD_SDA_LINE_STS))
0227             goto reset_out;
0228     }
0229 
0230 out:
0231     spin_unlock_irqrestore(&bus->lock, flags);
0232 
0233     return ret;
0234 
0235 reset_out:
0236     spin_unlock_irqrestore(&bus->lock, flags);
0237 
0238     return aspeed_i2c_reset(bus);
0239 }
0240 
0241 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0242 static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
0243 {
0244     u32 command, irq_handled = 0;
0245     struct i2c_client *slave = bus->slave;
0246     u8 value;
0247 
0248     if (!slave)
0249         return 0;
0250 
0251     command = readl(bus->base + ASPEED_I2C_CMD_REG);
0252 
0253     /* Slave was requested, restart state machine. */
0254     if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
0255         irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
0256         bus->slave_state = ASPEED_I2C_SLAVE_START;
0257     }
0258 
0259     /* Slave is not currently active, irq was for someone else. */
0260     if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
0261         return irq_handled;
0262 
0263     dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
0264         irq_status, command);
0265 
0266     /* Slave was sent something. */
0267     if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
0268         value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
0269         /* Handle address frame. */
0270         if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
0271             if (value & 0x1)
0272                 bus->slave_state =
0273                         ASPEED_I2C_SLAVE_READ_REQUESTED;
0274             else
0275                 bus->slave_state =
0276                         ASPEED_I2C_SLAVE_WRITE_REQUESTED;
0277         }
0278         irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
0279     }
0280 
0281     /* Slave was asked to stop. */
0282     if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
0283         irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
0284         bus->slave_state = ASPEED_I2C_SLAVE_STOP;
0285     }
0286     if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
0287         bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
0288         irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
0289         bus->slave_state = ASPEED_I2C_SLAVE_STOP;
0290     }
0291 
0292     switch (bus->slave_state) {
0293     case ASPEED_I2C_SLAVE_READ_REQUESTED:
0294         if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
0295             dev_err(bus->dev, "Unexpected ACK on read request.\n");
0296         bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
0297         i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
0298         writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
0299         writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
0300         break;
0301     case ASPEED_I2C_SLAVE_READ_PROCESSED:
0302         if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
0303             dev_err(bus->dev,
0304                 "Expected ACK after processed read.\n");
0305             break;
0306         }
0307         irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
0308         i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
0309         writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
0310         writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
0311         break;
0312     case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
0313         bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
0314         i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
0315         break;
0316     case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
0317         i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
0318         break;
0319     case ASPEED_I2C_SLAVE_STOP:
0320         i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
0321         bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
0322         break;
0323     case ASPEED_I2C_SLAVE_START:
0324         /* Slave was just started. Waiting for the next event. */;
0325         break;
0326     default:
0327         dev_err(bus->dev, "unknown slave_state: %d\n",
0328             bus->slave_state);
0329         bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
0330         break;
0331     }
0332 
0333     return irq_handled;
0334 }
0335 #endif /* CONFIG_I2C_SLAVE */
0336 
0337 /* precondition: bus.lock has been acquired. */
0338 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
0339 {
0340     u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
0341     struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
0342     u8 slave_addr = i2c_8bit_addr_from_msg(msg);
0343 
0344 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0345     /*
0346      * If it's requested in the middle of a slave session, set the master
0347      * state to 'pending' then H/W will continue handling this master
0348      * command when the bus comes back to the idle state.
0349      */
0350     if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {
0351         bus->master_state = ASPEED_I2C_MASTER_PENDING;
0352         return;
0353     }
0354 #endif /* CONFIG_I2C_SLAVE */
0355 
0356     bus->master_state = ASPEED_I2C_MASTER_START;
0357     bus->buf_index = 0;
0358 
0359     if (msg->flags & I2C_M_RD) {
0360         command |= ASPEED_I2CD_M_RX_CMD;
0361         /* Need to let the hardware know to NACK after RX. */
0362         if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
0363             command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
0364     }
0365 
0366     writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
0367     writel(command, bus->base + ASPEED_I2C_CMD_REG);
0368 }
0369 
0370 /* precondition: bus.lock has been acquired. */
0371 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
0372 {
0373     bus->master_state = ASPEED_I2C_MASTER_STOP;
0374     writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
0375 }
0376 
0377 /* precondition: bus.lock has been acquired. */
0378 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
0379 {
0380     if (bus->msgs_index + 1 < bus->msgs_count) {
0381         bus->msgs_index++;
0382         aspeed_i2c_do_start(bus);
0383     } else {
0384         aspeed_i2c_do_stop(bus);
0385     }
0386 }
0387 
0388 static int aspeed_i2c_is_irq_error(u32 irq_status)
0389 {
0390     if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
0391         return -EAGAIN;
0392     if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
0393               ASPEED_I2CD_INTR_SCL_TIMEOUT))
0394         return -EBUSY;
0395     if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
0396         return -EPROTO;
0397 
0398     return 0;
0399 }
0400 
0401 static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
0402 {
0403     u32 irq_handled = 0, command = 0;
0404     struct i2c_msg *msg;
0405     u8 recv_byte;
0406     int ret;
0407 
0408     if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
0409         bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0410         irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
0411         goto out_complete;
0412     }
0413 
0414     /*
0415      * We encountered an interrupt that reports an error: the hardware
0416      * should clear the command queue effectively taking us back to the
0417      * INACTIVE state.
0418      */
0419     ret = aspeed_i2c_is_irq_error(irq_status);
0420     if (ret) {
0421         dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
0422             irq_status);
0423         irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
0424         if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
0425             bus->cmd_err = ret;
0426             bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0427             goto out_complete;
0428         }
0429     }
0430 
0431     /* Master is not currently active, irq was for someone else. */
0432     if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
0433         bus->master_state == ASPEED_I2C_MASTER_PENDING)
0434         goto out_no_complete;
0435 
0436     /* We are in an invalid state; reset bus to a known state. */
0437     if (!bus->msgs) {
0438         dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
0439             irq_status);
0440         bus->cmd_err = -EIO;
0441         if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
0442             bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
0443             aspeed_i2c_do_stop(bus);
0444         goto out_no_complete;
0445     }
0446     msg = &bus->msgs[bus->msgs_index];
0447 
0448     /*
0449      * START is a special case because we still have to handle a subsequent
0450      * TX or RX immediately after we handle it, so we handle it here and
0451      * then update the state and handle the new state below.
0452      */
0453     if (bus->master_state == ASPEED_I2C_MASTER_START) {
0454 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0455         /*
0456          * If a peer master starts a xfer immediately after it queues a
0457          * master command, clear the queued master command and change
0458          * its state to 'pending'. To simplify handling of pending
0459          * cases, it uses S/W solution instead of H/W command queue
0460          * handling.
0461          */
0462         if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
0463             writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
0464                 ~ASPEED_I2CD_MASTER_CMDS_MASK,
0465                    bus->base + ASPEED_I2C_CMD_REG);
0466             bus->master_state = ASPEED_I2C_MASTER_PENDING;
0467             dev_dbg(bus->dev,
0468                 "master goes pending due to a slave start\n");
0469             goto out_no_complete;
0470         }
0471 #endif /* CONFIG_I2C_SLAVE */
0472         if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
0473             if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
0474                 bus->cmd_err = -ENXIO;
0475                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0476                 goto out_complete;
0477             }
0478             pr_devel("no slave present at %02x\n", msg->addr);
0479             irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
0480             bus->cmd_err = -ENXIO;
0481             aspeed_i2c_do_stop(bus);
0482             goto out_no_complete;
0483         }
0484         irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
0485         if (msg->len == 0) { /* SMBUS_QUICK */
0486             aspeed_i2c_do_stop(bus);
0487             goto out_no_complete;
0488         }
0489         if (msg->flags & I2C_M_RD)
0490             bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
0491         else
0492             bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
0493     }
0494 
0495     switch (bus->master_state) {
0496     case ASPEED_I2C_MASTER_TX:
0497         if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
0498             dev_dbg(bus->dev, "slave NACKed TX\n");
0499             irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
0500             goto error_and_stop;
0501         } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
0502             dev_err(bus->dev, "slave failed to ACK TX\n");
0503             goto error_and_stop;
0504         }
0505         irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
0506         fallthrough;
0507     case ASPEED_I2C_MASTER_TX_FIRST:
0508         if (bus->buf_index < msg->len) {
0509             bus->master_state = ASPEED_I2C_MASTER_TX;
0510             writel(msg->buf[bus->buf_index++],
0511                    bus->base + ASPEED_I2C_BYTE_BUF_REG);
0512             writel(ASPEED_I2CD_M_TX_CMD,
0513                    bus->base + ASPEED_I2C_CMD_REG);
0514         } else {
0515             aspeed_i2c_next_msg_or_stop(bus);
0516         }
0517         goto out_no_complete;
0518     case ASPEED_I2C_MASTER_RX_FIRST:
0519         /* RX may not have completed yet (only address cycle) */
0520         if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
0521             goto out_no_complete;
0522         fallthrough;
0523     case ASPEED_I2C_MASTER_RX:
0524         if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
0525             dev_err(bus->dev, "master failed to RX\n");
0526             goto error_and_stop;
0527         }
0528         irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
0529 
0530         recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
0531         msg->buf[bus->buf_index++] = recv_byte;
0532 
0533         if (msg->flags & I2C_M_RECV_LEN) {
0534             if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
0535                 bus->cmd_err = -EPROTO;
0536                 aspeed_i2c_do_stop(bus);
0537                 goto out_no_complete;
0538             }
0539             msg->len = recv_byte +
0540                     ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
0541             msg->flags &= ~I2C_M_RECV_LEN;
0542         }
0543 
0544         if (bus->buf_index < msg->len) {
0545             bus->master_state = ASPEED_I2C_MASTER_RX;
0546             command = ASPEED_I2CD_M_RX_CMD;
0547             if (bus->buf_index + 1 == msg->len)
0548                 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
0549             writel(command, bus->base + ASPEED_I2C_CMD_REG);
0550         } else {
0551             aspeed_i2c_next_msg_or_stop(bus);
0552         }
0553         goto out_no_complete;
0554     case ASPEED_I2C_MASTER_STOP:
0555         if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
0556             dev_err(bus->dev,
0557                 "master failed to STOP. irq_status:0x%x\n",
0558                 irq_status);
0559             bus->cmd_err = -EIO;
0560             /* Do not STOP as we have already tried. */
0561         } else {
0562             irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
0563         }
0564 
0565         bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0566         goto out_complete;
0567     case ASPEED_I2C_MASTER_INACTIVE:
0568         dev_err(bus->dev,
0569             "master received interrupt 0x%08x, but is inactive\n",
0570             irq_status);
0571         bus->cmd_err = -EIO;
0572         /* Do not STOP as we should be inactive. */
0573         goto out_complete;
0574     default:
0575         WARN(1, "unknown master state\n");
0576         bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0577         bus->cmd_err = -EINVAL;
0578         goto out_complete;
0579     }
0580 error_and_stop:
0581     bus->cmd_err = -EIO;
0582     aspeed_i2c_do_stop(bus);
0583     goto out_no_complete;
0584 out_complete:
0585     bus->msgs = NULL;
0586     if (bus->cmd_err)
0587         bus->master_xfer_result = bus->cmd_err;
0588     else
0589         bus->master_xfer_result = bus->msgs_index + 1;
0590     complete(&bus->cmd_complete);
0591 out_no_complete:
0592     return irq_handled;
0593 }
0594 
0595 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
0596 {
0597     struct aspeed_i2c_bus *bus = dev_id;
0598     u32 irq_received, irq_remaining, irq_handled;
0599 
0600     spin_lock(&bus->lock);
0601     irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
0602     /* Ack all interrupts except for Rx done */
0603     writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
0604            bus->base + ASPEED_I2C_INTR_STS_REG);
0605     readl(bus->base + ASPEED_I2C_INTR_STS_REG);
0606     irq_received &= ASPEED_I2CD_INTR_RECV_MASK;
0607     irq_remaining = irq_received;
0608 
0609 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0610     /*
0611      * In most cases, interrupt bits will be set one by one, although
0612      * multiple interrupt bits could be set at the same time. It's also
0613      * possible that master interrupt bits could be set along with slave
0614      * interrupt bits. Each case needs to be handled using corresponding
0615      * handlers depending on the current state.
0616      */
0617     if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
0618         bus->master_state != ASPEED_I2C_MASTER_PENDING) {
0619         irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
0620         irq_remaining &= ~irq_handled;
0621         if (irq_remaining)
0622             irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
0623     } else {
0624         irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
0625         irq_remaining &= ~irq_handled;
0626         if (irq_remaining)
0627             irq_handled |= aspeed_i2c_master_irq(bus,
0628                                  irq_remaining);
0629     }
0630 
0631     /*
0632      * Start a pending master command at here if a slave operation is
0633      * completed.
0634      */
0635     if (bus->master_state == ASPEED_I2C_MASTER_PENDING &&
0636         bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
0637         aspeed_i2c_do_start(bus);
0638 #else
0639     irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
0640 #endif /* CONFIG_I2C_SLAVE */
0641 
0642     irq_remaining &= ~irq_handled;
0643     if (irq_remaining)
0644         dev_err(bus->dev,
0645             "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
0646             irq_received, irq_handled);
0647 
0648     /* Ack Rx done */
0649     if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
0650         writel(ASPEED_I2CD_INTR_RX_DONE,
0651                bus->base + ASPEED_I2C_INTR_STS_REG);
0652         readl(bus->base + ASPEED_I2C_INTR_STS_REG);
0653     }
0654     spin_unlock(&bus->lock);
0655     return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
0656 }
0657 
0658 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
0659                   struct i2c_msg *msgs, int num)
0660 {
0661     struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
0662     unsigned long time_left, flags;
0663 
0664     spin_lock_irqsave(&bus->lock, flags);
0665     bus->cmd_err = 0;
0666 
0667     /* If bus is busy in a single master environment, attempt recovery. */
0668     if (!bus->multi_master &&
0669         (readl(bus->base + ASPEED_I2C_CMD_REG) &
0670          ASPEED_I2CD_BUS_BUSY_STS)) {
0671         int ret;
0672 
0673         spin_unlock_irqrestore(&bus->lock, flags);
0674         ret = aspeed_i2c_recover_bus(bus);
0675         if (ret)
0676             return ret;
0677         spin_lock_irqsave(&bus->lock, flags);
0678     }
0679 
0680     bus->cmd_err = 0;
0681     bus->msgs = msgs;
0682     bus->msgs_index = 0;
0683     bus->msgs_count = num;
0684 
0685     reinit_completion(&bus->cmd_complete);
0686     aspeed_i2c_do_start(bus);
0687     spin_unlock_irqrestore(&bus->lock, flags);
0688 
0689     time_left = wait_for_completion_timeout(&bus->cmd_complete,
0690                         bus->adap.timeout);
0691 
0692     if (time_left == 0) {
0693         /*
0694          * If timed out and bus is still busy in a multi master
0695          * environment, attempt recovery at here.
0696          */
0697         if (bus->multi_master &&
0698             (readl(bus->base + ASPEED_I2C_CMD_REG) &
0699              ASPEED_I2CD_BUS_BUSY_STS))
0700             aspeed_i2c_recover_bus(bus);
0701 
0702         /*
0703          * If timed out and the state is still pending, drop the pending
0704          * master command.
0705          */
0706         spin_lock_irqsave(&bus->lock, flags);
0707         if (bus->master_state == ASPEED_I2C_MASTER_PENDING)
0708             bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
0709         spin_unlock_irqrestore(&bus->lock, flags);
0710 
0711         return -ETIMEDOUT;
0712     }
0713 
0714     return bus->master_xfer_result;
0715 }
0716 
0717 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
0718 {
0719     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
0720 }
0721 
0722 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0723 /* precondition: bus.lock has been acquired. */
0724 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
0725 {
0726     u32 addr_reg_val, func_ctrl_reg_val;
0727 
0728     /*
0729      * Set slave addr.  Reserved bits can all safely be written with zeros
0730      * on all of ast2[456]00, so zero everything else to ensure we only
0731      * enable a single slave address (ast2500 has two, ast2600 has three,
0732      * the enable bits for which are also in this register) so that we don't
0733      * end up with additional phantom devices responding on the bus.
0734      */
0735     addr_reg_val = slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
0736     writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
0737 
0738     /* Turn on slave mode. */
0739     func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
0740     func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
0741     writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
0742 }
0743 
0744 static int aspeed_i2c_reg_slave(struct i2c_client *client)
0745 {
0746     struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
0747     unsigned long flags;
0748 
0749     spin_lock_irqsave(&bus->lock, flags);
0750     if (bus->slave) {
0751         spin_unlock_irqrestore(&bus->lock, flags);
0752         return -EINVAL;
0753     }
0754 
0755     __aspeed_i2c_reg_slave(bus, client->addr);
0756 
0757     bus->slave = client;
0758     bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
0759     spin_unlock_irqrestore(&bus->lock, flags);
0760 
0761     return 0;
0762 }
0763 
0764 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
0765 {
0766     struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
0767     u32 func_ctrl_reg_val;
0768     unsigned long flags;
0769 
0770     spin_lock_irqsave(&bus->lock, flags);
0771     if (!bus->slave) {
0772         spin_unlock_irqrestore(&bus->lock, flags);
0773         return -EINVAL;
0774     }
0775 
0776     /* Turn off slave mode. */
0777     func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
0778     func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
0779     writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
0780 
0781     bus->slave = NULL;
0782     spin_unlock_irqrestore(&bus->lock, flags);
0783 
0784     return 0;
0785 }
0786 #endif /* CONFIG_I2C_SLAVE */
0787 
0788 static const struct i2c_algorithm aspeed_i2c_algo = {
0789     .master_xfer    = aspeed_i2c_master_xfer,
0790     .functionality  = aspeed_i2c_functionality,
0791 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0792     .reg_slave  = aspeed_i2c_reg_slave,
0793     .unreg_slave    = aspeed_i2c_unreg_slave,
0794 #endif /* CONFIG_I2C_SLAVE */
0795 };
0796 
0797 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
0798                       u32 clk_high_low_mask,
0799                       u32 divisor)
0800 {
0801     u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
0802 
0803     /*
0804      * SCL_high and SCL_low represent a value 1 greater than what is stored
0805      * since a zero divider is meaningless. Thus, the max value each can
0806      * store is every bit set + 1. Since SCL_high and SCL_low are added
0807      * together (see below), the max value of both is the max value of one
0808      * them times two.
0809      */
0810     clk_high_low_max = (clk_high_low_mask + 1) * 2;
0811 
0812     /*
0813      * The actual clock frequency of SCL is:
0814      *  SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
0815      *       = APB_freq / divisor
0816      * where base_freq is a programmable clock divider; its value is
0817      *  base_freq = 1 << base_clk_divisor
0818      * SCL_high is the number of base_freq clock cycles that SCL stays high
0819      * and SCL_low is the number of base_freq clock cycles that SCL stays
0820      * low for a period of SCL.
0821      * The actual register has a minimum SCL_high and SCL_low minimum of 1;
0822      * thus, they start counting at zero. So
0823      *  SCL_high = clk_high + 1
0824      *  SCL_low  = clk_low + 1
0825      * Thus,
0826      *  SCL_freq = APB_freq /
0827      *      ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
0828      * The documentation recommends clk_high >= clk_high_max / 2 and
0829      * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
0830      * gives us the following solution:
0831      */
0832     base_clk_divisor = divisor > clk_high_low_max ?
0833             ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
0834 
0835     if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
0836         base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
0837         clk_low = clk_high_low_mask;
0838         clk_high = clk_high_low_mask;
0839         dev_err(dev,
0840             "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
0841             divisor, (1 << base_clk_divisor) * clk_high_low_max);
0842     } else {
0843         tmp = (divisor + (1 << base_clk_divisor) - 1)
0844                 >> base_clk_divisor;
0845         clk_low = tmp / 2;
0846         clk_high = tmp - clk_low;
0847 
0848         if (clk_high)
0849             clk_high--;
0850 
0851         if (clk_low)
0852             clk_low--;
0853     }
0854 
0855 
0856     return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
0857         & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
0858             | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
0859                & ASPEED_I2CD_TIME_SCL_LOW_MASK)
0860             | (base_clk_divisor
0861                & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
0862 }
0863 
0864 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
0865 {
0866     /*
0867      * clk_high and clk_low are each 3 bits wide, so each can hold a max
0868      * value of 8 giving a clk_high_low_max of 16.
0869      */
0870     return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
0871 }
0872 
0873 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
0874 {
0875     /*
0876      * clk_high and clk_low are each 4 bits wide, so each can hold a max
0877      * value of 16 giving a clk_high_low_max of 32.
0878      */
0879     return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
0880 }
0881 
0882 /* precondition: bus.lock has been acquired. */
0883 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
0884 {
0885     u32 divisor, clk_reg_val;
0886 
0887     divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
0888     clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
0889     clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
0890             ASPEED_I2CD_TIME_THDSTA_MASK |
0891             ASPEED_I2CD_TIME_TACST_MASK);
0892     clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
0893     writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
0894     writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
0895 
0896     return 0;
0897 }
0898 
0899 /* precondition: bus.lock has been acquired. */
0900 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
0901                  struct platform_device *pdev)
0902 {
0903     u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
0904     int ret;
0905 
0906     /* Disable everything. */
0907     writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
0908 
0909     ret = aspeed_i2c_init_clk(bus);
0910     if (ret < 0)
0911         return ret;
0912 
0913     if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
0914         bus->multi_master = true;
0915     else
0916         fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
0917 
0918     /* Enable Master Mode */
0919     writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
0920            bus->base + ASPEED_I2C_FUN_CTRL_REG);
0921 
0922 #if IS_ENABLED(CONFIG_I2C_SLAVE)
0923     /* If slave has already been registered, re-enable it. */
0924     if (bus->slave)
0925         __aspeed_i2c_reg_slave(bus, bus->slave->addr);
0926 #endif /* CONFIG_I2C_SLAVE */
0927 
0928     /* Set interrupt generation of I2C controller */
0929     writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
0930 
0931     return 0;
0932 }
0933 
0934 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
0935 {
0936     struct platform_device *pdev = to_platform_device(bus->dev);
0937     unsigned long flags;
0938     int ret;
0939 
0940     spin_lock_irqsave(&bus->lock, flags);
0941 
0942     /* Disable and ack all interrupts. */
0943     writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
0944     writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
0945 
0946     ret = aspeed_i2c_init(bus, pdev);
0947 
0948     spin_unlock_irqrestore(&bus->lock, flags);
0949 
0950     return ret;
0951 }
0952 
0953 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
0954     {
0955         .compatible = "aspeed,ast2400-i2c-bus",
0956         .data = aspeed_i2c_24xx_get_clk_reg_val,
0957     },
0958     {
0959         .compatible = "aspeed,ast2500-i2c-bus",
0960         .data = aspeed_i2c_25xx_get_clk_reg_val,
0961     },
0962     {
0963         .compatible = "aspeed,ast2600-i2c-bus",
0964         .data = aspeed_i2c_25xx_get_clk_reg_val,
0965     },
0966     { },
0967 };
0968 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
0969 
0970 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
0971 {
0972     const struct of_device_id *match;
0973     struct aspeed_i2c_bus *bus;
0974     struct clk *parent_clk;
0975     struct resource *res;
0976     int irq, ret;
0977 
0978     bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
0979     if (!bus)
0980         return -ENOMEM;
0981 
0982     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0983     bus->base = devm_ioremap_resource(&pdev->dev, res);
0984     if (IS_ERR(bus->base))
0985         return PTR_ERR(bus->base);
0986 
0987     parent_clk = devm_clk_get(&pdev->dev, NULL);
0988     if (IS_ERR(parent_clk))
0989         return PTR_ERR(parent_clk);
0990     bus->parent_clk_frequency = clk_get_rate(parent_clk);
0991     /* We just need the clock rate, we don't actually use the clk object. */
0992     devm_clk_put(&pdev->dev, parent_clk);
0993 
0994     bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
0995     if (IS_ERR(bus->rst)) {
0996         dev_err(&pdev->dev,
0997             "missing or invalid reset controller device tree entry\n");
0998         return PTR_ERR(bus->rst);
0999     }
1000     reset_control_deassert(bus->rst);
1001 
1002     ret = of_property_read_u32(pdev->dev.of_node,
1003                    "bus-frequency", &bus->bus_frequency);
1004     if (ret < 0) {
1005         dev_err(&pdev->dev,
1006             "Could not read bus-frequency property\n");
1007         bus->bus_frequency = I2C_MAX_STANDARD_MODE_FREQ;
1008     }
1009 
1010     match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
1011     if (!match)
1012         bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
1013     else
1014         bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
1015                 match->data;
1016 
1017     /* Initialize the I2C adapter */
1018     spin_lock_init(&bus->lock);
1019     init_completion(&bus->cmd_complete);
1020     bus->adap.owner = THIS_MODULE;
1021     bus->adap.retries = 0;
1022     bus->adap.algo = &aspeed_i2c_algo;
1023     bus->adap.dev.parent = &pdev->dev;
1024     bus->adap.dev.of_node = pdev->dev.of_node;
1025     strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
1026     i2c_set_adapdata(&bus->adap, bus);
1027 
1028     bus->dev = &pdev->dev;
1029 
1030     /* Clean up any left over interrupt state. */
1031     writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
1032     writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
1033     /*
1034      * bus.lock does not need to be held because the interrupt handler has
1035      * not been enabled yet.
1036      */
1037     ret = aspeed_i2c_init(bus, pdev);
1038     if (ret < 0)
1039         return ret;
1040 
1041     irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1042     ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
1043                    0, dev_name(&pdev->dev), bus);
1044     if (ret < 0)
1045         return ret;
1046 
1047     ret = i2c_add_adapter(&bus->adap);
1048     if (ret < 0)
1049         return ret;
1050 
1051     platform_set_drvdata(pdev, bus);
1052 
1053     dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
1054          bus->adap.nr, irq);
1055 
1056     return 0;
1057 }
1058 
1059 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
1060 {
1061     struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
1062     unsigned long flags;
1063 
1064     spin_lock_irqsave(&bus->lock, flags);
1065 
1066     /* Disable everything. */
1067     writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
1068     writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
1069 
1070     spin_unlock_irqrestore(&bus->lock, flags);
1071 
1072     reset_control_assert(bus->rst);
1073 
1074     i2c_del_adapter(&bus->adap);
1075 
1076     return 0;
1077 }
1078 
1079 static struct platform_driver aspeed_i2c_bus_driver = {
1080     .probe      = aspeed_i2c_probe_bus,
1081     .remove     = aspeed_i2c_remove_bus,
1082     .driver     = {
1083         .name       = "aspeed-i2c-bus",
1084         .of_match_table = aspeed_i2c_bus_of_table,
1085     },
1086 };
1087 module_platform_driver(aspeed_i2c_bus_driver);
1088 
1089 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
1090 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
1091 MODULE_LICENSE("GPL v2");
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