i2c/busses/i2c-amd8111.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SMBus 2.0 driver for AMD-8111 IO-Hub.
0004  *
0005  * Copyright (c) 2002 Vojtech Pavlik
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/pci.h>
0010 #include <linux/kernel.h>
0011 #include <linux/stddef.h>
0012 #include <linux/ioport.h>
0013 #include <linux/i2c.h>
0014 #include <linux/delay.h>
0015 #include <linux/acpi.h>
0016 #include <linux/slab.h>
0017 #include <linux/io.h>
0018
0019 MODULE_LICENSE("GPL");
0020 MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
0021 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
0022
0023 struct amd_smbus {
0024     struct pci_dev *dev;
0025     struct i2c_adapter adapter;
0026     int base;
0027     int size;
0028 };
0029
0030 static struct pci_driver amd8111_driver;
0031
0032 /*
0033  * AMD PCI control registers definitions.
0034  */
0035
0036 #define AMD_PCI_MISC    0x48
0037
0038 #define AMD_PCI_MISC_SCI    0x04    /* deliver SCI */
0039 #define AMD_PCI_MISC_INT    0x02    /* deliver PCI IRQ */
0040 #define AMD_PCI_MISC_SPEEDUP    0x01    /* 16x clock speedup */
0041
0042 /*
0043  * ACPI 2.0 chapter 13 PCI interface definitions.
0044  */
0045
0046 #define AMD_EC_DATA 0x00    /* data register */
0047 #define AMD_EC_SC   0x04    /* status of controller */
0048 #define AMD_EC_CMD  0x04    /* command register */
0049 #define AMD_EC_ICR  0x08    /* interrupt control register */
0050
0051 #define AMD_EC_SC_SMI   0x04    /* smi event pending */
0052 #define AMD_EC_SC_SCI   0x02    /* sci event pending */
0053 #define AMD_EC_SC_BURST 0x01    /* burst mode enabled */
0054 #define AMD_EC_SC_CMD   0x08    /* byte in data reg is command */
0055 #define AMD_EC_SC_IBF   0x02    /* data ready for embedded controller */
0056 #define AMD_EC_SC_OBF   0x01    /* data ready for host */
0057
0058 #define AMD_EC_CMD_RD   0x80    /* read EC */
0059 #define AMD_EC_CMD_WR   0x81    /* write EC */
0060 #define AMD_EC_CMD_BE   0x82    /* enable burst mode */
0061 #define AMD_EC_CMD_BD   0x83    /* disable burst mode */
0062 #define AMD_EC_CMD_QR   0x84    /* query EC */
0063
0064 /*
0065  * ACPI 2.0 chapter 13 access of registers of the EC
0066  */
0067
0068 static int amd_ec_wait_write(struct amd_smbus *smbus)
0069 {
0070     int timeout = 500;
0071
0072     while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
0073         udelay(1);
0074
0075     if (!timeout) {
0076         dev_warn(&smbus->dev->dev,
0077              "Timeout while waiting for IBF to clear\n");
0078         return -ETIMEDOUT;
0079     }
0080
0081     return 0;
0082 }
0083
0084 static int amd_ec_wait_read(struct amd_smbus *smbus)
0085 {
0086     int timeout = 500;
0087
0088     while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
0089         udelay(1);
0090
0091     if (!timeout) {
0092         dev_warn(&smbus->dev->dev,
0093              "Timeout while waiting for OBF to set\n");
0094         return -ETIMEDOUT;
0095     }
0096
0097     return 0;
0098 }
0099
0100 static int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
0101         unsigned char *data)
0102 {
0103     int status;
0104
0105     status = amd_ec_wait_write(smbus);
0106     if (status)
0107         return status;
0108     outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
0109
0110     status = amd_ec_wait_write(smbus);
0111     if (status)
0112         return status;
0113     outb(address, smbus->base + AMD_EC_DATA);
0114
0115     status = amd_ec_wait_read(smbus);
0116     if (status)
0117         return status;
0118     *data = inb(smbus->base + AMD_EC_DATA);
0119
0120     return 0;
0121 }
0122
0123 static int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
0124         unsigned char data)
0125 {
0126     int status;
0127
0128     status = amd_ec_wait_write(smbus);
0129     if (status)
0130         return status;
0131     outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
0132
0133     status = amd_ec_wait_write(smbus);
0134     if (status)
0135         return status;
0136     outb(address, smbus->base + AMD_EC_DATA);
0137
0138     status = amd_ec_wait_write(smbus);
0139     if (status)
0140         return status;
0141     outb(data, smbus->base + AMD_EC_DATA);
0142
0143     return 0;
0144 }
0145
0146 /*
0147  * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
0148  */
0149
0150 #define AMD_SMB_PRTCL   0x00    /* protocol, PEC */
0151 #define AMD_SMB_STS 0x01    /* status */
0152 #define AMD_SMB_ADDR    0x02    /* address */
0153 #define AMD_SMB_CMD 0x03    /* command */
0154 #define AMD_SMB_DATA    0x04    /* 32 data registers */
0155 #define AMD_SMB_BCNT    0x24    /* number of data bytes */
0156 #define AMD_SMB_ALRM_A  0x25    /* alarm address */
0157 #define AMD_SMB_ALRM_D  0x26    /* 2 bytes alarm data */
0158
0159 #define AMD_SMB_STS_DONE    0x80
0160 #define AMD_SMB_STS_ALRM    0x40
0161 #define AMD_SMB_STS_RES     0x20
0162 #define AMD_SMB_STS_STATUS  0x1f
0163
0164 #define AMD_SMB_STATUS_OK   0x00
0165 #define AMD_SMB_STATUS_FAIL 0x07
0166 #define AMD_SMB_STATUS_DNAK 0x10
0167 #define AMD_SMB_STATUS_DERR 0x11
0168 #define AMD_SMB_STATUS_CMD_DENY 0x12
0169 #define AMD_SMB_STATUS_UNKNOWN  0x13
0170 #define AMD_SMB_STATUS_ACC_DENY 0x17
0171 #define AMD_SMB_STATUS_TIMEOUT  0x18
0172 #define AMD_SMB_STATUS_NOTSUP   0x19
0173 #define AMD_SMB_STATUS_BUSY 0x1A
0174 #define AMD_SMB_STATUS_PEC  0x1F
0175
0176 #define AMD_SMB_PRTCL_WRITE     0x00
0177 #define AMD_SMB_PRTCL_READ      0x01
0178 #define AMD_SMB_PRTCL_QUICK     0x02
0179 #define AMD_SMB_PRTCL_BYTE      0x04
0180 #define AMD_SMB_PRTCL_BYTE_DATA     0x06
0181 #define AMD_SMB_PRTCL_WORD_DATA     0x08
0182 #define AMD_SMB_PRTCL_BLOCK_DATA    0x0a
0183 #define AMD_SMB_PRTCL_PROC_CALL     0x0c
0184 #define AMD_SMB_PRTCL_BLOCK_PROC_CALL   0x0d
0185 #define AMD_SMB_PRTCL_I2C_BLOCK_DATA    0x4a
0186 #define AMD_SMB_PRTCL_PEC       0x80
0187
0188
0189 static s32 amd8111_access(struct i2c_adapter *adap, u16 addr,
0190         unsigned short flags, char read_write, u8 command, int size,
0191         union i2c_smbus_data *data)
0192 {
0193     struct amd_smbus *smbus = adap->algo_data;
0194     unsigned char protocol, len, pec, temp[2];
0195     int i, status;
0196
0197     protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
0198                           : AMD_SMB_PRTCL_WRITE;
0199     pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
0200
0201     switch (size) {
0202     case I2C_SMBUS_QUICK:
0203         protocol |= AMD_SMB_PRTCL_QUICK;
0204         read_write = I2C_SMBUS_WRITE;
0205         break;
0206
0207     case I2C_SMBUS_BYTE:
0208         if (read_write == I2C_SMBUS_WRITE) {
0209             status = amd_ec_write(smbus, AMD_SMB_CMD,
0210                         command);
0211             if (status)
0212                 return status;
0213         }
0214         protocol |= AMD_SMB_PRTCL_BYTE;
0215         break;
0216
0217     case I2C_SMBUS_BYTE_DATA:
0218         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0219         if (status)
0220             return status;
0221         if (read_write == I2C_SMBUS_WRITE) {
0222             status = amd_ec_write(smbus, AMD_SMB_DATA,
0223                         data->byte);
0224             if (status)
0225                 return status;
0226         }
0227         protocol |= AMD_SMB_PRTCL_BYTE_DATA;
0228         break;
0229
0230     case I2C_SMBUS_WORD_DATA:
0231         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0232         if (status)
0233             return status;
0234         if (read_write == I2C_SMBUS_WRITE) {
0235             status = amd_ec_write(smbus, AMD_SMB_DATA,
0236                         data->word & 0xff);
0237             if (status)
0238                 return status;
0239             status = amd_ec_write(smbus, AMD_SMB_DATA + 1,
0240                         data->word >> 8);
0241             if (status)
0242                 return status;
0243         }
0244         protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
0245         break;
0246
0247     case I2C_SMBUS_BLOCK_DATA:
0248         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0249         if (status)
0250             return status;
0251         if (read_write == I2C_SMBUS_WRITE) {
0252             len = min_t(u8, data->block[0],
0253                     I2C_SMBUS_BLOCK_MAX);
0254             status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
0255             if (status)
0256                 return status;
0257             for (i = 0; i < len; i++) {
0258                 status =
0259                     amd_ec_write(smbus, AMD_SMB_DATA + i,
0260                         data->block[i + 1]);
0261                 if (status)
0262                     return status;
0263             }
0264         }
0265         protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
0266         break;
0267
0268     case I2C_SMBUS_I2C_BLOCK_DATA:
0269         len = min_t(u8, data->block[0],
0270                 I2C_SMBUS_BLOCK_MAX);
0271         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0272         if (status)
0273             return status;
0274         status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
0275         if (status)
0276             return status;
0277         if (read_write == I2C_SMBUS_WRITE)
0278             for (i = 0; i < len; i++) {
0279                 status =
0280                     amd_ec_write(smbus, AMD_SMB_DATA + i,
0281                         data->block[i + 1]);
0282                 if (status)
0283                     return status;
0284             }
0285         protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
0286         break;
0287
0288     case I2C_SMBUS_PROC_CALL:
0289         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0290         if (status)
0291             return status;
0292         status = amd_ec_write(smbus, AMD_SMB_DATA,
0293                     data->word & 0xff);
0294         if (status)
0295             return status;
0296         status = amd_ec_write(smbus, AMD_SMB_DATA + 1,
0297                     data->word >> 8);
0298         if (status)
0299             return status;
0300         protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
0301         read_write = I2C_SMBUS_READ;
0302         break;
0303
0304     case I2C_SMBUS_BLOCK_PROC_CALL:
0305         len = min_t(u8, data->block[0],
0306                 I2C_SMBUS_BLOCK_MAX - 1);
0307         status = amd_ec_write(smbus, AMD_SMB_CMD, command);
0308         if (status)
0309             return status;
0310         status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
0311         if (status)
0312             return status;
0313         for (i = 0; i < len; i++) {
0314             status = amd_ec_write(smbus, AMD_SMB_DATA + i,
0315                         data->block[i + 1]);
0316             if (status)
0317                 return status;
0318         }
0319         protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
0320         read_write = I2C_SMBUS_READ;
0321         break;
0322
0323     default:
0324         dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
0325         return -EOPNOTSUPP;
0326     }
0327
0328     status = amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
0329     if (status)
0330         return status;
0331     status = amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
0332     if (status)
0333         return status;
0334
0335     status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
0336     if (status)
0337         return status;
0338
0339     if (~temp[0] & AMD_SMB_STS_DONE) {
0340         udelay(500);
0341         status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
0342         if (status)
0343             return status;
0344     }
0345
0346     if (~temp[0] & AMD_SMB_STS_DONE) {
0347         msleep(1);
0348         status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
0349         if (status)
0350             return status;
0351     }
0352
0353     if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
0354         return -EIO;
0355
0356     if (read_write == I2C_SMBUS_WRITE)
0357         return 0;
0358
0359     switch (size) {
0360     case I2C_SMBUS_BYTE:
0361     case I2C_SMBUS_BYTE_DATA:
0362         status = amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
0363         if (status)
0364             return status;
0365         break;
0366
0367     case I2C_SMBUS_WORD_DATA:
0368     case I2C_SMBUS_PROC_CALL:
0369         status = amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
0370         if (status)
0371             return status;
0372         status = amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
0373         if (status)
0374             return status;
0375         data->word = (temp[1] << 8) | temp[0];
0376         break;
0377
0378     case I2C_SMBUS_BLOCK_DATA:
0379     case I2C_SMBUS_BLOCK_PROC_CALL:
0380         status = amd_ec_read(smbus, AMD_SMB_BCNT, &len);
0381         if (status)
0382             return status;
0383         len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
0384         fallthrough;
0385     case I2C_SMBUS_I2C_BLOCK_DATA:
0386         for (i = 0; i < len; i++) {
0387             status = amd_ec_read(smbus, AMD_SMB_DATA + i,
0388                         data->block + i + 1);
0389             if (status)
0390                 return status;
0391         }
0392         data->block[0] = len;
0393         break;
0394     }
0395
0396     return 0;
0397 }
0398
0399
0400 static u32 amd8111_func(struct i2c_adapter *adapter)
0401 {
0402     return  I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
0403         I2C_FUNC_SMBUS_BYTE_DATA |
0404         I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
0405         I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
0406         I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
0407 }
0408
0409 static const struct i2c_algorithm smbus_algorithm = {
0410     .smbus_xfer = amd8111_access,
0411     .functionality = amd8111_func,
0412 };
0413
0414
0415 static const struct pci_device_id amd8111_ids[] = {
0416     { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
0417     { 0, }
0418 };
0419
0420 MODULE_DEVICE_TABLE (pci, amd8111_ids);
0421
0422 static int amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id)
0423 {
0424     struct amd_smbus *smbus;
0425     int error;
0426
0427     if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
0428         return -ENODEV;
0429
0430     smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
0431     if (!smbus)
0432         return -ENOMEM;
0433
0434     smbus->dev = dev;
0435     smbus->base = pci_resource_start(dev, 0);
0436     smbus->size = pci_resource_len(dev, 0);
0437
0438     error = acpi_check_resource_conflict(&dev->resource[0]);
0439     if (error) {
0440         error = -ENODEV;
0441         goto out_kfree;
0442     }
0443
0444     if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
0445         error = -EBUSY;
0446         goto out_kfree;
0447     }
0448
0449     smbus->adapter.owner = THIS_MODULE;
0450     snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
0451         "SMBus2 AMD8111 adapter at %04x", smbus->base);
0452     smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
0453     smbus->adapter.algo = &smbus_algorithm;
0454     smbus->adapter.algo_data = smbus;
0455
0456     /* set up the sysfs linkage to our parent device */
0457     smbus->adapter.dev.parent = &dev->dev;
0458
0459     pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
0460     error = i2c_add_adapter(&smbus->adapter);
0461     if (error)
0462         goto out_release_region;
0463
0464     pci_set_drvdata(dev, smbus);
0465     return 0;
0466
0467  out_release_region:
0468     release_region(smbus->base, smbus->size);
0469  out_kfree:
0470     kfree(smbus);
0471     return error;
0472 }
0473
0474 static void amd8111_remove(struct pci_dev *dev)
0475 {
0476     struct amd_smbus *smbus = pci_get_drvdata(dev);
0477
0478     i2c_del_adapter(&smbus->adapter);
0479     release_region(smbus->base, smbus->size);
0480     kfree(smbus);
0481 }
0482
0483 static struct pci_driver amd8111_driver = {
0484     .name       = "amd8111_smbus2",
0485     .id_table   = amd8111_ids,
0486     .probe      = amd8111_probe,
0487     .remove     = amd8111_remove,
0488 };
0489
0490 module_pci_driver(amd8111_driver);