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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright Intel Corporation (C) 2017.
0004  *
0005  * Based on the i2c-axxia.c driver.
0006  */
0007 #include <linux/clk.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/err.h>
0010 #include <linux/i2c.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/module.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/platform_device.h>
0017 
0018 #define ALTR_I2C_TFR_CMD    0x00    /* Transfer Command register */
0019 #define     ALTR_I2C_TFR_CMD_STA    BIT(9)  /* send START before byte */
0020 #define     ALTR_I2C_TFR_CMD_STO    BIT(8)  /* send STOP after byte */
0021 #define     ALTR_I2C_TFR_CMD_RW_D   BIT(0)  /* Direction of transfer */
0022 #define ALTR_I2C_RX_DATA    0x04    /* RX data FIFO register */
0023 #define ALTR_I2C_CTRL       0x08    /* Control register */
0024 #define     ALTR_I2C_CTRL_RXT_SHFT  4   /* RX FIFO Threshold */
0025 #define     ALTR_I2C_CTRL_TCT_SHFT  2   /* TFER CMD FIFO Threshold */
0026 #define     ALTR_I2C_CTRL_BSPEED    BIT(1)  /* Bus Speed (1=Fast) */
0027 #define     ALTR_I2C_CTRL_EN    BIT(0)  /* Enable Core (1=Enable) */
0028 #define ALTR_I2C_ISER       0x0C    /* Interrupt Status Enable register */
0029 #define     ALTR_I2C_ISER_RXOF_EN   BIT(4)  /* Enable RX OVERFLOW IRQ */
0030 #define     ALTR_I2C_ISER_ARB_EN    BIT(3)  /* Enable ARB LOST IRQ */
0031 #define     ALTR_I2C_ISER_NACK_EN   BIT(2)  /* Enable NACK DET IRQ */
0032 #define     ALTR_I2C_ISER_RXRDY_EN  BIT(1)  /* Enable RX Ready IRQ */
0033 #define     ALTR_I2C_ISER_TXRDY_EN  BIT(0)  /* Enable TX Ready IRQ */
0034 #define ALTR_I2C_ISR        0x10    /* Interrupt Status register */
0035 #define     ALTR_I2C_ISR_RXOF       BIT(4)  /* RX OVERFLOW IRQ */
0036 #define     ALTR_I2C_ISR_ARB        BIT(3)  /* ARB LOST IRQ */
0037 #define     ALTR_I2C_ISR_NACK       BIT(2)  /* NACK DET IRQ */
0038 #define     ALTR_I2C_ISR_RXRDY      BIT(1)  /* RX Ready IRQ */
0039 #define     ALTR_I2C_ISR_TXRDY      BIT(0)  /* TX Ready IRQ */
0040 #define ALTR_I2C_STATUS     0x14    /* Status register */
0041 #define     ALTR_I2C_STAT_CORE      BIT(0)  /* Core Status (0=idle) */
0042 #define ALTR_I2C_TC_FIFO_LVL    0x18    /* Transfer FIFO LVL register */
0043 #define ALTR_I2C_RX_FIFO_LVL    0x1C    /* Receive FIFO LVL register */
0044 #define ALTR_I2C_SCL_LOW    0x20    /* SCL low count register */
0045 #define ALTR_I2C_SCL_HIGH   0x24    /* SCL high count register */
0046 #define ALTR_I2C_SDA_HOLD   0x28    /* SDA hold count register */
0047 
0048 #define ALTR_I2C_ALL_IRQ    (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
0049                  ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
0050                  ALTR_I2C_ISR_TXRDY)
0051 
0052 #define ALTR_I2C_THRESHOLD  0   /* IRQ Threshold at 1 element */
0053 #define ALTR_I2C_DFLT_FIFO_SZ   4
0054 #define ALTR_I2C_TIMEOUT    100000  /* 100ms */
0055 #define ALTR_I2C_XFER_TIMEOUT   (msecs_to_jiffies(250))
0056 
0057 /**
0058  * struct altr_i2c_dev - I2C device context
0059  * @base: pointer to register struct
0060  * @msg: pointer to current message
0061  * @msg_len: number of bytes transferred in msg
0062  * @msg_err: error code for completed message
0063  * @msg_complete: xfer completion object
0064  * @dev: device reference
0065  * @adapter: core i2c abstraction
0066  * @i2c_clk: clock reference for i2c input clock
0067  * @bus_clk_rate: current i2c bus clock rate
0068  * @buf: ptr to msg buffer for easier use.
0069  * @fifo_size: size of the FIFO passed in.
0070  * @isr_mask: cached copy of local ISR enables.
0071  * @isr_status: cached copy of local ISR status.
0072  * @isr_mutex: mutex for IRQ thread.
0073  */
0074 struct altr_i2c_dev {
0075     void __iomem *base;
0076     struct i2c_msg *msg;
0077     size_t msg_len;
0078     int msg_err;
0079     struct completion msg_complete;
0080     struct device *dev;
0081     struct i2c_adapter adapter;
0082     struct clk *i2c_clk;
0083     u32 bus_clk_rate;
0084     u8 *buf;
0085     u32 fifo_size;
0086     u32 isr_mask;
0087     u32 isr_status;
0088     struct mutex isr_mutex;
0089 };
0090 
0091 static void
0092 altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
0093 {
0094     u32 int_en;
0095 
0096     int_en = readl(idev->base + ALTR_I2C_ISER);
0097     if (enable)
0098         idev->isr_mask = int_en | mask;
0099     else
0100         idev->isr_mask = int_en & ~mask;
0101 
0102     writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
0103 }
0104 
0105 static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
0106 {
0107     u32 int_en = readl(idev->base + ALTR_I2C_ISR);
0108 
0109     writel(int_en | mask, idev->base + ALTR_I2C_ISR);
0110 }
0111 
0112 static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
0113 {
0114     u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
0115 
0116     writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
0117 }
0118 
0119 static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
0120 {
0121     u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
0122 
0123     writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
0124 }
0125 
0126 static void altr_i2c_reset(struct altr_i2c_dev *idev)
0127 {
0128     altr_i2c_core_disable(idev);
0129     altr_i2c_core_enable(idev);
0130 }
0131 
0132 static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
0133 {
0134     writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
0135 }
0136 
0137 static void altr_i2c_init(struct altr_i2c_dev *idev)
0138 {
0139     u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
0140     u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
0141     u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
0142           (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
0143     u32 t_high, t_low;
0144 
0145     if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
0146         tmp &= ~ALTR_I2C_CTRL_BSPEED;
0147         /* Standard mode SCL 50/50 */
0148         t_high = divisor * 1 / 2;
0149         t_low = divisor * 1 / 2;
0150     } else {
0151         tmp |= ALTR_I2C_CTRL_BSPEED;
0152         /* Fast mode SCL 33/66 */
0153         t_high = divisor * 1 / 3;
0154         t_low = divisor * 2 / 3;
0155     }
0156     writel(tmp, idev->base + ALTR_I2C_CTRL);
0157 
0158     dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
0159         idev->bus_clk_rate, clk_mhz, divisor);
0160 
0161     /* Reset controller */
0162     altr_i2c_reset(idev);
0163 
0164     /* SCL High Time */
0165     writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
0166     /* SCL Low Time */
0167     writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
0168     /* SDA Hold Time, 300ns */
0169     writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
0170 
0171     /* Mask all master interrupt bits */
0172     altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
0173 }
0174 
0175 /*
0176  * altr_i2c_transfer - On the last byte to be transmitted, send
0177  * a Stop bit on the last byte.
0178  */
0179 static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
0180 {
0181     /* On the last byte to be transmitted, send STOP */
0182     if (idev->msg_len == 1)
0183         data |= ALTR_I2C_TFR_CMD_STO;
0184     if (idev->msg_len > 0)
0185         writel(data, idev->base + ALTR_I2C_TFR_CMD);
0186 }
0187 
0188 /*
0189  * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
0190  * transfer. Send a Stop bit on the last byte.
0191  */
0192 static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
0193 {
0194     size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
0195     int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
0196 
0197     while (bytes_to_transfer-- > 0) {
0198         *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
0199         idev->msg_len--;
0200         altr_i2c_transfer(idev, 0);
0201     }
0202 }
0203 
0204 /*
0205  * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
0206  */
0207 static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
0208 {
0209     size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
0210                                ALTR_I2C_TC_FIFO_LVL);
0211     int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
0212     int ret = idev->msg_len - bytes_to_transfer;
0213 
0214     while (bytes_to_transfer-- > 0) {
0215         altr_i2c_transfer(idev, *idev->buf++);
0216         idev->msg_len--;
0217     }
0218 
0219     return ret;
0220 }
0221 
0222 static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
0223 {
0224     struct altr_i2c_dev *idev = _dev;
0225     irqreturn_t ret = IRQ_HANDLED;
0226 
0227     /* Read IRQ status but only interested in Enabled IRQs. */
0228     idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
0229     if (idev->isr_status)
0230         ret = IRQ_WAKE_THREAD;
0231 
0232     return ret;
0233 }
0234 
0235 static irqreturn_t altr_i2c_isr(int irq, void *_dev)
0236 {
0237     int ret;
0238     bool read, finish = false;
0239     struct altr_i2c_dev *idev = _dev;
0240     u32 status = idev->isr_status;
0241 
0242     mutex_lock(&idev->isr_mutex);
0243     if (!idev->msg) {
0244         dev_warn(idev->dev, "unexpected interrupt\n");
0245         altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
0246         goto out;
0247     }
0248     read = (idev->msg->flags & I2C_M_RD) != 0;
0249 
0250     /* handle Lost Arbitration */
0251     if (unlikely(status & ALTR_I2C_ISR_ARB)) {
0252         altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
0253         idev->msg_err = -EAGAIN;
0254         finish = true;
0255     } else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
0256         dev_dbg(idev->dev, "Could not get ACK\n");
0257         idev->msg_err = -ENXIO;
0258         altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
0259         altr_i2c_stop(idev);
0260         finish = true;
0261     } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
0262         /* handle RX FIFO Overflow */
0263         altr_i2c_empty_rx_fifo(idev);
0264         altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
0265         altr_i2c_stop(idev);
0266         dev_err(idev->dev, "RX FIFO Overflow\n");
0267         finish = true;
0268     } else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
0269         /* RX FIFO needs service? */
0270         altr_i2c_empty_rx_fifo(idev);
0271         altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
0272         if (!idev->msg_len)
0273             finish = true;
0274     } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
0275         /* TX FIFO needs service? */
0276         altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
0277         if (idev->msg_len > 0)
0278             altr_i2c_fill_tx_fifo(idev);
0279         else
0280             finish = true;
0281     } else {
0282         dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
0283         altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
0284     }
0285 
0286     if (finish) {
0287         /* Wait for the Core to finish */
0288         ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
0289                         status,
0290                         !(status & ALTR_I2C_STAT_CORE),
0291                         1, ALTR_I2C_TIMEOUT);
0292         if (ret)
0293             dev_err(idev->dev, "message timeout\n");
0294         altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
0295         altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
0296         complete(&idev->msg_complete);
0297         dev_dbg(idev->dev, "Message Complete\n");
0298     }
0299 out:
0300     mutex_unlock(&idev->isr_mutex);
0301 
0302     return IRQ_HANDLED;
0303 }
0304 
0305 static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
0306 {
0307     u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
0308     unsigned long time_left;
0309     u32 value;
0310     u8 addr = i2c_8bit_addr_from_msg(msg);
0311 
0312     mutex_lock(&idev->isr_mutex);
0313     idev->msg = msg;
0314     idev->msg_len = msg->len;
0315     idev->buf = msg->buf;
0316     idev->msg_err = 0;
0317     reinit_completion(&idev->msg_complete);
0318     altr_i2c_core_enable(idev);
0319 
0320     /* Make sure RX FIFO is empty */
0321     do {
0322         readl(idev->base + ALTR_I2C_RX_DATA);
0323     } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
0324 
0325     writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
0326 
0327     if ((msg->flags & I2C_M_RD) != 0) {
0328         imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
0329         altr_i2c_int_enable(idev, imask, true);
0330         /* write the first byte to start the RX */
0331         altr_i2c_transfer(idev, 0);
0332     } else {
0333         imask |= ALTR_I2C_ISR_TXRDY;
0334         altr_i2c_int_enable(idev, imask, true);
0335         altr_i2c_fill_tx_fifo(idev);
0336     }
0337     mutex_unlock(&idev->isr_mutex);
0338 
0339     time_left = wait_for_completion_timeout(&idev->msg_complete,
0340                         ALTR_I2C_XFER_TIMEOUT);
0341     mutex_lock(&idev->isr_mutex);
0342     altr_i2c_int_enable(idev, imask, false);
0343 
0344     value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
0345     if (value)
0346         dev_err(idev->dev, "Core Status not IDLE...\n");
0347 
0348     if (time_left == 0) {
0349         idev->msg_err = -ETIMEDOUT;
0350         dev_dbg(idev->dev, "Transaction timed out.\n");
0351     }
0352 
0353     altr_i2c_core_disable(idev);
0354     mutex_unlock(&idev->isr_mutex);
0355 
0356     return idev->msg_err;
0357 }
0358 
0359 static int
0360 altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0361 {
0362     struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
0363     int i, ret;
0364 
0365     for (i = 0; i < num; i++) {
0366         ret = altr_i2c_xfer_msg(idev, msgs++);
0367         if (ret)
0368             return ret;
0369     }
0370     return num;
0371 }
0372 
0373 static u32 altr_i2c_func(struct i2c_adapter *adap)
0374 {
0375     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0376 }
0377 
0378 static const struct i2c_algorithm altr_i2c_algo = {
0379     .master_xfer = altr_i2c_xfer,
0380     .functionality = altr_i2c_func,
0381 };
0382 
0383 static int altr_i2c_probe(struct platform_device *pdev)
0384 {
0385     struct altr_i2c_dev *idev = NULL;
0386     int irq, ret;
0387 
0388     idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
0389     if (!idev)
0390         return -ENOMEM;
0391 
0392     idev->base = devm_platform_ioremap_resource(pdev, 0);
0393     if (IS_ERR(idev->base))
0394         return PTR_ERR(idev->base);
0395 
0396     irq = platform_get_irq(pdev, 0);
0397     if (irq < 0)
0398         return irq;
0399 
0400     idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
0401     if (IS_ERR(idev->i2c_clk)) {
0402         dev_err(&pdev->dev, "missing clock\n");
0403         return PTR_ERR(idev->i2c_clk);
0404     }
0405 
0406     idev->dev = &pdev->dev;
0407     init_completion(&idev->msg_complete);
0408     mutex_init(&idev->isr_mutex);
0409 
0410     ret = device_property_read_u32(idev->dev, "fifo-size",
0411                        &idev->fifo_size);
0412     if (ret) {
0413         dev_err(&pdev->dev, "FIFO size set to default of %d\n",
0414             ALTR_I2C_DFLT_FIFO_SZ);
0415         idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
0416     }
0417 
0418     ret = device_property_read_u32(idev->dev, "clock-frequency",
0419                        &idev->bus_clk_rate);
0420     if (ret) {
0421         dev_err(&pdev->dev, "Default to 100kHz\n");
0422         idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;    /* default clock rate */
0423     }
0424 
0425     if (idev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) {
0426         dev_err(&pdev->dev, "invalid clock-frequency %d\n",
0427             idev->bus_clk_rate);
0428         return -EINVAL;
0429     }
0430 
0431     ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
0432                     altr_i2c_isr, IRQF_ONESHOT,
0433                     pdev->name, idev);
0434     if (ret) {
0435         dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
0436         return ret;
0437     }
0438 
0439     ret = clk_prepare_enable(idev->i2c_clk);
0440     if (ret) {
0441         dev_err(&pdev->dev, "failed to enable clock\n");
0442         return ret;
0443     }
0444 
0445     mutex_lock(&idev->isr_mutex);
0446     altr_i2c_init(idev);
0447     mutex_unlock(&idev->isr_mutex);
0448 
0449     i2c_set_adapdata(&idev->adapter, idev);
0450     strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
0451     idev->adapter.owner = THIS_MODULE;
0452     idev->adapter.algo = &altr_i2c_algo;
0453     idev->adapter.dev.parent = &pdev->dev;
0454     idev->adapter.dev.of_node = pdev->dev.of_node;
0455 
0456     platform_set_drvdata(pdev, idev);
0457 
0458     ret = i2c_add_adapter(&idev->adapter);
0459     if (ret) {
0460         clk_disable_unprepare(idev->i2c_clk);
0461         return ret;
0462     }
0463     dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
0464 
0465     return 0;
0466 }
0467 
0468 static int altr_i2c_remove(struct platform_device *pdev)
0469 {
0470     struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
0471 
0472     clk_disable_unprepare(idev->i2c_clk);
0473     i2c_del_adapter(&idev->adapter);
0474 
0475     return 0;
0476 }
0477 
0478 /* Match table for of_platform binding */
0479 static const struct of_device_id altr_i2c_of_match[] = {
0480     { .compatible = "altr,softip-i2c-v1.0" },
0481     {},
0482 };
0483 MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
0484 
0485 static struct platform_driver altr_i2c_driver = {
0486     .probe = altr_i2c_probe,
0487     .remove = altr_i2c_remove,
0488     .driver = {
0489         .name = "altera-i2c",
0490         .of_match_table = altr_i2c_of_match,
0491     },
0492 };
0493 
0494 module_platform_driver(altr_i2c_driver);
0495 
0496 MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
0497 MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
0498 MODULE_LICENSE("GPL v2");
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