hwtracing/intel_th/msu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
0004  *
0005  * Copyright (C) 2014-2015 Intel Corporation.
0006  */
0007
0008 #ifndef __INTEL_TH_MSU_H__
0009 #define __INTEL_TH_MSU_H__
0010
0011 enum {
0012     REG_MSU_MSUPARAMS   = 0x0000,
0013     REG_MSU_MSUSTS      = 0x0008,
0014     REG_MSU_MINTCTL     = 0x0004, /* MSU-global interrupt control */
0015     REG_MSU_MSC0CTL     = 0x0100, /* MSC0 control */
0016     REG_MSU_MSC0STS     = 0x0104, /* MSC0 status */
0017     REG_MSU_MSC0BAR     = 0x0108, /* MSC0 output base address */
0018     REG_MSU_MSC0SIZE    = 0x010c, /* MSC0 output size */
0019     REG_MSU_MSC0MWP     = 0x0110, /* MSC0 write pointer */
0020     REG_MSU_MSC0NWSA    = 0x011c, /* MSC0 next window start address */
0021
0022     REG_MSU_MSC1CTL     = 0x0200, /* MSC1 control */
0023     REG_MSU_MSC1STS     = 0x0204, /* MSC1 status */
0024     REG_MSU_MSC1BAR     = 0x0208, /* MSC1 output base address */
0025     REG_MSU_MSC1SIZE    = 0x020c, /* MSC1 output size */
0026     REG_MSU_MSC1MWP     = 0x0210, /* MSC1 write pointer */
0027     REG_MSU_MSC1NWSA    = 0x021c, /* MSC1 next window start address */
0028 };
0029
0030 /* MSUSTS bits */
0031 #define MSUSTS_MSU_INT  BIT(0)
0032 #define MSUSTS_MSC0BLAST    BIT(16)
0033 #define MSUSTS_MSC1BLAST    BIT(24)
0034
0035 /* MSCnCTL bits */
0036 #define MSC_EN      BIT(0)
0037 #define MSC_WRAPEN  BIT(1)
0038 #define MSC_RD_HDR_OVRD BIT(2)
0039 #define MSC_MODE    (BIT(4) | BIT(5))
0040 #define MSC_LEN     (BIT(8) | BIT(9) | BIT(10))
0041
0042 /* MINTCTL bits */
0043 #define MICDE       BIT(0)
0044 #define M0BLIE      BIT(16)
0045 #define M1BLIE      BIT(24)
0046
0047 /* MSCnSTS bits */
0048 #define MSCSTS_WRAPSTAT BIT(1)  /* Wrap occurred */
0049 #define MSCSTS_PLE  BIT(2)  /* Pipeline Empty */
0050
0051 /*
0052  * Multiblock/multiwindow block descriptor
0053  */
0054 struct msc_block_desc {
0055     u32 sw_tag;
0056     u32 block_sz;
0057     u32 next_blk;
0058     u32 next_win;
0059     u32 res0[4];
0060     u32 hw_tag;
0061     u32 valid_dw;
0062     u32 ts_low;
0063     u32 ts_high;
0064     u32 res1[4];
0065 } __packed;
0066
0067 #define MSC_BDESC   sizeof(struct msc_block_desc)
0068 #define DATA_IN_PAGE    (PAGE_SIZE - MSC_BDESC)
0069
0070 /* MSC multiblock sw tag bits */
0071 #define MSC_SW_TAG_LASTBLK  BIT(0)
0072 #define MSC_SW_TAG_LASTWIN  BIT(1)
0073
0074 /* MSC multiblock hw tag bits */
0075 #define MSC_HW_TAG_TRIGGER  BIT(0)
0076 #define MSC_HW_TAG_BLOCKWRAP    BIT(1)
0077 #define MSC_HW_TAG_WINWRAP  BIT(2)
0078 #define MSC_HW_TAG_ENDBIT   BIT(3)
0079
0080 static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
0081 {
0082     if (!bdesc->valid_dw)
0083         return 0;
0084
0085     return bdesc->valid_dw * 4 - MSC_BDESC;
0086 }
0087
0088 static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
0089 {
0090     return bdesc->valid_dw * 4;
0091 }
0092
0093 static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
0094 {
0095     return bdesc->block_sz * 64 - MSC_BDESC;
0096 }
0097
0098 static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
0099 {
0100     if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
0101         return true;
0102
0103     return false;
0104 }
0105
0106 static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
0107 {
0108     if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
0109         (msc_data_sz(bdesc) != msc_block_sz(bdesc)))
0110         return true;
0111
0112     return false;
0113 }
0114
0115 /* waiting for Pipeline Empty bit(s) to assert for MSC */
0116 #define MSC_PLE_WAITLOOP_DEPTH  10000
0117
0118 #endif /* __INTEL_TH_MSU_H__ */