hwtracing/intel_th/intel_th.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Intel(R) Trace Hub data structures
0004  *
0005  * Copyright (C) 2014-2015 Intel Corporation.
0006  */
0007
0008 #ifndef __INTEL_TH_H__
0009 #define __INTEL_TH_H__
0010
0011 #include <linux/irqreturn.h>
0012
0013 /* intel_th_device device types */
0014 enum {
0015     /* Devices that generate trace data */
0016     INTEL_TH_SOURCE = 0,
0017     /* Output ports (MSC, PTI) */
0018     INTEL_TH_OUTPUT,
0019     /* Switch, the Global Trace Hub (GTH) */
0020     INTEL_TH_SWITCH,
0021 };
0022
0023 struct intel_th_device;
0024
0025 /**
0026  * struct intel_th_output - descriptor INTEL_TH_OUTPUT type devices
0027  * @port:   output port number, assigned by the switch
0028  * @type:   GTH_{MSU,CTP,PTI}
0029  * @scratchpad: scratchpad bits to flag when this output is enabled
0030  * @multiblock: true for multiblock output configuration
0031  * @active: true when this output is enabled
0032  * @wait_empty: wait for device pipeline to be empty
0033  *
0034  * Output port descriptor, used by switch driver to tell which output
0035  * port this output device corresponds to. Filled in at output device's
0036  * probe time by switch::assign(). Passed from output device driver to
0037  * switch related code to enable/disable its port.
0038  */
0039 struct intel_th_output {
0040     int     port;
0041     unsigned int    type;
0042     unsigned int    scratchpad;
0043     bool        multiblock;
0044     bool        active;
0045 };
0046
0047 /**
0048  * struct intel_th_drvdata - describes hardware capabilities and quirks
0049  * @tscu_enable:    device needs SW to enable time stamping unit
0050  * @multi_is_broken:    device has multiblock mode is broken
0051  * @has_mintctl:    device has interrupt control (MINTCTL) register
0052  * @host_mode_only: device can only operate in 'host debugger' mode
0053  */
0054 struct intel_th_drvdata {
0055     unsigned int    tscu_enable        : 1,
0056             multi_is_broken    : 1,
0057             has_mintctl        : 1,
0058             host_mode_only     : 1;
0059 };
0060
0061 #define INTEL_TH_CAP(_th, _cap) ((_th)->drvdata ? (_th)->drvdata->_cap : 0)
0062
0063 /**
0064  * struct intel_th_device - device on the intel_th bus
0065  * @dev:        device
0066  * @drvdata:        hardware capabilities/quirks
0067  * @resource:       array of resources available to this device
0068  * @num_resources:  number of resources in @resource array
0069  * @type:       INTEL_TH_{SOURCE,OUTPUT,SWITCH}
0070  * @id:         device instance or -1
0071  * @host_mode:      Intel TH is controlled by an external debug host
0072  * @output:     output descriptor for INTEL_TH_OUTPUT devices
0073  * @name:       device name to match the driver
0074  */
0075 struct intel_th_device {
0076     struct device       dev;
0077     const struct intel_th_drvdata *drvdata;
0078     struct resource     *resource;
0079     unsigned int        num_resources;
0080     unsigned int        type;
0081     int         id;
0082
0083     /* INTEL_TH_SWITCH specific */
0084     bool            host_mode;
0085
0086     /* INTEL_TH_OUTPUT specific */
0087     struct intel_th_output  output;
0088
0089     char        name[];
0090 };
0091
0092 #define to_intel_th_device(_d)              \
0093     container_of((_d), struct intel_th_device, dev)
0094
0095 /**
0096  * intel_th_device_get_resource() - obtain @num'th resource of type @type
0097  * @thdev:  the device to search the resource for
0098  * @type:   resource type
0099  * @num:    number of the resource
0100  */
0101 static inline struct resource *
0102 intel_th_device_get_resource(struct intel_th_device *thdev, unsigned int type,
0103                  unsigned int num)
0104 {
0105     int i;
0106
0107     for (i = 0; i < thdev->num_resources; i++)
0108         if (resource_type(&thdev->resource[i]) == type && !num--)
0109             return &thdev->resource[i];
0110
0111     return NULL;
0112 }
0113
0114 /*
0115  * GTH, output ports configuration
0116  */
0117 enum {
0118     GTH_NONE = 0,
0119     GTH_MSU,    /* memory/usb */
0120     GTH_CTP,    /* Common Trace Port */
0121     GTH_LPP,    /* Low Power Path */
0122     GTH_PTI,    /* MIPI-PTI */
0123 };
0124
0125 /**
0126  * intel_th_output_assigned() - if an output device is assigned to a switch port
0127  * @thdev:  the output device
0128  *
0129  * Return:  true if the device is INTEL_TH_OUTPUT *and* is assigned a port
0130  */
0131 static inline bool
0132 intel_th_output_assigned(struct intel_th_device *thdev)
0133 {
0134     return thdev->type == INTEL_TH_OUTPUT &&
0135         (thdev->output.port >= 0 ||
0136          thdev->output.type == GTH_NONE);
0137 }
0138
0139 /**
0140  * struct intel_th_driver - driver for an intel_th_device device
0141  * @driver: generic driver
0142  * @probe:  probe method
0143  * @remove: remove method
0144  * @assign: match a given output type device against available outputs
0145  * @unassign:   deassociate an output type device from an output port
0146  * @prepare:    prepare output port for tracing
0147  * @enable: enable tracing for a given output device
0148  * @disable:    disable tracing for a given output device
0149  * @irq:    interrupt callback
0150  * @activate:   enable tracing on the output's side
0151  * @deactivate: disable tracing on the output's side
0152  * @fops:   file operations for device nodes
0153  * @attr_group: attributes provided by the driver
0154  *
0155  * Callbacks @probe and @remove are required for all device types.
0156  * Switch device driver needs to fill in @assign, @enable and @disable
0157  * callbacks.
0158  */
0159 struct intel_th_driver {
0160     struct device_driver    driver;
0161     int         (*probe)(struct intel_th_device *thdev);
0162     void            (*remove)(struct intel_th_device *thdev);
0163     /* switch (GTH) ops */
0164     int         (*assign)(struct intel_th_device *thdev,
0165                       struct intel_th_device *othdev);
0166     void            (*unassign)(struct intel_th_device *thdev,
0167                         struct intel_th_device *othdev);
0168     void            (*prepare)(struct intel_th_device *thdev,
0169                        struct intel_th_output *output);
0170     void            (*enable)(struct intel_th_device *thdev,
0171                       struct intel_th_output *output);
0172     void            (*trig_switch)(struct intel_th_device *thdev,
0173                            struct intel_th_output *output);
0174     void            (*disable)(struct intel_th_device *thdev,
0175                        struct intel_th_output *output);
0176     /* output ops */
0177     irqreturn_t     (*irq)(struct intel_th_device *thdev);
0178     void            (*wait_empty)(struct intel_th_device *thdev);
0179     int         (*activate)(struct intel_th_device *thdev);
0180     void            (*deactivate)(struct intel_th_device *thdev);
0181     /* file_operations for those who want a device node */
0182     const struct file_operations *fops;
0183     /* optional attributes */
0184     const struct attribute_group *attr_group;
0185
0186     /* source ops */
0187     int         (*set_output)(struct intel_th_device *thdev,
0188                           unsigned int master);
0189 };
0190
0191 #define to_intel_th_driver(_d)                  \
0192     container_of((_d), struct intel_th_driver, driver)
0193
0194 #define to_intel_th_driver_or_null(_d)      \
0195     ((_d) ? to_intel_th_driver(_d) : NULL)
0196
0197 /*
0198  * Subdevice tree structure is as follows:
0199  * + struct intel_th device (pci; dev_{get,set}_drvdata()
0200  *   + struct intel_th_device INTEL_TH_SWITCH (GTH)
0201  *     + struct intel_th_device INTEL_TH_OUTPUT (MSU, PTI)
0202  *   + struct intel_th_device INTEL_TH_SOURCE (STH)
0203  *
0204  * In other words, INTEL_TH_OUTPUT devices are children of INTEL_TH_SWITCH;
0205  * INTEL_TH_SWITCH and INTEL_TH_SOURCE are children of the intel_th device.
0206  */
0207 static inline struct intel_th_device *
0208 to_intel_th_parent(struct intel_th_device *thdev)
0209 {
0210     struct device *parent = thdev->dev.parent;
0211
0212     if (!parent)
0213         return NULL;
0214
0215     return to_intel_th_device(parent);
0216 }
0217
0218 static inline struct intel_th *to_intel_th(struct intel_th_device *thdev)
0219 {
0220     if (thdev->type == INTEL_TH_OUTPUT)
0221         thdev = to_intel_th_parent(thdev);
0222
0223     if (WARN_ON_ONCE(!thdev || thdev->type == INTEL_TH_OUTPUT))
0224         return NULL;
0225
0226     return dev_get_drvdata(thdev->dev.parent);
0227 }
0228
0229 struct intel_th *
0230 intel_th_alloc(struct device *dev, const struct intel_th_drvdata *drvdata,
0231            struct resource *devres, unsigned int ndevres);
0232 void intel_th_free(struct intel_th *th);
0233
0234 int intel_th_driver_register(struct intel_th_driver *thdrv);
0235 void intel_th_driver_unregister(struct intel_th_driver *thdrv);
0236
0237 int intel_th_trace_enable(struct intel_th_device *thdev);
0238 int intel_th_trace_switch(struct intel_th_device *thdev);
0239 int intel_th_trace_disable(struct intel_th_device *thdev);
0240 int intel_th_set_output(struct intel_th_device *thdev,
0241             unsigned int master);
0242 int intel_th_output_enable(struct intel_th *th, unsigned int otype);
0243
0244 enum th_mmio_idx {
0245     TH_MMIO_CONFIG = 0,
0246     TH_MMIO_SW = 1,
0247     TH_MMIO_RTIT = 2,
0248     TH_MMIO_END,
0249 };
0250
0251 #define TH_POSSIBLE_OUTPUTS 8
0252 /* Total number of possible subdevices: outputs + GTH + STH */
0253 #define TH_SUBDEVICE_MAX    (TH_POSSIBLE_OUTPUTS + 2)
0254 #define TH_CONFIGURABLE_MASTERS 256
0255 #define TH_MSC_MAX      2
0256
0257 /* Maximum IRQ vectors */
0258 #define TH_NVEC_MAX     8
0259
0260 /**
0261  * struct intel_th - Intel TH controller
0262  * @dev:    driver core's device
0263  * @thdev:  subdevices
0264  * @hub:    "switch" subdevice (GTH)
0265  * @resource:   resources of the entire controller
0266  * @num_thdevs: number of devices in the @thdev array
0267  * @num_resources:  number of resources in the @resource array
0268  * @irq:    irq number
0269  * @num_irqs:   number of IRQs is use
0270  * @id:     this Intel TH controller's device ID in the system
0271  * @major:  device node major for output devices
0272  */
0273 struct intel_th {
0274     struct device       *dev;
0275
0276     struct intel_th_device  *thdev[TH_SUBDEVICE_MAX];
0277     struct intel_th_device  *hub;
0278     const struct intel_th_drvdata   *drvdata;
0279
0280     struct resource     resource[TH_MMIO_END];
0281     int         (*activate)(struct intel_th *);
0282     void            (*deactivate)(struct intel_th *);
0283     unsigned int        num_thdevs;
0284     unsigned int        num_resources;
0285     int         irq;
0286     int         num_irqs;
0287
0288     int         id;
0289     int         major;
0290 #ifdef CONFIG_MODULES
0291     struct work_struct  request_module_work;
0292 #endif /* CONFIG_MODULES */
0293 #ifdef CONFIG_INTEL_TH_DEBUG
0294     struct dentry       *dbg;
0295 #endif
0296 };
0297
0298 static inline struct intel_th_device *
0299 to_intel_th_hub(struct intel_th_device *thdev)
0300 {
0301     if (thdev->type == INTEL_TH_SWITCH)
0302         return thdev;
0303     else if (thdev->type == INTEL_TH_OUTPUT)
0304         return to_intel_th_parent(thdev);
0305
0306     return to_intel_th(thdev)->hub;
0307 }
0308
0309 /*
0310  * Register windows
0311  */
0312 enum {
0313     /* Global Trace Hub (GTH) */
0314     REG_GTH_OFFSET      = 0x0000,
0315     REG_GTH_LENGTH      = 0x2000,
0316
0317     /* Timestamp counter unit (TSCU) */
0318     REG_TSCU_OFFSET     = 0x2000,
0319     REG_TSCU_LENGTH     = 0x1000,
0320
0321     REG_CTS_OFFSET      = 0x3000,
0322     REG_CTS_LENGTH      = 0x1000,
0323
0324     /* Software Trace Hub (STH) [0x4000..0x4fff] */
0325     REG_STH_OFFSET      = 0x4000,
0326     REG_STH_LENGTH      = 0x2000,
0327
0328     /* Memory Storage Unit (MSU) [0xa0000..0xa1fff] */
0329     REG_MSU_OFFSET      = 0xa0000,
0330     REG_MSU_LENGTH      = 0x02000,
0331
0332     /* Internal MSU trace buffer [0x80000..0x9ffff] */
0333     BUF_MSU_OFFSET      = 0x80000,
0334     BUF_MSU_LENGTH      = 0x20000,
0335
0336     /* PTI output == same window as GTH */
0337     REG_PTI_OFFSET      = REG_GTH_OFFSET,
0338     REG_PTI_LENGTH      = REG_GTH_LENGTH,
0339
0340     /* DCI Handler (DCIH) == some window as MSU */
0341     REG_DCIH_OFFSET     = REG_MSU_OFFSET,
0342     REG_DCIH_LENGTH     = REG_MSU_LENGTH,
0343 };
0344
0345 /*
0346  * Scratchpad bits: tell firmware and external debuggers
0347  * what we are up to.
0348  */
0349 enum {
0350     /* Memory is the primary destination */
0351     SCRPD_MEM_IS_PRIM_DEST      = BIT(0),
0352     /* XHCI DbC is the primary destination */
0353     SCRPD_DBC_IS_PRIM_DEST      = BIT(1),
0354     /* PTI is the primary destination */
0355     SCRPD_PTI_IS_PRIM_DEST      = BIT(2),
0356     /* BSSB is the primary destination */
0357     SCRPD_BSSB_IS_PRIM_DEST     = BIT(3),
0358     /* PTI is the alternate destination */
0359     SCRPD_PTI_IS_ALT_DEST       = BIT(4),
0360     /* BSSB is the alternate destination */
0361     SCRPD_BSSB_IS_ALT_DEST      = BIT(5),
0362     /* DeepSx exit occurred */
0363     SCRPD_DEEPSX_EXIT       = BIT(6),
0364     /* S4 exit occurred */
0365     SCRPD_S4_EXIT           = BIT(7),
0366     /* S5 exit occurred */
0367     SCRPD_S5_EXIT           = BIT(8),
0368     /* MSU controller 0/1 is enabled */
0369     SCRPD_MSC0_IS_ENABLED       = BIT(9),
0370     SCRPD_MSC1_IS_ENABLED       = BIT(10),
0371     /* Sx exit occurred */
0372     SCRPD_SX_EXIT           = BIT(11),
0373     /* Trigger Unit is enabled */
0374     SCRPD_TRIGGER_IS_ENABLED    = BIT(12),
0375     SCRPD_ODLA_IS_ENABLED       = BIT(13),
0376     SCRPD_SOCHAP_IS_ENABLED     = BIT(14),
0377     SCRPD_STH_IS_ENABLED        = BIT(15),
0378     SCRPD_DCIH_IS_ENABLED       = BIT(16),
0379     SCRPD_VER_IS_ENABLED        = BIT(17),
0380     /* External debugger is using Intel TH */
0381     SCRPD_DEBUGGER_IN_USE       = BIT(24),
0382 };
0383
0384 #endif