hwtracing/intel_th/gth.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Intel(R) Trace Hub Global Trace Hub (GTH) data structures
0004  *
0005  * Copyright (C) 2014-2015 Intel Corporation.
0006  */
0007
0008 #ifndef __INTEL_TH_GTH_H__
0009 #define __INTEL_TH_GTH_H__
0010
0011 /* Map output port parameter bits to symbolic names */
0012 #define TH_OUTPUT_PARM(name)            \
0013     TH_OUTPUT_ ## name
0014
0015 enum intel_th_output_parm {
0016     /* output port type */
0017     TH_OUTPUT_PARM(port),
0018     /* generate NULL packet */
0019     TH_OUTPUT_PARM(null),
0020     /* packet drop */
0021     TH_OUTPUT_PARM(drop),
0022     /* port in reset state */
0023     TH_OUTPUT_PARM(reset),
0024     /* flush out data */
0025     TH_OUTPUT_PARM(flush),
0026     /* mainenance packet frequency */
0027     TH_OUTPUT_PARM(smcfreq),
0028 };
0029
0030 /*
0031  * Register offsets
0032  */
0033 enum {
0034     REG_GTH_GTHOPT0     = 0x00, /* Output ports 0..3 config */
0035     REG_GTH_GTHOPT1     = 0x04, /* Output ports 4..7 config */
0036     REG_GTH_SWDEST0     = 0x08, /* Switching destination masters 0..7 */
0037     REG_GTH_GSWTDEST    = 0x88, /* Global sw trace destination */
0038     REG_GTH_SMCR0       = 0x9c, /* STP mainenance for ports 0/1 */
0039     REG_GTH_SMCR1       = 0xa0, /* STP mainenance for ports 2/3 */
0040     REG_GTH_SMCR2       = 0xa4, /* STP mainenance for ports 4/5 */
0041     REG_GTH_SMCR3       = 0xa8, /* STP mainenance for ports 6/7 */
0042     REG_GTH_SCR     = 0xc8, /* Source control (storeEn override) */
0043     REG_GTH_STAT        = 0xd4, /* GTH status */
0044     REG_GTH_SCR2        = 0xd8, /* Source control (force storeEn off) */
0045     REG_GTH_DESTOVR     = 0xdc, /* Destination override */
0046     REG_GTH_SCRPD0      = 0xe0, /* ScratchPad[0] */
0047     REG_GTH_SCRPD1      = 0xe4, /* ScratchPad[1] */
0048     REG_GTH_SCRPD2      = 0xe8, /* ScratchPad[2] */
0049     REG_GTH_SCRPD3      = 0xec, /* ScratchPad[3] */
0050     REG_TSCU_TSUCTRL    = 0x2000, /* TSCU control register */
0051     REG_TSCU_TSCUSTAT   = 0x2004, /* TSCU status register */
0052
0053     /* Common Capture Sequencer (CTS) registers */
0054     REG_CTS_C0S0_EN     = 0x30c0, /* clause_event_enable_c0s0 */
0055     REG_CTS_C0S0_ACT    = 0x3180, /* clause_action_control_c0s0 */
0056     REG_CTS_STAT        = 0x32a0, /* cts_status */
0057     REG_CTS_CTL     = 0x32a4, /* cts_control */
0058 };
0059
0060 /* waiting for Pipeline Empty bit(s) to assert for GTH */
0061 #define GTH_PLE_WAITLOOP_DEPTH  10000
0062
0063 #define TSUCTRL_CTCRESYNC   BIT(0)
0064 #define TSCUSTAT_CTCSYNCING BIT(1)
0065
0066 /* waiting for Trigger status to assert for CTS */
0067 #define CTS_TRIG_WAITLOOP_DEPTH 10000
0068
0069 #define CTS_EVENT_ENABLE_IF_ANYTHING    BIT(31)
0070 #define CTS_ACTION_CONTROL_STATE_OFF    27
0071 #define CTS_ACTION_CONTROL_SET_STATE(x) \
0072     (((x) & 0x1f) << CTS_ACTION_CONTROL_STATE_OFF)
0073 #define CTS_ACTION_CONTROL_TRIGGER  BIT(4)
0074
0075 #define CTS_STATE_IDLE          0x10u
0076
0077 #define CTS_CTL_SEQUENCER_ENABLE    BIT(0)
0078
0079 #endif /* __INTEL_TH_GTH_H__ */