hwtracing/coresight/coresight-tpiu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
0004  *
0005  * Description: CoreSight Trace Port Interface Unit driver
0006  */
0007
0008 #include <linux/atomic.h>
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/device.h>
0012 #include <linux/io.h>
0013 #include <linux/err.h>
0014 #include <linux/slab.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/coresight.h>
0017 #include <linux/amba/bus.h>
0018 #include <linux/clk.h>
0019
0020 #include "coresight-priv.h"
0021
0022 #define TPIU_SUPP_PORTSZ    0x000
0023 #define TPIU_CURR_PORTSZ    0x004
0024 #define TPIU_SUPP_TRIGMODES 0x100
0025 #define TPIU_TRIG_CNTRVAL   0x104
0026 #define TPIU_TRIG_MULT      0x108
0027 #define TPIU_SUPP_TESTPATM  0x200
0028 #define TPIU_CURR_TESTPATM  0x204
0029 #define TPIU_TEST_PATREPCNTR    0x208
0030 #define TPIU_FFSR       0x300
0031 #define TPIU_FFCR       0x304
0032 #define TPIU_FSYNC_CNTR     0x308
0033 #define TPIU_EXTCTL_INPORT  0x400
0034 #define TPIU_EXTCTL_OUTPORT 0x404
0035 #define TPIU_ITTRFLINACK    0xee4
0036 #define TPIU_ITTRFLIN       0xee8
0037 #define TPIU_ITATBDATA0     0xeec
0038 #define TPIU_ITATBCTR2      0xef0
0039 #define TPIU_ITATBCTR1      0xef4
0040 #define TPIU_ITATBCTR0      0xef8
0041
0042 /** register definition **/
0043 /* FFSR - 0x300 */
0044 #define FFSR_FT_STOPPED_BIT 1
0045 /* FFCR - 0x304 */
0046 #define FFCR_FON_MAN_BIT    6
0047 #define FFCR_FON_MAN        BIT(6)
0048 #define FFCR_STOP_FI        BIT(12)
0049
0050 DEFINE_CORESIGHT_DEVLIST(tpiu_devs, "tpiu");
0051
0052 /*
0053  * @base:   memory mapped base address for this component.
0054  * @atclk:  optional clock for the core parts of the TPIU.
0055  * @csdev:  component vitals needed by the framework.
0056  */
0057 struct tpiu_drvdata {
0058     void __iomem        *base;
0059     struct clk      *atclk;
0060     struct coresight_device *csdev;
0061 };
0062
0063 static void tpiu_enable_hw(struct csdev_access *csa)
0064 {
0065     CS_UNLOCK(csa->base);
0066
0067     /* TODO: fill this up */
0068
0069     CS_LOCK(csa->base);
0070 }
0071
0072 static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
0073 {
0074     tpiu_enable_hw(&csdev->access);
0075     atomic_inc(csdev->refcnt);
0076     dev_dbg(&csdev->dev, "TPIU enabled\n");
0077     return 0;
0078 }
0079
0080 static void tpiu_disable_hw(struct csdev_access *csa)
0081 {
0082     CS_UNLOCK(csa->base);
0083
0084     /* Clear formatter and stop on flush */
0085     csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
0086     /* Generate manual flush */
0087     csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
0088     /* Wait for flush to complete */
0089     coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
0090     /* Wait for formatter to stop */
0091     coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
0092
0093     CS_LOCK(csa->base);
0094 }
0095
0096 static int tpiu_disable(struct coresight_device *csdev)
0097 {
0098     if (atomic_dec_return(csdev->refcnt))
0099         return -EBUSY;
0100
0101     tpiu_disable_hw(&csdev->access);
0102
0103     dev_dbg(&csdev->dev, "TPIU disabled\n");
0104     return 0;
0105 }
0106
0107 static const struct coresight_ops_sink tpiu_sink_ops = {
0108     .enable     = tpiu_enable,
0109     .disable    = tpiu_disable,
0110 };
0111
0112 static const struct coresight_ops tpiu_cs_ops = {
0113     .sink_ops   = &tpiu_sink_ops,
0114 };
0115
0116 static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
0117 {
0118     int ret;
0119     void __iomem *base;
0120     struct device *dev = &adev->dev;
0121     struct coresight_platform_data *pdata = NULL;
0122     struct tpiu_drvdata *drvdata;
0123     struct resource *res = &adev->res;
0124     struct coresight_desc desc = { 0 };
0125
0126     desc.name = coresight_alloc_device_name(&tpiu_devs, dev);
0127     if (!desc.name)
0128         return -ENOMEM;
0129
0130     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
0131     if (!drvdata)
0132         return -ENOMEM;
0133
0134     drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
0135     if (!IS_ERR(drvdata->atclk)) {
0136         ret = clk_prepare_enable(drvdata->atclk);
0137         if (ret)
0138             return ret;
0139     }
0140     dev_set_drvdata(dev, drvdata);
0141
0142     /* Validity for the resource is already checked by the AMBA core */
0143     base = devm_ioremap_resource(dev, res);
0144     if (IS_ERR(base))
0145         return PTR_ERR(base);
0146
0147     drvdata->base = base;
0148     desc.access = CSDEV_ACCESS_IOMEM(base);
0149
0150     /* Disable tpiu to support older devices */
0151     tpiu_disable_hw(&desc.access);
0152
0153     pdata = coresight_get_platform_data(dev);
0154     if (IS_ERR(pdata))
0155         return PTR_ERR(pdata);
0156     dev->platform_data = pdata;
0157
0158     desc.type = CORESIGHT_DEV_TYPE_SINK;
0159     desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
0160     desc.ops = &tpiu_cs_ops;
0161     desc.pdata = pdata;
0162     desc.dev = dev;
0163     drvdata->csdev = coresight_register(&desc);
0164
0165     if (!IS_ERR(drvdata->csdev)) {
0166         pm_runtime_put(&adev->dev);
0167         return 0;
0168     }
0169
0170     return PTR_ERR(drvdata->csdev);
0171 }
0172
0173 static void tpiu_remove(struct amba_device *adev)
0174 {
0175     struct tpiu_drvdata *drvdata = dev_get_drvdata(&adev->dev);
0176
0177     coresight_unregister(drvdata->csdev);
0178 }
0179
0180 #ifdef CONFIG_PM
0181 static int tpiu_runtime_suspend(struct device *dev)
0182 {
0183     struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
0184
0185     if (drvdata && !IS_ERR(drvdata->atclk))
0186         clk_disable_unprepare(drvdata->atclk);
0187
0188     return 0;
0189 }
0190
0191 static int tpiu_runtime_resume(struct device *dev)
0192 {
0193     struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
0194
0195     if (drvdata && !IS_ERR(drvdata->atclk))
0196         clk_prepare_enable(drvdata->atclk);
0197
0198     return 0;
0199 }
0200 #endif
0201
0202 static const struct dev_pm_ops tpiu_dev_pm_ops = {
0203     SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL)
0204 };
0205
0206 static const struct amba_id tpiu_ids[] = {
0207     {
0208         .id = 0x000bb912,
0209         .mask   = 0x000fffff,
0210     },
0211     {
0212         .id = 0x0004b912,
0213         .mask   = 0x0007ffff,
0214     },
0215     {
0216         /* Coresight SoC-600 */
0217         .id = 0x000bb9e7,
0218         .mask   = 0x000fffff,
0219     },
0220     { 0, 0},
0221 };
0222
0223 MODULE_DEVICE_TABLE(amba, tpiu_ids);
0224
0225 static struct amba_driver tpiu_driver = {
0226     .drv = {
0227         .name   = "coresight-tpiu",
0228         .owner  = THIS_MODULE,
0229         .pm = &tpiu_dev_pm_ops,
0230         .suppress_bind_attrs = true,
0231     },
0232     .probe      = tpiu_probe,
0233     .remove         = tpiu_remove,
0234     .id_table   = tpiu_ids,
0235 };
0236
0237 module_amba_driver(tpiu_driver);
0238
0239 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
0240 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
0241 MODULE_DESCRIPTION("Arm CoreSight TPIU (Trace Port Interface Unit) driver");
0242 MODULE_LICENSE("GPL v2");