hwtracing/coresight/coresight-tmc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright(C) 2015 Linaro Limited. All rights reserved.
0004  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
0005  */
0006
0007 #ifndef _CORESIGHT_TMC_H
0008 #define _CORESIGHT_TMC_H
0009
0010 #include <linux/dma-mapping.h>
0011 #include <linux/idr.h>
0012 #include <linux/miscdevice.h>
0013 #include <linux/mutex.h>
0014 #include <linux/refcount.h>
0015
0016 #define TMC_RSZ         0x004
0017 #define TMC_STS         0x00c
0018 #define TMC_RRD         0x010
0019 #define TMC_RRP         0x014
0020 #define TMC_RWP         0x018
0021 #define TMC_TRG         0x01c
0022 #define TMC_CTL         0x020
0023 #define TMC_RWD         0x024
0024 #define TMC_MODE        0x028
0025 #define TMC_LBUFLEVEL       0x02c
0026 #define TMC_CBUFLEVEL       0x030
0027 #define TMC_BUFWM       0x034
0028 #define TMC_RRPHI       0x038
0029 #define TMC_RWPHI       0x03c
0030 #define TMC_AXICTL      0x110
0031 #define TMC_DBALO       0x118
0032 #define TMC_DBAHI       0x11c
0033 #define TMC_FFSR        0x300
0034 #define TMC_FFCR        0x304
0035 #define TMC_PSCR        0x308
0036 #define TMC_ITMISCOP0       0xee0
0037 #define TMC_ITTRFLIN        0xee8
0038 #define TMC_ITATBDATA0      0xeec
0039 #define TMC_ITATBCTR2       0xef0
0040 #define TMC_ITATBCTR1       0xef4
0041 #define TMC_ITATBCTR0       0xef8
0042 #define TMC_AUTHSTATUS      0xfb8
0043
0044 /* register description */
0045 /* TMC_CTL - 0x020 */
0046 #define TMC_CTL_CAPT_EN     BIT(0)
0047 /* TMC_STS - 0x00C */
0048 #define TMC_STS_TMCREADY_BIT    2
0049 #define TMC_STS_FULL        BIT(0)
0050 #define TMC_STS_TRIGGERED   BIT(1)
0051 #define TMC_STS_MEMERR      BIT(5)
0052 /*
0053  * TMC_AXICTL - 0x110
0054  *
0055  * TMC AXICTL format for SoC-400
0056  *  Bits [0-1]  : ProtCtrlBit0-1
0057  *  Bits [2-5]  : CacheCtrlBits 0-3 (AXCACHE)
0058  *  Bit  6      : Reserved
0059  *  Bit  7      : ScatterGatherMode
0060  *  Bits [8-11] : WrBurstLen
0061  *  Bits [12-31]    : Reserved.
0062  * TMC AXICTL format for SoC-600, as above except:
0063  *  Bits [2-5]  : AXI WCACHE
0064  *  Bits [16-19]    : AXI RCACHE
0065  *  Bits [20-31]    : Reserved
0066  */
0067 #define TMC_AXICTL_CLEAR_MASK 0xfbf
0068 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
0069
0070 #define TMC_AXICTL_PROT_CTL_B0  BIT(0)
0071 #define TMC_AXICTL_PROT_CTL_B1  BIT(1)
0072 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
0073 #define TMC_AXICTL_WR_BURST(v)  (((v) & 0xf) << 8)
0074 #define TMC_AXICTL_WR_BURST_16  0xf
0075 /* Write-back Read and Write-allocate */
0076 #define TMC_AXICTL_AXCACHE_OS   (0xf << 2)
0077 #define TMC_AXICTL_ARCACHE_OS   (0xf << 16)
0078
0079 /* TMC_FFCR - 0x304 */
0080 #define TMC_FFCR_FLUSHMAN_BIT   6
0081 #define TMC_FFCR_EN_FMT     BIT(0)
0082 #define TMC_FFCR_EN_TI      BIT(1)
0083 #define TMC_FFCR_FON_FLIN   BIT(4)
0084 #define TMC_FFCR_FON_TRIG_EVT   BIT(5)
0085 #define TMC_FFCR_TRIGON_TRIGIN  BIT(8)
0086 #define TMC_FFCR_STOP_ON_FLUSH  BIT(12)
0087
0088
0089 #define TMC_DEVID_NOSCAT    BIT(24)
0090
0091 #define TMC_DEVID_AXIAW_VALID   BIT(16)
0092 #define TMC_DEVID_AXIAW_SHIFT   17
0093 #define TMC_DEVID_AXIAW_MASK    0x7f
0094
0095 #define TMC_AUTH_NSID_MASK  GENMASK(1, 0)
0096
0097 enum tmc_config_type {
0098     TMC_CONFIG_TYPE_ETB,
0099     TMC_CONFIG_TYPE_ETR,
0100     TMC_CONFIG_TYPE_ETF,
0101 };
0102
0103 enum tmc_mode {
0104     TMC_MODE_CIRCULAR_BUFFER,
0105     TMC_MODE_SOFTWARE_FIFO,
0106     TMC_MODE_HARDWARE_FIFO,
0107 };
0108
0109 enum tmc_mem_intf_width {
0110     TMC_MEM_INTF_WIDTH_32BITS   = 1,
0111     TMC_MEM_INTF_WIDTH_64BITS   = 2,
0112     TMC_MEM_INTF_WIDTH_128BITS  = 4,
0113     TMC_MEM_INTF_WIDTH_256BITS  = 8,
0114 };
0115
0116 /* TMC ETR Capability bit definitions */
0117 #define TMC_ETR_SG          (0x1U << 0)
0118 /* ETR has separate read/write cache encodings */
0119 #define TMC_ETR_AXI_ARCACHE     (0x1U << 1)
0120 /*
0121  * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
0122  * retained when TMC leaves Disabled state, allowing us to continue
0123  * the tracing from a point where we stopped. This also implies that
0124  * the RRP/RWP/STS.Full should always be programmed to the correct
0125  * value. Unfortunately this is not advertised by the hardware,
0126  * so we have to rely on PID of the IP to detect the functionality.
0127  */
0128 #define TMC_ETR_SAVE_RESTORE        (0x1U << 2)
0129
0130 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
0131 #define CORESIGHT_SOC_600_ETR_CAPS  \
0132     (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
0133
0134 enum etr_mode {
0135     ETR_MODE_FLAT,      /* Uses contiguous flat buffer */
0136     ETR_MODE_ETR_SG,    /* Uses in-built TMC ETR SG mechanism */
0137     ETR_MODE_CATU,      /* Use SG mechanism in CATU */
0138 };
0139
0140 struct etr_buf_operations;
0141
0142 /**
0143  * struct etr_buf - Details of the buffer used by ETR
0144  * refcount ; Number of sources currently using this etr_buf.
0145  * @mode    : Mode of the ETR buffer, contiguous, Scatter Gather etc.
0146  * @full    : Trace data overflow
0147  * @size    : Size of the buffer.
0148  * @hwaddr  : Address to be programmed in the TMC:DBA{LO,HI}
0149  * @offset  : Offset of the trace data in the buffer for consumption.
0150  * @len     : Available trace data @buf (may round up to the beginning).
0151  * @ops     : ETR buffer operations for the mode.
0152  * @private : Backend specific information for the buf
0153  */
0154 struct etr_buf {
0155     refcount_t          refcount;
0156     enum etr_mode           mode;
0157     bool                full;
0158     ssize_t             size;
0159     dma_addr_t          hwaddr;
0160     unsigned long           offset;
0161     s64             len;
0162     const struct etr_buf_operations *ops;
0163     void                *private;
0164 };
0165
0166 /**
0167  * struct tmc_drvdata - specifics associated to an TMC component
0168  * @base:   memory mapped base address for this component.
0169  * @csdev:  component vitals needed by the framework.
0170  * @miscdev:    specifics to handle "/dev/xyz.tmc" entry.
0171  * @spinlock:   only one at a time pls.
0172  * @pid:    Process ID of the process being monitored by the session
0173  *      that is using this component.
0174  * @buf:    Snapshot of the trace data for ETF/ETB.
0175  * @etr_buf:    details of buffer used in TMC-ETR
0176  * @len:    size of the available trace for ETF/ETB.
0177  * @size:   trace buffer size for this TMC (common for all modes).
0178  * @max_burst_size: The maximum burst size that can be initiated by
0179  *      TMC-ETR on AXI bus.
0180  * @mode:   how this TMC is being used.
0181  * @config_type: TMC variant, must be of type @tmc_config_type.
0182  * @memwidth:   width of the memory interface databus, in bytes.
0183  * @trigger_cntr: amount of words to store after a trigger.
0184  * @etr_caps:   Bitmask of capabilities of the TMC ETR, inferred from the
0185  *      device configuration register (DEVID)
0186  * @idr:    Holds etr_bufs allocated for this ETR.
0187  * @idr_mutex:  Access serialisation for idr.
0188  * @sysfs_buf:  SYSFS buffer for ETR.
0189  * @perf_buf:   PERF buffer for ETR.
0190  */
0191 struct tmc_drvdata {
0192     void __iomem        *base;
0193     struct coresight_device *csdev;
0194     struct miscdevice   miscdev;
0195     spinlock_t      spinlock;
0196     pid_t           pid;
0197     bool            reading;
0198     union {
0199         char        *buf;       /* TMC ETB */
0200         struct etr_buf  *etr_buf;   /* TMC ETR */
0201     };
0202     u32         len;
0203     u32         size;
0204     u32         max_burst_size;
0205     u32         mode;
0206     enum tmc_config_type    config_type;
0207     enum tmc_mem_intf_width memwidth;
0208     u32         trigger_cntr;
0209     u32         etr_caps;
0210     struct idr      idr;
0211     struct mutex        idr_mutex;
0212     struct etr_buf      *sysfs_buf;
0213     struct etr_buf      *perf_buf;
0214 };
0215
0216 struct etr_buf_operations {
0217     int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
0218              int node, void **pages);
0219     void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
0220     ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
0221                 char **bufpp);
0222     void (*free)(struct etr_buf *etr_buf);
0223 };
0224
0225 /**
0226  * struct tmc_pages - Collection of pages used for SG.
0227  * @nr_pages:       Number of pages in the list.
0228  * @daddrs:     Array of DMA'able page address.
0229  * @pages:      Array pages for the buffer.
0230  */
0231 struct tmc_pages {
0232     int nr_pages;
0233     dma_addr_t  *daddrs;
0234     struct page **pages;
0235 };
0236
0237 /*
0238  * struct tmc_sg_table - Generic SG table for TMC
0239  * @dev:        Device for DMA allocations
0240  * @table_vaddr:    Contiguous Virtual address for PageTable
0241  * @data_vaddr:     Contiguous Virtual address for Data Buffer
0242  * @table_daddr:    DMA address of the PageTable base
0243  * @node:       Node for Page allocations
0244  * @table_pages:    List of pages & dma address for Table
0245  * @data_pages:     List of pages & dma address for Data
0246  */
0247 struct tmc_sg_table {
0248     struct device *dev;
0249     void *table_vaddr;
0250     void *data_vaddr;
0251     dma_addr_t table_daddr;
0252     int node;
0253     struct tmc_pages table_pages;
0254     struct tmc_pages data_pages;
0255 };
0256
0257 /* Generic functions */
0258 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
0259 void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
0260 void tmc_enable_hw(struct tmc_drvdata *drvdata);
0261 void tmc_disable_hw(struct tmc_drvdata *drvdata);
0262 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
0263
0264 /* ETB/ETF functions */
0265 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
0266 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
0267 extern const struct coresight_ops tmc_etb_cs_ops;
0268 extern const struct coresight_ops tmc_etf_cs_ops;
0269
0270 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
0271                 loff_t pos, size_t len, char **bufpp);
0272 /* ETR functions */
0273 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
0274 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
0275 void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
0276 extern const struct coresight_ops tmc_etr_cs_ops;
0277 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
0278                 loff_t pos, size_t len, char **bufpp);
0279
0280
0281 #define TMC_REG_PAIR(name, lo_off, hi_off)              \
0282 static inline u64                           \
0283 tmc_read_##name(struct tmc_drvdata *drvdata)                \
0284 {                                   \
0285     return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);  \
0286 }                                   \
0287 static inline void                          \
0288 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)          \
0289 {                                   \
0290     coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);   \
0291 }
0292
0293 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
0294 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
0295 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
0296
0297 /* Initialise the caps from unadvertised static capabilities of the device */
0298 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
0299 {
0300     WARN_ON(drvdata->etr_caps);
0301     drvdata->etr_caps = dev_caps;
0302 }
0303
0304 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
0305 {
0306     drvdata->etr_caps |= cap;
0307 }
0308
0309 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
0310 {
0311     return !!(drvdata->etr_caps & cap);
0312 }
0313
0314 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,
0315                     int node,
0316                     int nr_tpages,
0317                     int nr_dpages,
0318                     void **pages);
0319 void tmc_free_sg_table(struct tmc_sg_table *sg_table);
0320 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table);
0321 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
0322                   u64 offset, u64 size);
0323 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,
0324                   u64 offset, size_t len, char **bufpp);
0325 static inline unsigned long
0326 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
0327 {
0328     return sg_table->data_pages.nr_pages << PAGE_SHIFT;
0329 }
0330
0331 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
0332
0333 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
0334 void tmc_etr_remove_catu_ops(void);
0335
0336 #endif