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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
0003  *
0004  * Description: CoreSight Trace Memory Controller driver
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/types.h>
0010 #include <linux/device.h>
0011 #include <linux/idr.h>
0012 #include <linux/io.h>
0013 #include <linux/err.h>
0014 #include <linux/fs.h>
0015 #include <linux/miscdevice.h>
0016 #include <linux/mutex.h>
0017 #include <linux/property.h>
0018 #include <linux/uaccess.h>
0019 #include <linux/slab.h>
0020 #include <linux/dma-mapping.h>
0021 #include <linux/spinlock.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/of.h>
0024 #include <linux/coresight.h>
0025 #include <linux/amba/bus.h>
0026 
0027 #include "coresight-priv.h"
0028 #include "coresight-tmc.h"
0029 
0030 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
0031 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
0032 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
0033 
0034 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
0035 {
0036     struct coresight_device *csdev = drvdata->csdev;
0037     struct csdev_access *csa = &csdev->access;
0038 
0039     /* Ensure formatter, unformatter and hardware fifo are empty */
0040     if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
0041         dev_err(&csdev->dev,
0042             "timeout while waiting for TMC to be Ready\n");
0043     }
0044 }
0045 
0046 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
0047 {
0048     struct coresight_device *csdev = drvdata->csdev;
0049     struct csdev_access *csa = &csdev->access;
0050     u32 ffcr;
0051 
0052     ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
0053     ffcr |= TMC_FFCR_STOP_ON_FLUSH;
0054     writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
0055     ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
0056     writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
0057     /* Ensure flush completes */
0058     if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
0059         dev_err(&csdev->dev,
0060         "timeout while waiting for completion of Manual Flush\n");
0061     }
0062 
0063     tmc_wait_for_tmcready(drvdata);
0064 }
0065 
0066 void tmc_enable_hw(struct tmc_drvdata *drvdata)
0067 {
0068     writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
0069 }
0070 
0071 void tmc_disable_hw(struct tmc_drvdata *drvdata)
0072 {
0073     writel_relaxed(0x0, drvdata->base + TMC_CTL);
0074 }
0075 
0076 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
0077 {
0078     u32 mask = 0;
0079 
0080     /*
0081      * When moving RRP or an offset address forward, the new values must
0082      * be byte-address aligned to the width of the trace memory databus
0083      * _and_ to a frame boundary (16 byte), whichever is the biggest. For
0084      * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
0085      * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
0086      * be 0s.
0087      */
0088     switch (drvdata->memwidth) {
0089     case TMC_MEM_INTF_WIDTH_32BITS:
0090     case TMC_MEM_INTF_WIDTH_64BITS:
0091     case TMC_MEM_INTF_WIDTH_128BITS:
0092         mask = GENMASK(31, 4);
0093         break;
0094     case TMC_MEM_INTF_WIDTH_256BITS:
0095         mask = GENMASK(31, 5);
0096         break;
0097     }
0098 
0099     return mask;
0100 }
0101 
0102 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
0103 {
0104     int ret = 0;
0105 
0106     switch (drvdata->config_type) {
0107     case TMC_CONFIG_TYPE_ETB:
0108     case TMC_CONFIG_TYPE_ETF:
0109         ret = tmc_read_prepare_etb(drvdata);
0110         break;
0111     case TMC_CONFIG_TYPE_ETR:
0112         ret = tmc_read_prepare_etr(drvdata);
0113         break;
0114     default:
0115         ret = -EINVAL;
0116     }
0117 
0118     if (!ret)
0119         dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
0120 
0121     return ret;
0122 }
0123 
0124 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
0125 {
0126     int ret = 0;
0127 
0128     switch (drvdata->config_type) {
0129     case TMC_CONFIG_TYPE_ETB:
0130     case TMC_CONFIG_TYPE_ETF:
0131         ret = tmc_read_unprepare_etb(drvdata);
0132         break;
0133     case TMC_CONFIG_TYPE_ETR:
0134         ret = tmc_read_unprepare_etr(drvdata);
0135         break;
0136     default:
0137         ret = -EINVAL;
0138     }
0139 
0140     if (!ret)
0141         dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
0142 
0143     return ret;
0144 }
0145 
0146 static int tmc_open(struct inode *inode, struct file *file)
0147 {
0148     int ret;
0149     struct tmc_drvdata *drvdata = container_of(file->private_data,
0150                            struct tmc_drvdata, miscdev);
0151 
0152     ret = tmc_read_prepare(drvdata);
0153     if (ret)
0154         return ret;
0155 
0156     nonseekable_open(inode, file);
0157 
0158     dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
0159     return 0;
0160 }
0161 
0162 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
0163                       loff_t pos, size_t len, char **bufpp)
0164 {
0165     switch (drvdata->config_type) {
0166     case TMC_CONFIG_TYPE_ETB:
0167     case TMC_CONFIG_TYPE_ETF:
0168         return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
0169     case TMC_CONFIG_TYPE_ETR:
0170         return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
0171     }
0172 
0173     return -EINVAL;
0174 }
0175 
0176 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
0177             loff_t *ppos)
0178 {
0179     char *bufp;
0180     ssize_t actual;
0181     struct tmc_drvdata *drvdata = container_of(file->private_data,
0182                            struct tmc_drvdata, miscdev);
0183     actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
0184     if (actual <= 0)
0185         return 0;
0186 
0187     if (copy_to_user(data, bufp, actual)) {
0188         dev_dbg(&drvdata->csdev->dev,
0189             "%s: copy_to_user failed\n", __func__);
0190         return -EFAULT;
0191     }
0192 
0193     *ppos += actual;
0194     dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
0195 
0196     return actual;
0197 }
0198 
0199 static int tmc_release(struct inode *inode, struct file *file)
0200 {
0201     int ret;
0202     struct tmc_drvdata *drvdata = container_of(file->private_data,
0203                            struct tmc_drvdata, miscdev);
0204 
0205     ret = tmc_read_unprepare(drvdata);
0206     if (ret)
0207         return ret;
0208 
0209     dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
0210     return 0;
0211 }
0212 
0213 static const struct file_operations tmc_fops = {
0214     .owner      = THIS_MODULE,
0215     .open       = tmc_open,
0216     .read       = tmc_read,
0217     .release    = tmc_release,
0218     .llseek     = no_llseek,
0219 };
0220 
0221 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
0222 {
0223     enum tmc_mem_intf_width memwidth;
0224 
0225     /*
0226      * Excerpt from the TRM:
0227      *
0228      * DEVID::MEMWIDTH[10:8]
0229      * 0x2 Memory interface databus is 32 bits wide.
0230      * 0x3 Memory interface databus is 64 bits wide.
0231      * 0x4 Memory interface databus is 128 bits wide.
0232      * 0x5 Memory interface databus is 256 bits wide.
0233      */
0234     switch (BMVAL(devid, 8, 10)) {
0235     case 0x2:
0236         memwidth = TMC_MEM_INTF_WIDTH_32BITS;
0237         break;
0238     case 0x3:
0239         memwidth = TMC_MEM_INTF_WIDTH_64BITS;
0240         break;
0241     case 0x4:
0242         memwidth = TMC_MEM_INTF_WIDTH_128BITS;
0243         break;
0244     case 0x5:
0245         memwidth = TMC_MEM_INTF_WIDTH_256BITS;
0246         break;
0247     default:
0248         memwidth = 0;
0249     }
0250 
0251     return memwidth;
0252 }
0253 
0254 #define coresight_tmc_reg(name, offset)         \
0255     coresight_simple_reg32(struct tmc_drvdata, name, offset)
0256 #define coresight_tmc_reg64(name, lo_off, hi_off)   \
0257     coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
0258 
0259 coresight_tmc_reg(rsz, TMC_RSZ);
0260 coresight_tmc_reg(sts, TMC_STS);
0261 coresight_tmc_reg(trg, TMC_TRG);
0262 coresight_tmc_reg(ctl, TMC_CTL);
0263 coresight_tmc_reg(ffsr, TMC_FFSR);
0264 coresight_tmc_reg(ffcr, TMC_FFCR);
0265 coresight_tmc_reg(mode, TMC_MODE);
0266 coresight_tmc_reg(pscr, TMC_PSCR);
0267 coresight_tmc_reg(axictl, TMC_AXICTL);
0268 coresight_tmc_reg(authstatus, TMC_AUTHSTATUS);
0269 coresight_tmc_reg(devid, CORESIGHT_DEVID);
0270 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
0271 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
0272 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
0273 
0274 static struct attribute *coresight_tmc_mgmt_attrs[] = {
0275     &dev_attr_rsz.attr,
0276     &dev_attr_sts.attr,
0277     &dev_attr_rrp.attr,
0278     &dev_attr_rwp.attr,
0279     &dev_attr_trg.attr,
0280     &dev_attr_ctl.attr,
0281     &dev_attr_ffsr.attr,
0282     &dev_attr_ffcr.attr,
0283     &dev_attr_mode.attr,
0284     &dev_attr_pscr.attr,
0285     &dev_attr_devid.attr,
0286     &dev_attr_dba.attr,
0287     &dev_attr_axictl.attr,
0288     &dev_attr_authstatus.attr,
0289     NULL,
0290 };
0291 
0292 static ssize_t trigger_cntr_show(struct device *dev,
0293                  struct device_attribute *attr, char *buf)
0294 {
0295     struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
0296     unsigned long val = drvdata->trigger_cntr;
0297 
0298     return sprintf(buf, "%#lx\n", val);
0299 }
0300 
0301 static ssize_t trigger_cntr_store(struct device *dev,
0302                  struct device_attribute *attr,
0303                  const char *buf, size_t size)
0304 {
0305     int ret;
0306     unsigned long val;
0307     struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
0308 
0309     ret = kstrtoul(buf, 16, &val);
0310     if (ret)
0311         return ret;
0312 
0313     drvdata->trigger_cntr = val;
0314     return size;
0315 }
0316 static DEVICE_ATTR_RW(trigger_cntr);
0317 
0318 static ssize_t buffer_size_show(struct device *dev,
0319                 struct device_attribute *attr, char *buf)
0320 {
0321     struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
0322 
0323     return sprintf(buf, "%#x\n", drvdata->size);
0324 }
0325 
0326 static ssize_t buffer_size_store(struct device *dev,
0327                  struct device_attribute *attr,
0328                  const char *buf, size_t size)
0329 {
0330     int ret;
0331     unsigned long val;
0332     struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
0333 
0334     /* Only permitted for TMC-ETRs */
0335     if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
0336         return -EPERM;
0337 
0338     ret = kstrtoul(buf, 0, &val);
0339     if (ret)
0340         return ret;
0341     /* The buffer size should be page aligned */
0342     if (val & (PAGE_SIZE - 1))
0343         return -EINVAL;
0344     drvdata->size = val;
0345     return size;
0346 }
0347 
0348 static DEVICE_ATTR_RW(buffer_size);
0349 
0350 static struct attribute *coresight_tmc_attrs[] = {
0351     &dev_attr_trigger_cntr.attr,
0352     &dev_attr_buffer_size.attr,
0353     NULL,
0354 };
0355 
0356 static const struct attribute_group coresight_tmc_group = {
0357     .attrs = coresight_tmc_attrs,
0358 };
0359 
0360 static const struct attribute_group coresight_tmc_mgmt_group = {
0361     .attrs = coresight_tmc_mgmt_attrs,
0362     .name = "mgmt",
0363 };
0364 
0365 static const struct attribute_group *coresight_tmc_groups[] = {
0366     &coresight_tmc_group,
0367     &coresight_tmc_mgmt_group,
0368     NULL,
0369 };
0370 
0371 static inline bool tmc_etr_can_use_sg(struct device *dev)
0372 {
0373     return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
0374 }
0375 
0376 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
0377 {
0378     u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
0379 
0380     return (auth & TMC_AUTH_NSID_MASK) == 0x3;
0381 }
0382 
0383 /* Detect and initialise the capabilities of a TMC ETR */
0384 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
0385 {
0386     int rc;
0387     u32 dma_mask = 0;
0388     struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
0389 
0390     if (!tmc_etr_has_non_secure_access(drvdata))
0391         return -EACCES;
0392 
0393     /* Set the unadvertised capabilities */
0394     tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
0395 
0396     if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
0397         tmc_etr_set_cap(drvdata, TMC_ETR_SG);
0398 
0399     /* Check if the AXI address width is available */
0400     if (devid & TMC_DEVID_AXIAW_VALID)
0401         dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
0402                 TMC_DEVID_AXIAW_MASK);
0403 
0404     /*
0405      * Unless specified in the device configuration, ETR uses a 40-bit
0406      * AXI master in place of the embedded SRAM of ETB/ETF.
0407      */
0408     switch (dma_mask) {
0409     case 32:
0410     case 40:
0411     case 44:
0412     case 48:
0413     case 52:
0414         dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
0415         break;
0416     default:
0417         dma_mask = 40;
0418     }
0419 
0420     rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
0421     if (rc)
0422         dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
0423     return rc;
0424 }
0425 
0426 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
0427 {
0428     u32 size;
0429 
0430     if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
0431         size = SZ_1M;
0432     return size;
0433 }
0434 
0435 static u32 tmc_etr_get_max_burst_size(struct device *dev)
0436 {
0437     u32 burst_size;
0438 
0439     if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size",
0440                      &burst_size))
0441         return TMC_AXICTL_WR_BURST_16;
0442 
0443     /* Only permissible values are 0 to 15 */
0444     if (burst_size > 0xF)
0445         burst_size = TMC_AXICTL_WR_BURST_16;
0446 
0447     return burst_size;
0448 }
0449 
0450 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
0451 {
0452     int ret = 0;
0453     u32 devid;
0454     void __iomem *base;
0455     struct device *dev = &adev->dev;
0456     struct coresight_platform_data *pdata = NULL;
0457     struct tmc_drvdata *drvdata;
0458     struct resource *res = &adev->res;
0459     struct coresight_desc desc = { 0 };
0460     struct coresight_dev_list *dev_list = NULL;
0461 
0462     ret = -ENOMEM;
0463     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
0464     if (!drvdata)
0465         goto out;
0466 
0467     dev_set_drvdata(dev, drvdata);
0468 
0469     /* Validity for the resource is already checked by the AMBA core */
0470     base = devm_ioremap_resource(dev, res);
0471     if (IS_ERR(base)) {
0472         ret = PTR_ERR(base);
0473         goto out;
0474     }
0475 
0476     drvdata->base = base;
0477     desc.access = CSDEV_ACCESS_IOMEM(base);
0478 
0479     spin_lock_init(&drvdata->spinlock);
0480 
0481     devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
0482     drvdata->config_type = BMVAL(devid, 6, 7);
0483     drvdata->memwidth = tmc_get_memwidth(devid);
0484     /* This device is not associated with a session */
0485     drvdata->pid = -1;
0486 
0487     if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
0488         drvdata->size = tmc_etr_get_default_buffer_size(dev);
0489         drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev);
0490     } else {
0491         drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
0492     }
0493 
0494     desc.dev = dev;
0495     desc.groups = coresight_tmc_groups;
0496 
0497     switch (drvdata->config_type) {
0498     case TMC_CONFIG_TYPE_ETB:
0499         desc.type = CORESIGHT_DEV_TYPE_SINK;
0500         desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
0501         desc.ops = &tmc_etb_cs_ops;
0502         dev_list = &etb_devs;
0503         break;
0504     case TMC_CONFIG_TYPE_ETR:
0505         desc.type = CORESIGHT_DEV_TYPE_SINK;
0506         desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM;
0507         desc.ops = &tmc_etr_cs_ops;
0508         ret = tmc_etr_setup_caps(dev, devid,
0509                      coresight_get_uci_data(id));
0510         if (ret)
0511             goto out;
0512         idr_init(&drvdata->idr);
0513         mutex_init(&drvdata->idr_mutex);
0514         dev_list = &etr_devs;
0515         break;
0516     case TMC_CONFIG_TYPE_ETF:
0517         desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
0518         desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
0519         desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
0520         desc.ops = &tmc_etf_cs_ops;
0521         dev_list = &etf_devs;
0522         break;
0523     default:
0524         pr_err("%s: Unsupported TMC config\n", desc.name);
0525         ret = -EINVAL;
0526         goto out;
0527     }
0528 
0529     desc.name = coresight_alloc_device_name(dev_list, dev);
0530     if (!desc.name) {
0531         ret = -ENOMEM;
0532         goto out;
0533     }
0534 
0535     pdata = coresight_get_platform_data(dev);
0536     if (IS_ERR(pdata)) {
0537         ret = PTR_ERR(pdata);
0538         goto out;
0539     }
0540     adev->dev.platform_data = pdata;
0541     desc.pdata = pdata;
0542 
0543     drvdata->csdev = coresight_register(&desc);
0544     if (IS_ERR(drvdata->csdev)) {
0545         ret = PTR_ERR(drvdata->csdev);
0546         goto out;
0547     }
0548 
0549     drvdata->miscdev.name = desc.name;
0550     drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
0551     drvdata->miscdev.fops = &tmc_fops;
0552     ret = misc_register(&drvdata->miscdev);
0553     if (ret)
0554         coresight_unregister(drvdata->csdev);
0555     else
0556         pm_runtime_put(&adev->dev);
0557 out:
0558     return ret;
0559 }
0560 
0561 static void tmc_shutdown(struct amba_device *adev)
0562 {
0563     unsigned long flags;
0564     struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
0565 
0566     spin_lock_irqsave(&drvdata->spinlock, flags);
0567 
0568     if (drvdata->mode == CS_MODE_DISABLED)
0569         goto out;
0570 
0571     if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
0572         tmc_etr_disable_hw(drvdata);
0573 
0574     /*
0575      * We do not care about coresight unregister here unlike remove
0576      * callback which is required for making coresight modular since
0577      * the system is going down after this.
0578      */
0579 out:
0580     spin_unlock_irqrestore(&drvdata->spinlock, flags);
0581 }
0582 
0583 static void tmc_remove(struct amba_device *adev)
0584 {
0585     struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev);
0586 
0587     /*
0588      * Since misc_open() holds a refcount on the f_ops, which is
0589      * etb fops in this case, device is there until last file
0590      * handler to this device is closed.
0591      */
0592     misc_deregister(&drvdata->miscdev);
0593     coresight_unregister(drvdata->csdev);
0594 }
0595 
0596 static const struct amba_id tmc_ids[] = {
0597     CS_AMBA_ID(0x000bb961),
0598     /* Coresight SoC 600 TMC-ETR/ETS */
0599     CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
0600     /* Coresight SoC 600 TMC-ETB */
0601     CS_AMBA_ID(0x000bb9e9),
0602     /* Coresight SoC 600 TMC-ETF */
0603     CS_AMBA_ID(0x000bb9ea),
0604     { 0, 0},
0605 };
0606 
0607 MODULE_DEVICE_TABLE(amba, tmc_ids);
0608 
0609 static struct amba_driver tmc_driver = {
0610     .drv = {
0611         .name   = "coresight-tmc",
0612         .owner  = THIS_MODULE,
0613         .suppress_bind_attrs = true,
0614     },
0615     .probe      = tmc_probe,
0616     .shutdown   = tmc_shutdown,
0617     .remove     = tmc_remove,
0618     .id_table   = tmc_ids,
0619 };
0620 
0621 module_amba_driver(tmc_driver);
0622 
0623 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
0624 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver");
0625 MODULE_LICENSE("GPL v2");
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