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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
0004  *
0005  * Description: CoreSight System Trace Macrocell driver
0006  *
0007  * Initial implementation by Pratik Patel
0008  * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
0009  *
0010  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
0011  * framework by Mathieu Poirier
0012  * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
0013  *
0014  * Guaranteed timing and support for various packet type coming from the
0015  * generic STM API by Chunyan Zhang
0016  * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
0017  */
0018 #include <asm/local.h>
0019 #include <linux/acpi.h>
0020 #include <linux/amba/bus.h>
0021 #include <linux/bitmap.h>
0022 #include <linux/clk.h>
0023 #include <linux/coresight.h>
0024 #include <linux/coresight-stm.h>
0025 #include <linux/err.h>
0026 #include <linux/kernel.h>
0027 #include <linux/moduleparam.h>
0028 #include <linux/of_address.h>
0029 #include <linux/perf_event.h>
0030 #include <linux/pm_runtime.h>
0031 #include <linux/stm.h>
0032 
0033 #include "coresight-priv.h"
0034 
0035 #define STMDMASTARTR            0xc04
0036 #define STMDMASTOPR         0xc08
0037 #define STMDMASTATR         0xc0c
0038 #define STMDMACTLR          0xc10
0039 #define STMDMAIDR           0xcfc
0040 #define STMHEER             0xd00
0041 #define STMHETER            0xd20
0042 #define STMHEBSR            0xd60
0043 #define STMHEMCR            0xd64
0044 #define STMHEMASTR          0xdf4
0045 #define STMHEFEAT1R         0xdf8
0046 #define STMHEIDR            0xdfc
0047 #define STMSPER             0xe00
0048 #define STMSPTER            0xe20
0049 #define STMPRIVMASKR            0xe40
0050 #define STMSPSCR            0xe60
0051 #define STMSPMSCR           0xe64
0052 #define STMSPOVERRIDER          0xe68
0053 #define STMSPMOVERRIDER         0xe6c
0054 #define STMSPTRIGCSR            0xe70
0055 #define STMTCSR             0xe80
0056 #define STMTSSTIMR          0xe84
0057 #define STMTSFREQR          0xe8c
0058 #define STMSYNCR            0xe90
0059 #define STMAUXCR            0xe94
0060 #define STMSPFEAT1R         0xea0
0061 #define STMSPFEAT2R         0xea4
0062 #define STMSPFEAT3R         0xea8
0063 #define STMITTRIGGER            0xee8
0064 #define STMITATBDATA0           0xeec
0065 #define STMITATBCTR2            0xef0
0066 #define STMITATBID          0xef4
0067 #define STMITATBCTR0            0xef8
0068 
0069 #define STM_32_CHANNEL          32
0070 #define BYTES_PER_CHANNEL       256
0071 #define STM_TRACE_BUF_SIZE      4096
0072 #define STM_SW_MASTER_END       127
0073 
0074 /* Register bit definition */
0075 #define STMTCSR_BUSY_BIT        23
0076 /* Reserve the first 10 channels for kernel usage */
0077 #define STM_CHANNEL_OFFSET      0
0078 
0079 enum stm_pkt_type {
0080     STM_PKT_TYPE_DATA   = 0x98,
0081     STM_PKT_TYPE_FLAG   = 0xE8,
0082     STM_PKT_TYPE_TRIG   = 0xF8,
0083 };
0084 
0085 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
0086                     (ch * BYTES_PER_CHANNEL))
0087 #define stm_channel_off(type, opts) (type & ~opts)
0088 
0089 static int boot_nr_channel;
0090 
0091 /*
0092  * Not really modular but using module_param is the easiest way to
0093  * remain consistent with existing use cases for now.
0094  */
0095 module_param_named(
0096     boot_nr_channel, boot_nr_channel, int, S_IRUGO
0097 );
0098 
0099 /*
0100  * struct channel_space - central management entity for extended ports
0101  * @base:       memory mapped base address where channels start.
0102  * @phys:       physical base address of channel region.
0103  * @guaraneed:      is the channel delivery guaranteed.
0104  */
0105 struct channel_space {
0106     void __iomem        *base;
0107     phys_addr_t     phys;
0108     unsigned long       *guaranteed;
0109 };
0110 
0111 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
0112 
0113 /**
0114  * struct stm_drvdata - specifics associated to an STM component
0115  * @base:       memory mapped base address for this component.
0116  * @atclk:      optional clock for the core parts of the STM.
0117  * @csdev:      component vitals needed by the framework.
0118  * @spinlock:       only one at a time pls.
0119  * @chs:        the channels accociated to this STM.
0120  * @stm:        structure associated to the generic STM interface.
0121  * @mode:       this tracer's mode, i.e sysFS, or disabled.
0122  * @traceid:        value of the current ID for this component.
0123  * @write_bytes:    Maximus bytes this STM can write at a time.
0124  * @stmsper:        settings for register STMSPER.
0125  * @stmspscr:       settings for register STMSPSCR.
0126  * @numsp:      the total number of stimulus port support by this STM.
0127  * @stmheer:        settings for register STMHEER.
0128  * @stmheter:       settings for register STMHETER.
0129  * @stmhebsr:       settings for register STMHEBSR.
0130  */
0131 struct stm_drvdata {
0132     void __iomem        *base;
0133     struct clk      *atclk;
0134     struct coresight_device *csdev;
0135     spinlock_t      spinlock;
0136     struct channel_space    chs;
0137     struct stm_data     stm;
0138     local_t         mode;
0139     u8          traceid;
0140     u32         write_bytes;
0141     u32         stmsper;
0142     u32         stmspscr;
0143     u32         numsp;
0144     u32         stmheer;
0145     u32         stmheter;
0146     u32         stmhebsr;
0147 };
0148 
0149 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
0150 {
0151     CS_UNLOCK(drvdata->base);
0152 
0153     writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
0154     writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
0155     writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
0156     writel_relaxed(0x01 |   /* Enable HW event tracing */
0157                0x04,    /* Error detection on event tracing */
0158                drvdata->base + STMHEMCR);
0159 
0160     CS_LOCK(drvdata->base);
0161 }
0162 
0163 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
0164 {
0165     CS_UNLOCK(drvdata->base);
0166     /* ATB trigger enable on direct writes to TRIG locations */
0167     writel_relaxed(0x10,
0168                drvdata->base + STMSPTRIGCSR);
0169     writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
0170     writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
0171 
0172     CS_LOCK(drvdata->base);
0173 }
0174 
0175 static void stm_enable_hw(struct stm_drvdata *drvdata)
0176 {
0177     if (drvdata->stmheer)
0178         stm_hwevent_enable_hw(drvdata);
0179 
0180     stm_port_enable_hw(drvdata);
0181 
0182     CS_UNLOCK(drvdata->base);
0183 
0184     /* 4096 byte between synchronisation packets */
0185     writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
0186     writel_relaxed((drvdata->traceid << 16 | /* trace id */
0187             0x02 |           /* timestamp enable */
0188             0x01),           /* global STM enable */
0189             drvdata->base + STMTCSR);
0190 
0191     CS_LOCK(drvdata->base);
0192 }
0193 
0194 static int stm_enable(struct coresight_device *csdev,
0195               struct perf_event *event, u32 mode)
0196 {
0197     u32 val;
0198     struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0199 
0200     if (mode != CS_MODE_SYSFS)
0201         return -EINVAL;
0202 
0203     val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
0204 
0205     /* Someone is already using the tracer */
0206     if (val)
0207         return -EBUSY;
0208 
0209     pm_runtime_get_sync(csdev->dev.parent);
0210 
0211     spin_lock(&drvdata->spinlock);
0212     stm_enable_hw(drvdata);
0213     spin_unlock(&drvdata->spinlock);
0214 
0215     dev_dbg(&csdev->dev, "STM tracing enabled\n");
0216     return 0;
0217 }
0218 
0219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
0220 {
0221     CS_UNLOCK(drvdata->base);
0222 
0223     writel_relaxed(0x0, drvdata->base + STMHEMCR);
0224     writel_relaxed(0x0, drvdata->base + STMHEER);
0225     writel_relaxed(0x0, drvdata->base + STMHETER);
0226 
0227     CS_LOCK(drvdata->base);
0228 }
0229 
0230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
0231 {
0232     CS_UNLOCK(drvdata->base);
0233 
0234     writel_relaxed(0x0, drvdata->base + STMSPER);
0235     writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
0236 
0237     CS_LOCK(drvdata->base);
0238 }
0239 
0240 static void stm_disable_hw(struct stm_drvdata *drvdata)
0241 {
0242     u32 val;
0243 
0244     CS_UNLOCK(drvdata->base);
0245 
0246     val = readl_relaxed(drvdata->base + STMTCSR);
0247     val &= ~0x1; /* clear global STM enable [0] */
0248     writel_relaxed(val, drvdata->base + STMTCSR);
0249 
0250     CS_LOCK(drvdata->base);
0251 
0252     stm_port_disable_hw(drvdata);
0253     if (drvdata->stmheer)
0254         stm_hwevent_disable_hw(drvdata);
0255 }
0256 
0257 static void stm_disable(struct coresight_device *csdev,
0258             struct perf_event *event)
0259 {
0260     struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0261     struct csdev_access *csa = &csdev->access;
0262 
0263     /*
0264      * For as long as the tracer isn't disabled another entity can't
0265      * change its status.  As such we can read the status here without
0266      * fearing it will change under us.
0267      */
0268     if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
0269         spin_lock(&drvdata->spinlock);
0270         stm_disable_hw(drvdata);
0271         spin_unlock(&drvdata->spinlock);
0272 
0273         /* Wait until the engine has completely stopped */
0274         coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
0275 
0276         pm_runtime_put(csdev->dev.parent);
0277 
0278         local_set(&drvdata->mode, CS_MODE_DISABLED);
0279         dev_dbg(&csdev->dev, "STM tracing disabled\n");
0280     }
0281 }
0282 
0283 static int stm_trace_id(struct coresight_device *csdev)
0284 {
0285     struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0286 
0287     return drvdata->traceid;
0288 }
0289 
0290 static const struct coresight_ops_source stm_source_ops = {
0291     .trace_id   = stm_trace_id,
0292     .enable     = stm_enable,
0293     .disable    = stm_disable,
0294 };
0295 
0296 static const struct coresight_ops stm_cs_ops = {
0297     .source_ops = &stm_source_ops,
0298 };
0299 
0300 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
0301 {
0302     return ((unsigned long)addr & (write_bytes - 1));
0303 }
0304 
0305 static void stm_send(void __iomem *addr, const void *data,
0306              u32 size, u8 write_bytes)
0307 {
0308     u8 paload[8];
0309 
0310     if (stm_addr_unaligned(data, write_bytes)) {
0311         memcpy(paload, data, size);
0312         data = paload;
0313     }
0314 
0315     /* now we are 64bit/32bit aligned */
0316     switch (size) {
0317 #ifdef CONFIG_64BIT
0318     case 8:
0319         writeq_relaxed(*(u64 *)data, addr);
0320         break;
0321 #endif
0322     case 4:
0323         writel_relaxed(*(u32 *)data, addr);
0324         break;
0325     case 2:
0326         writew_relaxed(*(u16 *)data, addr);
0327         break;
0328     case 1:
0329         writeb_relaxed(*(u8 *)data, addr);
0330         break;
0331     default:
0332         break;
0333     }
0334 }
0335 
0336 static int stm_generic_link(struct stm_data *stm_data,
0337                 unsigned int master,  unsigned int channel)
0338 {
0339     struct stm_drvdata *drvdata = container_of(stm_data,
0340                            struct stm_drvdata, stm);
0341     if (!drvdata || !drvdata->csdev)
0342         return -EINVAL;
0343 
0344     return coresight_enable(drvdata->csdev);
0345 }
0346 
0347 static void stm_generic_unlink(struct stm_data *stm_data,
0348                    unsigned int master,  unsigned int channel)
0349 {
0350     struct stm_drvdata *drvdata = container_of(stm_data,
0351                            struct stm_drvdata, stm);
0352     if (!drvdata || !drvdata->csdev)
0353         return;
0354 
0355     coresight_disable(drvdata->csdev);
0356 }
0357 
0358 static phys_addr_t
0359 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
0360           unsigned int channel, unsigned int nr_chans)
0361 {
0362     struct stm_drvdata *drvdata = container_of(stm_data,
0363                            struct stm_drvdata, stm);
0364     phys_addr_t addr;
0365 
0366     addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
0367 
0368     if (offset_in_page(addr) ||
0369         offset_in_page(nr_chans * BYTES_PER_CHANNEL))
0370         return 0;
0371 
0372     return addr;
0373 }
0374 
0375 static long stm_generic_set_options(struct stm_data *stm_data,
0376                     unsigned int master,
0377                     unsigned int channel,
0378                     unsigned int nr_chans,
0379                     unsigned long options)
0380 {
0381     struct stm_drvdata *drvdata = container_of(stm_data,
0382                            struct stm_drvdata, stm);
0383     if (!(drvdata && local_read(&drvdata->mode)))
0384         return -EINVAL;
0385 
0386     if (channel >= drvdata->numsp)
0387         return -EINVAL;
0388 
0389     switch (options) {
0390     case STM_OPTION_GUARANTEED:
0391         set_bit(channel, drvdata->chs.guaranteed);
0392         break;
0393 
0394     case STM_OPTION_INVARIANT:
0395         clear_bit(channel, drvdata->chs.guaranteed);
0396         break;
0397 
0398     default:
0399         return -EINVAL;
0400     }
0401 
0402     return 0;
0403 }
0404 
0405 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
0406                   unsigned int master,
0407                   unsigned int channel,
0408                   unsigned int packet,
0409                   unsigned int flags,
0410                   unsigned int size,
0411                   const unsigned char *payload)
0412 {
0413     void __iomem *ch_addr;
0414     struct stm_drvdata *drvdata = container_of(stm_data,
0415                            struct stm_drvdata, stm);
0416     unsigned int stm_flags;
0417 
0418     if (!(drvdata && local_read(&drvdata->mode)))
0419         return -EACCES;
0420 
0421     if (channel >= drvdata->numsp)
0422         return -EINVAL;
0423 
0424     ch_addr = stm_channel_addr(drvdata, channel);
0425 
0426     stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
0427             STM_FLAG_TIMESTAMPED : 0;
0428     stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
0429                STM_FLAG_GUARANTEED : 0;
0430 
0431     if (size > drvdata->write_bytes)
0432         size = drvdata->write_bytes;
0433     else
0434         size = rounddown_pow_of_two(size);
0435 
0436     switch (packet) {
0437     case STP_PACKET_FLAG:
0438         ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
0439 
0440         /*
0441          * The generic STM core sets a size of '0' on flag packets.
0442          * As such send a flag packet of size '1' and tell the
0443          * core we did so.
0444          */
0445         stm_send(ch_addr, payload, 1, drvdata->write_bytes);
0446         size = 1;
0447         break;
0448 
0449     case STP_PACKET_DATA:
0450         stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
0451         ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
0452         stm_send(ch_addr, payload, size,
0453                 drvdata->write_bytes);
0454         break;
0455 
0456     default:
0457         return -ENOTSUPP;
0458     }
0459 
0460     return size;
0461 }
0462 
0463 static ssize_t hwevent_enable_show(struct device *dev,
0464                    struct device_attribute *attr, char *buf)
0465 {
0466     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0467     unsigned long val = drvdata->stmheer;
0468 
0469     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
0470 }
0471 
0472 static ssize_t hwevent_enable_store(struct device *dev,
0473                     struct device_attribute *attr,
0474                     const char *buf, size_t size)
0475 {
0476     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0477     unsigned long val;
0478     int ret = 0;
0479 
0480     ret = kstrtoul(buf, 16, &val);
0481     if (ret)
0482         return -EINVAL;
0483 
0484     drvdata->stmheer = val;
0485     /* HW event enable and trigger go hand in hand */
0486     drvdata->stmheter = val;
0487 
0488     return size;
0489 }
0490 static DEVICE_ATTR_RW(hwevent_enable);
0491 
0492 static ssize_t hwevent_select_show(struct device *dev,
0493                    struct device_attribute *attr, char *buf)
0494 {
0495     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0496     unsigned long val = drvdata->stmhebsr;
0497 
0498     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
0499 }
0500 
0501 static ssize_t hwevent_select_store(struct device *dev,
0502                     struct device_attribute *attr,
0503                     const char *buf, size_t size)
0504 {
0505     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0506     unsigned long val;
0507     int ret = 0;
0508 
0509     ret = kstrtoul(buf, 16, &val);
0510     if (ret)
0511         return -EINVAL;
0512 
0513     drvdata->stmhebsr = val;
0514 
0515     return size;
0516 }
0517 static DEVICE_ATTR_RW(hwevent_select);
0518 
0519 static ssize_t port_select_show(struct device *dev,
0520                 struct device_attribute *attr, char *buf)
0521 {
0522     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0523     unsigned long val;
0524 
0525     if (!local_read(&drvdata->mode)) {
0526         val = drvdata->stmspscr;
0527     } else {
0528         spin_lock(&drvdata->spinlock);
0529         val = readl_relaxed(drvdata->base + STMSPSCR);
0530         spin_unlock(&drvdata->spinlock);
0531     }
0532 
0533     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
0534 }
0535 
0536 static ssize_t port_select_store(struct device *dev,
0537                  struct device_attribute *attr,
0538                  const char *buf, size_t size)
0539 {
0540     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0541     unsigned long val, stmsper;
0542     int ret = 0;
0543 
0544     ret = kstrtoul(buf, 16, &val);
0545     if (ret)
0546         return ret;
0547 
0548     spin_lock(&drvdata->spinlock);
0549     drvdata->stmspscr = val;
0550 
0551     if (local_read(&drvdata->mode)) {
0552         CS_UNLOCK(drvdata->base);
0553         /* Process as per ARM's TRM recommendation */
0554         stmsper = readl_relaxed(drvdata->base + STMSPER);
0555         writel_relaxed(0x0, drvdata->base + STMSPER);
0556         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
0557         writel_relaxed(stmsper, drvdata->base + STMSPER);
0558         CS_LOCK(drvdata->base);
0559     }
0560     spin_unlock(&drvdata->spinlock);
0561 
0562     return size;
0563 }
0564 static DEVICE_ATTR_RW(port_select);
0565 
0566 static ssize_t port_enable_show(struct device *dev,
0567                 struct device_attribute *attr, char *buf)
0568 {
0569     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0570     unsigned long val;
0571 
0572     if (!local_read(&drvdata->mode)) {
0573         val = drvdata->stmsper;
0574     } else {
0575         spin_lock(&drvdata->spinlock);
0576         val = readl_relaxed(drvdata->base + STMSPER);
0577         spin_unlock(&drvdata->spinlock);
0578     }
0579 
0580     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
0581 }
0582 
0583 static ssize_t port_enable_store(struct device *dev,
0584                  struct device_attribute *attr,
0585                  const char *buf, size_t size)
0586 {
0587     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0588     unsigned long val;
0589     int ret = 0;
0590 
0591     ret = kstrtoul(buf, 16, &val);
0592     if (ret)
0593         return ret;
0594 
0595     spin_lock(&drvdata->spinlock);
0596     drvdata->stmsper = val;
0597 
0598     if (local_read(&drvdata->mode)) {
0599         CS_UNLOCK(drvdata->base);
0600         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
0601         CS_LOCK(drvdata->base);
0602     }
0603     spin_unlock(&drvdata->spinlock);
0604 
0605     return size;
0606 }
0607 static DEVICE_ATTR_RW(port_enable);
0608 
0609 static ssize_t traceid_show(struct device *dev,
0610                 struct device_attribute *attr, char *buf)
0611 {
0612     unsigned long val;
0613     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0614 
0615     val = drvdata->traceid;
0616     return sprintf(buf, "%#lx\n", val);
0617 }
0618 
0619 static ssize_t traceid_store(struct device *dev,
0620                  struct device_attribute *attr,
0621                  const char *buf, size_t size)
0622 {
0623     int ret;
0624     unsigned long val;
0625     struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
0626 
0627     ret = kstrtoul(buf, 16, &val);
0628     if (ret)
0629         return ret;
0630 
0631     /* traceid field is 7bit wide on STM32 */
0632     drvdata->traceid = val & 0x7f;
0633     return size;
0634 }
0635 static DEVICE_ATTR_RW(traceid);
0636 
0637 #define coresight_stm_reg(name, offset) \
0638     coresight_simple_reg32(struct stm_drvdata, name, offset)
0639 
0640 coresight_stm_reg(tcsr, STMTCSR);
0641 coresight_stm_reg(tsfreqr, STMTSFREQR);
0642 coresight_stm_reg(syncr, STMSYNCR);
0643 coresight_stm_reg(sper, STMSPER);
0644 coresight_stm_reg(spter, STMSPTER);
0645 coresight_stm_reg(privmaskr, STMPRIVMASKR);
0646 coresight_stm_reg(spscr, STMSPSCR);
0647 coresight_stm_reg(spmscr, STMSPMSCR);
0648 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
0649 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
0650 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
0651 coresight_stm_reg(devid, CORESIGHT_DEVID);
0652 
0653 static struct attribute *coresight_stm_attrs[] = {
0654     &dev_attr_hwevent_enable.attr,
0655     &dev_attr_hwevent_select.attr,
0656     &dev_attr_port_enable.attr,
0657     &dev_attr_port_select.attr,
0658     &dev_attr_traceid.attr,
0659     NULL,
0660 };
0661 
0662 static struct attribute *coresight_stm_mgmt_attrs[] = {
0663     &dev_attr_tcsr.attr,
0664     &dev_attr_tsfreqr.attr,
0665     &dev_attr_syncr.attr,
0666     &dev_attr_sper.attr,
0667     &dev_attr_spter.attr,
0668     &dev_attr_privmaskr.attr,
0669     &dev_attr_spscr.attr,
0670     &dev_attr_spmscr.attr,
0671     &dev_attr_spfeat1r.attr,
0672     &dev_attr_spfeat2r.attr,
0673     &dev_attr_spfeat3r.attr,
0674     &dev_attr_devid.attr,
0675     NULL,
0676 };
0677 
0678 static const struct attribute_group coresight_stm_group = {
0679     .attrs = coresight_stm_attrs,
0680 };
0681 
0682 static const struct attribute_group coresight_stm_mgmt_group = {
0683     .attrs = coresight_stm_mgmt_attrs,
0684     .name = "mgmt",
0685 };
0686 
0687 static const struct attribute_group *coresight_stm_groups[] = {
0688     &coresight_stm_group,
0689     &coresight_stm_mgmt_group,
0690     NULL,
0691 };
0692 
0693 #ifdef CONFIG_OF
0694 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
0695 {
0696     const char *name = NULL;
0697     int index = 0, found = 0;
0698     struct device_node *np = dev->of_node;
0699 
0700     while (!of_property_read_string_index(np, "reg-names", index, &name)) {
0701         if (strcmp("stm-stimulus-base", name)) {
0702             index++;
0703             continue;
0704         }
0705 
0706         /* We have a match and @index is where it's at */
0707         found = 1;
0708         break;
0709     }
0710 
0711     if (!found)
0712         return -EINVAL;
0713 
0714     return of_address_to_resource(np, index, res);
0715 }
0716 #else
0717 static inline int of_stm_get_stimulus_area(struct device *dev,
0718                        struct resource *res)
0719 {
0720     return -ENOENT;
0721 }
0722 #endif
0723 
0724 #ifdef CONFIG_ACPI
0725 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
0726 {
0727     int rc;
0728     bool found_base = false;
0729     struct resource_entry *rent;
0730     LIST_HEAD(res_list);
0731 
0732     struct acpi_device *adev = ACPI_COMPANION(dev);
0733 
0734     rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
0735     if (rc < 0)
0736         return rc;
0737 
0738     /*
0739      * The stimulus base for STM device must be listed as the second memory
0740      * resource, followed by the programming base address as described in
0741      * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
0742      * document (DEN0067).
0743      */
0744     rc = -ENOENT;
0745     list_for_each_entry(rent, &res_list, node) {
0746         if (resource_type(rent->res) != IORESOURCE_MEM)
0747             continue;
0748         if (found_base) {
0749             *res = *rent->res;
0750             rc = 0;
0751             break;
0752         }
0753 
0754         found_base = true;
0755     }
0756 
0757     acpi_dev_free_resource_list(&res_list);
0758     return rc;
0759 }
0760 #else
0761 static inline int acpi_stm_get_stimulus_area(struct device *dev,
0762                          struct resource *res)
0763 {
0764     return -ENOENT;
0765 }
0766 #endif
0767 
0768 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
0769 {
0770     struct fwnode_handle *fwnode = dev_fwnode(dev);
0771 
0772     if (is_of_node(fwnode))
0773         return of_stm_get_stimulus_area(dev, res);
0774     else if (is_acpi_node(fwnode))
0775         return acpi_stm_get_stimulus_area(dev, res);
0776     return -ENOENT;
0777 }
0778 
0779 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
0780 {
0781     u32 stmspfeat2r;
0782 
0783     if (!IS_ENABLED(CONFIG_64BIT))
0784         return 4;
0785 
0786     stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
0787 
0788     /*
0789      * bit[15:12] represents the fundamental data size
0790      * 0 - 32-bit data
0791      * 1 - 64-bit data
0792      */
0793     return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
0794 }
0795 
0796 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
0797 {
0798     u32 numsp;
0799 
0800     numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
0801     /*
0802      * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
0803      * 32 stimulus ports are supported.
0804      */
0805     numsp &= 0x1ffff;
0806     if (!numsp)
0807         numsp = STM_32_CHANNEL;
0808     return numsp;
0809 }
0810 
0811 static void stm_init_default_data(struct stm_drvdata *drvdata)
0812 {
0813     /* Don't use port selection */
0814     drvdata->stmspscr = 0x0;
0815     /*
0816      * Enable all channel regardless of their number.  When port
0817      * selection isn't used (see above) STMSPER applies to all
0818      * 32 channel group available, hence setting all 32 bits to 1
0819      */
0820     drvdata->stmsper = ~0x0;
0821 
0822     /*
0823      * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
0824      * anything equal to or higher than 0x70 is reserved.  Since 0x00 is
0825      * also reserved the STM trace ID needs to be higher than 0x00 and
0826      * lowner than 0x10.
0827      */
0828     drvdata->traceid = 0x1;
0829 
0830     /* Set invariant transaction timing on all channels */
0831     bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
0832 }
0833 
0834 static void stm_init_generic_data(struct stm_drvdata *drvdata,
0835                   const char *name)
0836 {
0837     drvdata->stm.name = name;
0838 
0839     /*
0840      * MasterIDs are assigned at HW design phase. As such the core is
0841      * using a single master for interaction with this device.
0842      */
0843     drvdata->stm.sw_start = 1;
0844     drvdata->stm.sw_end = 1;
0845     drvdata->stm.hw_override = true;
0846     drvdata->stm.sw_nchannels = drvdata->numsp;
0847     drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
0848     drvdata->stm.packet = stm_generic_packet;
0849     drvdata->stm.mmio_addr = stm_mmio_addr;
0850     drvdata->stm.link = stm_generic_link;
0851     drvdata->stm.unlink = stm_generic_unlink;
0852     drvdata->stm.set_options = stm_generic_set_options;
0853 }
0854 
0855 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
0856 {
0857     int ret;
0858     void __iomem *base;
0859     struct device *dev = &adev->dev;
0860     struct coresight_platform_data *pdata = NULL;
0861     struct stm_drvdata *drvdata;
0862     struct resource *res = &adev->res;
0863     struct resource ch_res;
0864     struct coresight_desc desc = { 0 };
0865 
0866     desc.name = coresight_alloc_device_name(&stm_devs, dev);
0867     if (!desc.name)
0868         return -ENOMEM;
0869 
0870     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
0871     if (!drvdata)
0872         return -ENOMEM;
0873 
0874     drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
0875     if (!IS_ERR(drvdata->atclk)) {
0876         ret = clk_prepare_enable(drvdata->atclk);
0877         if (ret)
0878             return ret;
0879     }
0880     dev_set_drvdata(dev, drvdata);
0881 
0882     base = devm_ioremap_resource(dev, res);
0883     if (IS_ERR(base))
0884         return PTR_ERR(base);
0885     drvdata->base = base;
0886     desc.access = CSDEV_ACCESS_IOMEM(base);
0887 
0888     ret = stm_get_stimulus_area(dev, &ch_res);
0889     if (ret)
0890         return ret;
0891     drvdata->chs.phys = ch_res.start;
0892 
0893     base = devm_ioremap_resource(dev, &ch_res);
0894     if (IS_ERR(base))
0895         return PTR_ERR(base);
0896     drvdata->chs.base = base;
0897 
0898     drvdata->write_bytes = stm_fundamental_data_size(drvdata);
0899 
0900     if (boot_nr_channel)
0901         drvdata->numsp = boot_nr_channel;
0902     else
0903         drvdata->numsp = stm_num_stimulus_port(drvdata);
0904 
0905     drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp,
0906                              GFP_KERNEL);
0907     if (!drvdata->chs.guaranteed)
0908         return -ENOMEM;
0909 
0910     spin_lock_init(&drvdata->spinlock);
0911 
0912     stm_init_default_data(drvdata);
0913     stm_init_generic_data(drvdata, desc.name);
0914 
0915     if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
0916         dev_info(dev,
0917              "%s : stm_register_device failed, probing deferred\n",
0918              desc.name);
0919         return -EPROBE_DEFER;
0920     }
0921 
0922     pdata = coresight_get_platform_data(dev);
0923     if (IS_ERR(pdata)) {
0924         ret = PTR_ERR(pdata);
0925         goto stm_unregister;
0926     }
0927     adev->dev.platform_data = pdata;
0928 
0929     desc.type = CORESIGHT_DEV_TYPE_SOURCE;
0930     desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
0931     desc.ops = &stm_cs_ops;
0932     desc.pdata = pdata;
0933     desc.dev = dev;
0934     desc.groups = coresight_stm_groups;
0935     drvdata->csdev = coresight_register(&desc);
0936     if (IS_ERR(drvdata->csdev)) {
0937         ret = PTR_ERR(drvdata->csdev);
0938         goto stm_unregister;
0939     }
0940 
0941     pm_runtime_put(&adev->dev);
0942 
0943     dev_info(&drvdata->csdev->dev, "%s initialized\n",
0944          (char *)coresight_get_uci_data(id));
0945     return 0;
0946 
0947 stm_unregister:
0948     stm_unregister_device(&drvdata->stm);
0949     return ret;
0950 }
0951 
0952 static void stm_remove(struct amba_device *adev)
0953 {
0954     struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
0955 
0956     coresight_unregister(drvdata->csdev);
0957 
0958     stm_unregister_device(&drvdata->stm);
0959 }
0960 
0961 #ifdef CONFIG_PM
0962 static int stm_runtime_suspend(struct device *dev)
0963 {
0964     struct stm_drvdata *drvdata = dev_get_drvdata(dev);
0965 
0966     if (drvdata && !IS_ERR(drvdata->atclk))
0967         clk_disable_unprepare(drvdata->atclk);
0968 
0969     return 0;
0970 }
0971 
0972 static int stm_runtime_resume(struct device *dev)
0973 {
0974     struct stm_drvdata *drvdata = dev_get_drvdata(dev);
0975 
0976     if (drvdata && !IS_ERR(drvdata->atclk))
0977         clk_prepare_enable(drvdata->atclk);
0978 
0979     return 0;
0980 }
0981 #endif
0982 
0983 static const struct dev_pm_ops stm_dev_pm_ops = {
0984     SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
0985 };
0986 
0987 static const struct amba_id stm_ids[] = {
0988     CS_AMBA_ID_DATA(0x000bb962, "STM32"),
0989     CS_AMBA_ID_DATA(0x000bb963, "STM500"),
0990     { 0, 0},
0991 };
0992 
0993 MODULE_DEVICE_TABLE(amba, stm_ids);
0994 
0995 static struct amba_driver stm_driver = {
0996     .drv = {
0997         .name   = "coresight-stm",
0998         .owner  = THIS_MODULE,
0999         .pm = &stm_dev_pm_ops,
1000         .suppress_bind_attrs = true,
1001     },
1002     .probe          = stm_probe,
1003     .remove         = stm_remove,
1004     .id_table   = stm_ids,
1005 };
1006 
1007 module_amba_driver(stm_driver);
1008 
1009 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1010 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1011 MODULE_LICENSE("GPL v2");
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