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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/bitops.h>
0007 #include <linux/kernel.h>
0008 #include <linux/moduleparam.h>
0009 #include <linux/init.h>
0010 #include <linux/types.h>
0011 #include <linux/device.h>
0012 #include <linux/io.h>
0013 #include <linux/err.h>
0014 #include <linux/fs.h>
0015 #include <linux/slab.h>
0016 #include <linux/delay.h>
0017 #include <linux/smp.h>
0018 #include <linux/sysfs.h>
0019 #include <linux/stat.h>
0020 #include <linux/clk.h>
0021 #include <linux/cpu.h>
0022 #include <linux/cpu_pm.h>
0023 #include <linux/coresight.h>
0024 #include <linux/coresight-pmu.h>
0025 #include <linux/pm_wakeup.h>
0026 #include <linux/amba/bus.h>
0027 #include <linux/seq_file.h>
0028 #include <linux/uaccess.h>
0029 #include <linux/perf_event.h>
0030 #include <linux/platform_device.h>
0031 #include <linux/pm_runtime.h>
0032 #include <linux/property.h>
0033 
0034 #include <asm/barrier.h>
0035 #include <asm/sections.h>
0036 #include <asm/sysreg.h>
0037 #include <asm/local.h>
0038 #include <asm/virt.h>
0039 
0040 #include "coresight-etm4x.h"
0041 #include "coresight-etm-perf.h"
0042 #include "coresight-etm4x-cfg.h"
0043 #include "coresight-self-hosted-trace.h"
0044 #include "coresight-syscfg.h"
0045 
0046 static int boot_enable;
0047 module_param(boot_enable, int, 0444);
0048 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
0049 
0050 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
0051 #define PARAM_PM_SAVE_NEVER   1 /* never save any state */
0052 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
0053 
0054 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
0055 module_param(pm_save_enable, int, 0444);
0056 MODULE_PARM_DESC(pm_save_enable,
0057     "Save/restore state on power down: 1 = never, 2 = self-hosted");
0058 
0059 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
0060 static void etm4_set_default_config(struct etmv4_config *config);
0061 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
0062                   struct perf_event *event);
0063 static u64 etm4_get_access_type(struct etmv4_config *config);
0064 
0065 static enum cpuhp_state hp_online;
0066 
0067 struct etm4_init_arg {
0068     unsigned int        pid;
0069     struct etmv4_drvdata    *drvdata;
0070     struct csdev_access *csa;
0071 };
0072 
0073 /*
0074  * Check if TRCSSPCICRn(i) is implemented for a given instance.
0075  *
0076  * TRCSSPCICRn is implemented only if :
0077  *  TRCSSPCICR<n> is present only if all of the following are true:
0078  *      TRCIDR4.NUMSSCC > n.
0079  *      TRCIDR4.NUMPC > 0b0000 .
0080  *      TRCSSCSR<n>.PC == 0b1
0081  */
0082 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
0083 {
0084     return (n < drvdata->nr_ss_cmp) &&
0085            drvdata->nr_pe &&
0086            (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
0087 }
0088 
0089 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
0090 {
0091     u64 res = 0;
0092 
0093     switch (offset) {
0094     ETM4x_READ_SYSREG_CASES(res)
0095     default :
0096         pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
0097              offset);
0098     }
0099 
0100     if (!_relaxed)
0101         __io_ar(res);   /* Imitate the !relaxed I/O helpers */
0102 
0103     return res;
0104 }
0105 
0106 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
0107 {
0108     if (!_relaxed)
0109         __io_bw();  /* Imitate the !relaxed I/O helpers */
0110     if (!_64bit)
0111         val &= GENMASK(31, 0);
0112 
0113     switch (offset) {
0114     ETM4x_WRITE_SYSREG_CASES(val)
0115     default :
0116         pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
0117             offset);
0118     }
0119 }
0120 
0121 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
0122 {
0123     u64 res = 0;
0124 
0125     switch (offset) {
0126     ETE_READ_CASES(res)
0127     default :
0128         pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
0129                     offset);
0130     }
0131 
0132     if (!_relaxed)
0133         __io_ar(res);   /* Imitate the !relaxed I/O helpers */
0134 
0135     return res;
0136 }
0137 
0138 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
0139 {
0140     if (!_relaxed)
0141         __io_bw();  /* Imitate the !relaxed I/O helpers */
0142     if (!_64bit)
0143         val &= GENMASK(31, 0);
0144 
0145     switch (offset) {
0146     ETE_WRITE_CASES(val)
0147     default :
0148         pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
0149                     offset);
0150     }
0151 }
0152 
0153 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
0154                    struct csdev_access *csa)
0155 {
0156     u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
0157 
0158     drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
0159 }
0160 
0161 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
0162                   struct csdev_access *csa, u32 val)
0163 {
0164     val = !!val;
0165 
0166     switch (drvdata->os_lock_model) {
0167     case ETM_OSLOCK_PRESENT:
0168         etm4x_relaxed_write32(csa, val, TRCOSLAR);
0169         break;
0170     case ETM_OSLOCK_PE:
0171         write_sysreg_s(val, SYS_OSLAR_EL1);
0172         break;
0173     default:
0174         pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
0175                  smp_processor_id(), drvdata->os_lock_model);
0176         fallthrough;
0177     case ETM_OSLOCK_NI:
0178         return;
0179     }
0180     isb();
0181 }
0182 
0183 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
0184                       struct csdev_access *csa)
0185 {
0186     WARN_ON(drvdata->cpu != smp_processor_id());
0187 
0188     /* Writing 0 to OS Lock unlocks the trace unit registers */
0189     etm_write_os_lock(drvdata, csa, 0x0);
0190     drvdata->os_unlock = true;
0191 }
0192 
0193 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
0194 {
0195     if (!WARN_ON(!drvdata->csdev))
0196         etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
0197 }
0198 
0199 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
0200 {
0201     if (WARN_ON(!drvdata->csdev))
0202         return;
0203     /* Writing 0x1 to OS Lock locks the trace registers */
0204     etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
0205     drvdata->os_unlock = false;
0206 }
0207 
0208 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
0209              struct csdev_access *csa)
0210 {
0211     /* Software Lock is only accessible via memory mapped interface */
0212     if (csa->io_mem)
0213         CS_LOCK(csa->base);
0214 }
0215 
0216 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
0217                struct csdev_access *csa)
0218 {
0219     if (csa->io_mem)
0220         CS_UNLOCK(csa->base);
0221 }
0222 
0223 static int etm4_cpu_id(struct coresight_device *csdev)
0224 {
0225     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0226 
0227     return drvdata->cpu;
0228 }
0229 
0230 static int etm4_trace_id(struct coresight_device *csdev)
0231 {
0232     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0233 
0234     return drvdata->trcid;
0235 }
0236 
0237 struct etm4_enable_arg {
0238     struct etmv4_drvdata *drvdata;
0239     int rc;
0240 };
0241 
0242 /*
0243  * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
0244  * When the CPU supports FEAT_TRF, we could move the ETM to a trace
0245  * prohibited state by filtering the Exception levels via TRFCR_EL1.
0246  */
0247 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
0248 {
0249     /* If the CPU doesn't support FEAT_TRF, nothing to do */
0250     if (!drvdata->trfcr)
0251         return;
0252     cpu_prohibit_trace();
0253 }
0254 
0255 /*
0256  * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
0257  * as configured by the drvdata->config.mode for the current
0258  * session. Even though we have TRCVICTLR bits to filter the
0259  * trace in the ELs, it doesn't prevent the ETM from generating
0260  * a packet (e.g, TraceInfo) that might contain the addresses from
0261  * the excluded levels. Thus we use the additional controls provided
0262  * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
0263  * is generated for the excluded ELs.
0264  */
0265 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
0266 {
0267     u64 trfcr = drvdata->trfcr;
0268 
0269     /* If the CPU doesn't support FEAT_TRF, nothing to do */
0270     if (!trfcr)
0271         return;
0272 
0273     if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
0274         trfcr &= ~TRFCR_ELx_ExTRE;
0275     if (drvdata->config.mode & ETM_MODE_EXCL_USER)
0276         trfcr &= ~TRFCR_ELx_E0TRE;
0277 
0278     write_trfcr(trfcr);
0279 }
0280 
0281 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
0282 
0283 #define HISI_HIP08_AMBA_ID      0x000b6d01
0284 #define ETM4_AMBA_MASK          0xfffff
0285 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
0286 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
0287 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
0288 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
0289 #define HISI_HIP08_CORE_COMMIT_REG  sys_reg(3, 1, 15, 2, 5)
0290 
0291 struct etm4_arch_features {
0292     void (*arch_callback)(bool enable);
0293 };
0294 
0295 static bool etm4_hisi_match_pid(unsigned int id)
0296 {
0297     return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
0298 }
0299 
0300 static void etm4_hisi_config_core_commit(bool enable)
0301 {
0302     u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
0303             HISI_HIP08_CORE_COMMIT_FULL;
0304     u64 val;
0305 
0306     /*
0307      * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
0308      * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
0309      * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
0310      * speed(minimun value). So bit 12 and 13 should be cleared together.
0311      */
0312     val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
0313     val &= ~HISI_HIP08_CORE_COMMIT_MASK;
0314     val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
0315     write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
0316 }
0317 
0318 static struct etm4_arch_features etm4_features[] = {
0319     [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
0320         .arch_callback = etm4_hisi_config_core_commit,
0321     },
0322     {},
0323 };
0324 
0325 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
0326 {
0327     struct etm4_arch_features *ftr;
0328     int bit;
0329 
0330     for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
0331         ftr = &etm4_features[bit];
0332 
0333         if (ftr->arch_callback)
0334             ftr->arch_callback(true);
0335     }
0336 }
0337 
0338 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
0339 {
0340     struct etm4_arch_features *ftr;
0341     int bit;
0342 
0343     for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
0344         ftr = &etm4_features[bit];
0345 
0346         if (ftr->arch_callback)
0347             ftr->arch_callback(false);
0348     }
0349 }
0350 
0351 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
0352                       unsigned int id)
0353 {
0354     if (etm4_hisi_match_pid(id))
0355         set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
0356 }
0357 #else
0358 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
0359 {
0360 }
0361 
0362 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
0363 {
0364 }
0365 
0366 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
0367                      unsigned int id)
0368 {
0369 }
0370 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
0371 
0372 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
0373 {
0374     int i, rc;
0375     struct etmv4_config *config = &drvdata->config;
0376     struct coresight_device *csdev = drvdata->csdev;
0377     struct device *etm_dev = &csdev->dev;
0378     struct csdev_access *csa = &csdev->access;
0379 
0380 
0381     etm4_cs_unlock(drvdata, csa);
0382     etm4_enable_arch_specific(drvdata);
0383 
0384     etm4_os_unlock(drvdata);
0385 
0386     rc = coresight_claim_device_unlocked(csdev);
0387     if (rc)
0388         goto done;
0389 
0390     /* Disable the trace unit before programming trace registers */
0391     etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
0392 
0393     /*
0394      * If we use system instructions, we need to synchronize the
0395      * write to the TRCPRGCTLR, before accessing the TRCSTATR.
0396      * See ARM IHI0064F, section
0397      * "4.3.7 Synchronization of register updates"
0398      */
0399     if (!csa->io_mem)
0400         isb();
0401 
0402     /* wait for TRCSTATR.IDLE to go up */
0403     if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
0404         dev_err(etm_dev,
0405             "timeout while waiting for Idle Trace Status\n");
0406     if (drvdata->nr_pe)
0407         etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
0408     etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
0409     /* nothing specific implemented */
0410     etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
0411     etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
0412     etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
0413     if (drvdata->stallctl)
0414         etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
0415     etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
0416     etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
0417     etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
0418     etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
0419     etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
0420     etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
0421     etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
0422     etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
0423     if (drvdata->nr_pe_cmp)
0424         etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
0425     for (i = 0; i < drvdata->nrseqstate - 1; i++)
0426         etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
0427     etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
0428     etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
0429     etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
0430     for (i = 0; i < drvdata->nr_cntr; i++) {
0431         etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
0432         etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
0433         etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
0434     }
0435 
0436     /*
0437      * Resource selector pair 0 is always implemented and reserved.  As
0438      * such start at 2.
0439      */
0440     for (i = 2; i < drvdata->nr_resource * 2; i++)
0441         etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
0442 
0443     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
0444         /* always clear status bit on restart if using single-shot */
0445         if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
0446             config->ss_status[i] &= ~TRCSSCSRn_STATUS;
0447         etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
0448         etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
0449         if (etm4x_sspcicrn_present(drvdata, i))
0450             etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
0451     }
0452     for (i = 0; i < drvdata->nr_addr_cmp; i++) {
0453         etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
0454         etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
0455     }
0456     for (i = 0; i < drvdata->numcidc; i++)
0457         etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
0458     etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
0459     if (drvdata->numcidc > 4)
0460         etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
0461 
0462     for (i = 0; i < drvdata->numvmidc; i++)
0463         etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
0464     etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
0465     if (drvdata->numvmidc > 4)
0466         etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
0467 
0468     if (!drvdata->skip_power_up) {
0469         u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
0470 
0471         /*
0472          * Request to keep the trace unit powered and also
0473          * emulation of powerdown
0474          */
0475         etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
0476     }
0477 
0478     /*
0479      * ETE mandates that the TRCRSR is written to before
0480      * enabling it.
0481      */
0482     if (etm4x_is_ete(drvdata))
0483         etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
0484 
0485     etm4x_allow_trace(drvdata);
0486     /* Enable the trace unit */
0487     etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
0488 
0489     /* Synchronize the register updates for sysreg access */
0490     if (!csa->io_mem)
0491         isb();
0492 
0493     /* wait for TRCSTATR.IDLE to go back down to '0' */
0494     if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
0495         dev_err(etm_dev,
0496             "timeout while waiting for Idle Trace Status\n");
0497 
0498     /*
0499      * As recommended by section 4.3.7 ("Synchronization when using the
0500      * memory-mapped interface") of ARM IHI 0064D
0501      */
0502     dsb(sy);
0503     isb();
0504 
0505 done:
0506     etm4_cs_lock(drvdata, csa);
0507 
0508     dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
0509         drvdata->cpu, rc);
0510     return rc;
0511 }
0512 
0513 static void etm4_enable_hw_smp_call(void *info)
0514 {
0515     struct etm4_enable_arg *arg = info;
0516 
0517     if (WARN_ON(!arg))
0518         return;
0519     arg->rc = etm4_enable_hw(arg->drvdata);
0520 }
0521 
0522 /*
0523  * The goal of function etm4_config_timestamp_event() is to configure a
0524  * counter that will tell the tracer to emit a timestamp packet when it
0525  * reaches zero.  This is done in order to get a more fine grained idea
0526  * of when instructions are executed so that they can be correlated
0527  * with execution on other CPUs.
0528  *
0529  * To do this the counter itself is configured to self reload and
0530  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
0531  * there a resource selector is configured with the counter and the
0532  * timestamp control register to use the resource selector to trigger the
0533  * event that will insert a timestamp packet in the stream.
0534  */
0535 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
0536 {
0537     int ctridx, ret = -EINVAL;
0538     int counter, rselector;
0539     u32 val = 0;
0540     struct etmv4_config *config = &drvdata->config;
0541 
0542     /* No point in trying if we don't have at least one counter */
0543     if (!drvdata->nr_cntr)
0544         goto out;
0545 
0546     /* Find a counter that hasn't been initialised */
0547     for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
0548         if (config->cntr_val[ctridx] == 0)
0549             break;
0550 
0551     /* All the counters have been configured already, bail out */
0552     if (ctridx == drvdata->nr_cntr) {
0553         pr_debug("%s: no available counter found\n", __func__);
0554         ret = -ENOSPC;
0555         goto out;
0556     }
0557 
0558     /*
0559      * Searching for an available resource selector to use, starting at
0560      * '2' since every implementation has at least 2 resource selector.
0561      * ETMIDR4 gives the number of resource selector _pairs_,
0562      * hence multiply by 2.
0563      */
0564     for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
0565         if (!config->res_ctrl[rselector])
0566             break;
0567 
0568     if (rselector == drvdata->nr_resource * 2) {
0569         pr_debug("%s: no available resource selector found\n",
0570              __func__);
0571         ret = -ENOSPC;
0572         goto out;
0573     }
0574 
0575     /* Remember what counter we used */
0576     counter = 1 << ctridx;
0577 
0578     /*
0579      * Initialise original and reload counter value to the smallest
0580      * possible value in order to get as much precision as we can.
0581      */
0582     config->cntr_val[ctridx] = 1;
0583     config->cntrldvr[ctridx] = 1;
0584 
0585     /* Set the trace counter control register */
0586     val =  0x1 << 16    |  /* Bit 16, reload counter automatically */
0587            0x0 << 7     |  /* Select single resource selector */
0588            0x1;        /* Resource selector 1, i.e always true */
0589 
0590     config->cntr_ctrl[ctridx] = val;
0591 
0592     val = 0x2 << 16     | /* Group 0b0010 - Counter and sequencers */
0593           counter << 0;   /* Counter to use */
0594 
0595     config->res_ctrl[rselector] = val;
0596 
0597     val = 0x0 << 7      | /* Select single resource selector */
0598           rselector;      /* Resource selector */
0599 
0600     config->ts_ctrl = val;
0601 
0602     ret = 0;
0603 out:
0604     return ret;
0605 }
0606 
0607 static int etm4_parse_event_config(struct coresight_device *csdev,
0608                    struct perf_event *event)
0609 {
0610     int ret = 0;
0611     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0612     struct etmv4_config *config = &drvdata->config;
0613     struct perf_event_attr *attr = &event->attr;
0614     unsigned long cfg_hash;
0615     int preset;
0616 
0617     /* Clear configuration from previous run */
0618     memset(config, 0, sizeof(struct etmv4_config));
0619 
0620     if (attr->exclude_kernel)
0621         config->mode = ETM_MODE_EXCL_KERN;
0622 
0623     if (attr->exclude_user)
0624         config->mode = ETM_MODE_EXCL_USER;
0625 
0626     /* Always start from the default config */
0627     etm4_set_default_config(config);
0628 
0629     /* Configure filters specified on the perf cmd line, if any. */
0630     ret = etm4_set_event_filters(drvdata, event);
0631     if (ret)
0632         goto out;
0633 
0634     /* Go from generic option to ETMv4 specifics */
0635     if (attr->config & BIT(ETM_OPT_CYCACC)) {
0636         config->cfg |= TRCCONFIGR_CCI;
0637         /* TRM: Must program this for cycacc to work */
0638         config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
0639     }
0640     if (attr->config & BIT(ETM_OPT_TS)) {
0641         /*
0642          * Configure timestamps to be emitted at regular intervals in
0643          * order to correlate instructions executed on different CPUs
0644          * (CPU-wide trace scenarios).
0645          */
0646         ret = etm4_config_timestamp_event(drvdata);
0647 
0648         /*
0649          * No need to go further if timestamp intervals can't
0650          * be configured.
0651          */
0652         if (ret)
0653             goto out;
0654 
0655         /* bit[11], Global timestamp tracing bit */
0656         config->cfg |= TRCCONFIGR_TS;
0657     }
0658 
0659     /* Only trace contextID when runs in root PID namespace */
0660     if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
0661         task_is_in_init_pid_ns(current))
0662         /* bit[6], Context ID tracing bit */
0663         config->cfg |= TRCCONFIGR_CID;
0664 
0665     /*
0666      * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
0667      * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
0668      * kernel is not running in EL2.
0669      */
0670     if (attr->config & BIT(ETM_OPT_CTXTID2)) {
0671         if (!is_kernel_in_hyp_mode()) {
0672             ret = -EINVAL;
0673             goto out;
0674         }
0675         /* Only trace virtual contextID when runs in root PID namespace */
0676         if (task_is_in_init_pid_ns(current))
0677             config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
0678     }
0679 
0680     /* return stack - enable if selected and supported */
0681     if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
0682         /* bit[12], Return stack enable bit */
0683         config->cfg |= TRCCONFIGR_RS;
0684 
0685     /*
0686      * Set any selected configuration and preset.
0687      *
0688      * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
0689      * in the perf attributes defined in coresight-etm-perf.c.
0690      * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
0691      * A zero configid means no configuration active, preset = 0 means no preset selected.
0692      */
0693     if (attr->config2 & GENMASK_ULL(63, 32)) {
0694         cfg_hash = (u32)(attr->config2 >> 32);
0695         preset = attr->config & 0xF;
0696         ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
0697     }
0698 
0699     /* branch broadcast - enable if selected and supported */
0700     if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
0701         if (!drvdata->trcbb) {
0702             /*
0703              * Missing BB support could cause silent decode errors
0704              * so fail to open if it's not supported.
0705              */
0706             ret = -EINVAL;
0707             goto out;
0708         } else {
0709             config->cfg |= BIT(ETM4_CFG_BIT_BB);
0710         }
0711     }
0712 
0713 out:
0714     return ret;
0715 }
0716 
0717 static int etm4_enable_perf(struct coresight_device *csdev,
0718                 struct perf_event *event)
0719 {
0720     int ret = 0;
0721     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0722 
0723     if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
0724         ret = -EINVAL;
0725         goto out;
0726     }
0727 
0728     /* Configure the tracer based on the session's specifics */
0729     ret = etm4_parse_event_config(csdev, event);
0730     if (ret)
0731         goto out;
0732     /* And enable it */
0733     ret = etm4_enable_hw(drvdata);
0734 
0735 out:
0736     return ret;
0737 }
0738 
0739 static int etm4_enable_sysfs(struct coresight_device *csdev)
0740 {
0741     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0742     struct etm4_enable_arg arg = { };
0743     unsigned long cfg_hash;
0744     int ret, preset;
0745 
0746     /* enable any config activated by configfs */
0747     cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
0748     if (cfg_hash) {
0749         ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
0750         if (ret)
0751             return ret;
0752     }
0753 
0754     spin_lock(&drvdata->spinlock);
0755 
0756     /*
0757      * Executing etm4_enable_hw on the cpu whose ETM is being enabled
0758      * ensures that register writes occur when cpu is powered.
0759      */
0760     arg.drvdata = drvdata;
0761     ret = smp_call_function_single(drvdata->cpu,
0762                        etm4_enable_hw_smp_call, &arg, 1);
0763     if (!ret)
0764         ret = arg.rc;
0765     if (!ret)
0766         drvdata->sticky_enable = true;
0767     spin_unlock(&drvdata->spinlock);
0768 
0769     if (!ret)
0770         dev_dbg(&csdev->dev, "ETM tracing enabled\n");
0771     return ret;
0772 }
0773 
0774 static int etm4_enable(struct coresight_device *csdev,
0775                struct perf_event *event, u32 mode)
0776 {
0777     int ret;
0778     u32 val;
0779     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0780 
0781     val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
0782 
0783     /* Someone is already using the tracer */
0784     if (val)
0785         return -EBUSY;
0786 
0787     switch (mode) {
0788     case CS_MODE_SYSFS:
0789         ret = etm4_enable_sysfs(csdev);
0790         break;
0791     case CS_MODE_PERF:
0792         ret = etm4_enable_perf(csdev, event);
0793         break;
0794     default:
0795         ret = -EINVAL;
0796     }
0797 
0798     /* The tracer didn't start */
0799     if (ret)
0800         local_set(&drvdata->mode, CS_MODE_DISABLED);
0801 
0802     return ret;
0803 }
0804 
0805 static void etm4_disable_hw(void *info)
0806 {
0807     u32 control;
0808     struct etmv4_drvdata *drvdata = info;
0809     struct etmv4_config *config = &drvdata->config;
0810     struct coresight_device *csdev = drvdata->csdev;
0811     struct device *etm_dev = &csdev->dev;
0812     struct csdev_access *csa = &csdev->access;
0813     int i;
0814 
0815     etm4_cs_unlock(drvdata, csa);
0816     etm4_disable_arch_specific(drvdata);
0817 
0818     if (!drvdata->skip_power_up) {
0819         /* power can be removed from the trace unit now */
0820         control = etm4x_relaxed_read32(csa, TRCPDCR);
0821         control &= ~TRCPDCR_PU;
0822         etm4x_relaxed_write32(csa, control, TRCPDCR);
0823     }
0824 
0825     control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
0826 
0827     /* EN, bit[0] Trace unit enable bit */
0828     control &= ~0x1;
0829 
0830     /*
0831      * If the CPU supports v8.4 Trace filter Control,
0832      * set the ETM to trace prohibited region.
0833      */
0834     etm4x_prohibit_trace(drvdata);
0835     /*
0836      * Make sure everything completes before disabling, as recommended
0837      * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
0838      * SSTATUS") of ARM IHI 0064D
0839      */
0840     dsb(sy);
0841     isb();
0842     /* Trace synchronization barrier, is a nop if not supported */
0843     tsb_csync();
0844     etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
0845 
0846     /* wait for TRCSTATR.PMSTABLE to go to '1' */
0847     if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
0848         dev_err(etm_dev,
0849             "timeout while waiting for PM stable Trace Status\n");
0850     /* read the status of the single shot comparators */
0851     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
0852         config->ss_status[i] =
0853             etm4x_relaxed_read32(csa, TRCSSCSRn(i));
0854     }
0855 
0856     /* read back the current counter values */
0857     for (i = 0; i < drvdata->nr_cntr; i++) {
0858         config->cntr_val[i] =
0859             etm4x_relaxed_read32(csa, TRCCNTVRn(i));
0860     }
0861 
0862     coresight_disclaim_device_unlocked(csdev);
0863     etm4_cs_lock(drvdata, csa);
0864 
0865     dev_dbg(&drvdata->csdev->dev,
0866         "cpu: %d disable smp call done\n", drvdata->cpu);
0867 }
0868 
0869 static int etm4_disable_perf(struct coresight_device *csdev,
0870                  struct perf_event *event)
0871 {
0872     u32 control;
0873     struct etm_filters *filters = event->hw.addr_filters;
0874     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0875     struct perf_event_attr *attr = &event->attr;
0876 
0877     if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
0878         return -EINVAL;
0879 
0880     etm4_disable_hw(drvdata);
0881     /*
0882      * The config_id occupies bits 63:32 of the config2 perf event attr
0883      * field. If this is non-zero then we will have enabled a config.
0884      */
0885     if (attr->config2 & GENMASK_ULL(63, 32))
0886         cscfg_csdev_disable_active_config(csdev);
0887 
0888     /*
0889      * Check if the start/stop logic was active when the unit was stopped.
0890      * That way we can re-enable the start/stop logic when the process is
0891      * scheduled again.  Configuration of the start/stop logic happens in
0892      * function etm4_set_event_filters().
0893      */
0894     control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
0895     /* TRCVICTLR::SSSTATUS, bit[9] */
0896     filters->ssstatus = (control & BIT(9));
0897 
0898     return 0;
0899 }
0900 
0901 static void etm4_disable_sysfs(struct coresight_device *csdev)
0902 {
0903     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0904 
0905     /*
0906      * Taking hotplug lock here protects from clocks getting disabled
0907      * with tracing being left on (crash scenario) if user disable occurs
0908      * after cpu online mask indicates the cpu is offline but before the
0909      * DYING hotplug callback is serviced by the ETM driver.
0910      */
0911     cpus_read_lock();
0912     spin_lock(&drvdata->spinlock);
0913 
0914     /*
0915      * Executing etm4_disable_hw on the cpu whose ETM is being disabled
0916      * ensures that register writes occur when cpu is powered.
0917      */
0918     smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
0919 
0920     spin_unlock(&drvdata->spinlock);
0921     cpus_read_unlock();
0922 
0923     dev_dbg(&csdev->dev, "ETM tracing disabled\n");
0924 }
0925 
0926 static void etm4_disable(struct coresight_device *csdev,
0927              struct perf_event *event)
0928 {
0929     u32 mode;
0930     struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
0931 
0932     /*
0933      * For as long as the tracer isn't disabled another entity can't
0934      * change its status.  As such we can read the status here without
0935      * fearing it will change under us.
0936      */
0937     mode = local_read(&drvdata->mode);
0938 
0939     switch (mode) {
0940     case CS_MODE_DISABLED:
0941         break;
0942     case CS_MODE_SYSFS:
0943         etm4_disable_sysfs(csdev);
0944         break;
0945     case CS_MODE_PERF:
0946         etm4_disable_perf(csdev, event);
0947         break;
0948     }
0949 
0950     if (mode)
0951         local_set(&drvdata->mode, CS_MODE_DISABLED);
0952 }
0953 
0954 static const struct coresight_ops_source etm4_source_ops = {
0955     .cpu_id     = etm4_cpu_id,
0956     .trace_id   = etm4_trace_id,
0957     .enable     = etm4_enable,
0958     .disable    = etm4_disable,
0959 };
0960 
0961 static const struct coresight_ops etm4_cs_ops = {
0962     .source_ops = &etm4_source_ops,
0963 };
0964 
0965 static inline bool cpu_supports_sysreg_trace(void)
0966 {
0967     u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
0968 
0969     return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
0970 }
0971 
0972 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
0973                     struct csdev_access *csa)
0974 {
0975     u32 devarch;
0976 
0977     if (!cpu_supports_sysreg_trace())
0978         return false;
0979 
0980     /*
0981      * ETMs implementing sysreg access must implement TRCDEVARCH.
0982      */
0983     devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
0984     switch (devarch & ETM_DEVARCH_ID_MASK) {
0985     case ETM_DEVARCH_ETMv4x_ARCH:
0986         *csa = (struct csdev_access) {
0987             .io_mem = false,
0988             .read   = etm4x_sysreg_read,
0989             .write  = etm4x_sysreg_write,
0990         };
0991         break;
0992     case ETM_DEVARCH_ETE_ARCH:
0993         *csa = (struct csdev_access) {
0994             .io_mem = false,
0995             .read   = ete_sysreg_read,
0996             .write  = ete_sysreg_write,
0997         };
0998         break;
0999     default:
1000         return false;
1001     }
1002 
1003     drvdata->arch = etm_devarch_to_arch(devarch);
1004     return true;
1005 }
1006 
1007 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1008                    struct csdev_access *csa)
1009 {
1010     u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1011     u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
1012 
1013     /*
1014      * All ETMs must implement TRCDEVARCH to indicate that
1015      * the component is an ETMv4. To support any broken
1016      * implementations we fall back to TRCIDR1 check, which
1017      * is not really reliable.
1018      */
1019     if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
1020         drvdata->arch = etm_devarch_to_arch(devarch);
1021     } else {
1022         pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
1023             smp_processor_id(), devarch);
1024 
1025         if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
1026             return false;
1027         drvdata->arch = etm_trcidr_to_arch(idr1);
1028     }
1029 
1030     *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1031     return true;
1032 }
1033 
1034 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1035                    struct csdev_access *csa)
1036 {
1037     /*
1038      * Always choose the memory mapped io, if there is
1039      * a memory map to prevent sysreg access on broken
1040      * systems.
1041      */
1042     if (drvdata->base)
1043         return etm4_init_iomem_access(drvdata, csa);
1044 
1045     if (etm4_init_sysreg_access(drvdata, csa))
1046         return true;
1047 
1048     return false;
1049 }
1050 
1051 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1052 {
1053     u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1054     u64 trfcr;
1055 
1056     drvdata->trfcr = 0;
1057     if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
1058         return;
1059 
1060     /*
1061      * If the CPU supports v8.4 SelfHosted Tracing, enable
1062      * tracing at the kernel EL and EL0, forcing to use the
1063      * virtual time as the timestamp.
1064      */
1065     trfcr = (TRFCR_ELx_TS_VIRTUAL |
1066          TRFCR_ELx_ExTRE |
1067          TRFCR_ELx_E0TRE);
1068 
1069     /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1070     if (is_kernel_in_hyp_mode())
1071         trfcr |= TRFCR_EL2_CX;
1072 
1073     drvdata->trfcr = trfcr;
1074 }
1075 
1076 static void etm4_init_arch_data(void *info)
1077 {
1078     u32 etmidr0;
1079     u32 etmidr2;
1080     u32 etmidr3;
1081     u32 etmidr4;
1082     u32 etmidr5;
1083     struct etm4_init_arg *init_arg = info;
1084     struct etmv4_drvdata *drvdata;
1085     struct csdev_access *csa;
1086     int i;
1087 
1088     drvdata = init_arg->drvdata;
1089     csa = init_arg->csa;
1090 
1091     /*
1092      * If we are unable to detect the access mechanism,
1093      * or unable to detect the trace unit type, fail
1094      * early.
1095      */
1096     if (!etm4_init_csdev_access(drvdata, csa))
1097         return;
1098 
1099     /* Detect the support for OS Lock before we actually use it */
1100     etm_detect_os_lock(drvdata, csa);
1101 
1102     /* Make sure all registers are accessible */
1103     etm4_os_unlock_csa(drvdata, csa);
1104     etm4_cs_unlock(drvdata, csa);
1105 
1106     etm4_check_arch_features(drvdata, init_arg->pid);
1107 
1108     /* find all capabilities of the tracing unit */
1109     etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1110 
1111     /* INSTP0, bits[2:1] P0 tracing support field */
1112     drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1113     /* TRCBB, bit[5] Branch broadcast tracing support bit */
1114     drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1115     /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1116     drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1117     /* TRCCCI, bit[7] Cycle counting instruction bit */
1118     drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1119     /* RETSTACK, bit[9] Return stack bit */
1120     drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1121     /* NUMEVENT, bits[11:10] Number of events field */
1122     drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1123     /* QSUPP, bits[16:15] Q element support field */
1124     drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1125     /* TSSIZE, bits[28:24] Global timestamp size field */
1126     drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1127 
1128     /* maximum size of resources */
1129     etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1130     /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1131     drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1132     /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1133     drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1134     /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1135     drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1136 
1137     etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1138     /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1139     drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1140     /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1141     drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1142     drvdata->config.s_ex_level = drvdata->s_ex_level;
1143     /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1144     drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1145     /*
1146      * TRCERR, bit[24] whether a trace unit can trace a
1147      * system error exception.
1148      */
1149     drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1150     /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1151     drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1152     /* STALLCTL, bit[26] is stall control implemented? */
1153     drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1154     /* SYSSTALL, bit[27] implementation can support stall control? */
1155     drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1156     /*
1157      * NUMPROC - the number of PEs available for tracing, 5bits
1158      *         = TRCIDR3.bits[13:12]bits[30:28]
1159      *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1160      *  bits[3:0] = TRCIDR3.bits[30:28]
1161      */
1162     drvdata->nr_pe =  (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1163                FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1164     /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1165     drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1166 
1167     /* number of resources trace unit supports */
1168     etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1169     /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1170     drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1171     /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1172     drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1173     /*
1174      * NUMRSPAIR, bits[19:16]
1175      * The number of resource pairs conveyed by the HW starts at 0, i.e a
1176      * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1177      * As such add 1 to the value of NUMRSPAIR for a better representation.
1178      *
1179      * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1180      * the default TRUE and FALSE resource selectors are omitted.
1181      * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1182      */
1183     drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1184     if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1185         drvdata->nr_resource += 1;
1186     /*
1187      * NUMSSCC, bits[23:20] the number of single-shot
1188      * comparator control for tracing. Read any status regs as these
1189      * also contain RO capability data.
1190      */
1191     drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1192     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1193         drvdata->config.ss_status[i] =
1194             etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1195     }
1196     /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1197     drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1198     /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1199     drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1200 
1201     etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1202     /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1203     drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1204     /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1205     drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1206     /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1207     drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1208     /*
1209      * LPOVERRIDE, bit[23] implementation supports
1210      * low-power state override
1211      */
1212     drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1213     /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1214     drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1215     /* NUMCNTR, bits[30:28] number of counters available for tracing */
1216     drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1217     etm4_cs_lock(drvdata, csa);
1218     cpu_detect_trace_filtering(drvdata);
1219 }
1220 
1221 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1222 {
1223     return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1224 }
1225 
1226 /* Set ELx trace filter access in the TRCVICTLR register */
1227 static void etm4_set_victlr_access(struct etmv4_config *config)
1228 {
1229     config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1230     config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1231 }
1232 
1233 static void etm4_set_default_config(struct etmv4_config *config)
1234 {
1235     /* disable all events tracing */
1236     config->eventctrl0 = 0x0;
1237     config->eventctrl1 = 0x0;
1238 
1239     /* disable stalling */
1240     config->stall_ctrl = 0x0;
1241 
1242     /* enable trace synchronization every 4096 bytes, if available */
1243     config->syncfreq = 0xC;
1244 
1245     /* disable timestamp event */
1246     config->ts_ctrl = 0x0;
1247 
1248     /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1249     config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1250 
1251     /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1252     etm4_set_victlr_access(config);
1253 }
1254 
1255 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1256 {
1257     u64 access_type = 0;
1258 
1259     /*
1260      * EXLEVEL_NS, for NonSecure Exception levels.
1261      * The mask here is a generic value and must be
1262      * shifted to the corresponding field for the registers
1263      */
1264     if (!is_kernel_in_hyp_mode()) {
1265         /* Stay away from hypervisor mode for non-VHE */
1266         access_type =  ETM_EXLEVEL_NS_HYP;
1267         if (config->mode & ETM_MODE_EXCL_KERN)
1268             access_type |= ETM_EXLEVEL_NS_OS;
1269     } else if (config->mode & ETM_MODE_EXCL_KERN) {
1270         access_type = ETM_EXLEVEL_NS_HYP;
1271     }
1272 
1273     if (config->mode & ETM_MODE_EXCL_USER)
1274         access_type |= ETM_EXLEVEL_NS_APP;
1275 
1276     return access_type;
1277 }
1278 
1279 /*
1280  * Construct the exception level masks for a given config.
1281  * This must be shifted to the corresponding register field
1282  * for usage.
1283  */
1284 static u64 etm4_get_access_type(struct etmv4_config *config)
1285 {
1286     /* All Secure exception levels are excluded from the trace */
1287     return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1288 }
1289 
1290 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1291 {
1292     return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1293 }
1294 
1295 static void etm4_set_comparator_filter(struct etmv4_config *config,
1296                        u64 start, u64 stop, int comparator)
1297 {
1298     u64 access_type = etm4_get_comparator_access_type(config);
1299 
1300     /* First half of default address comparator */
1301     config->addr_val[comparator] = start;
1302     config->addr_acc[comparator] = access_type;
1303     config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1304 
1305     /* Second half of default address comparator */
1306     config->addr_val[comparator + 1] = stop;
1307     config->addr_acc[comparator + 1] = access_type;
1308     config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1309 
1310     /*
1311      * Configure the ViewInst function to include this address range
1312      * comparator.
1313      *
1314      * @comparator is divided by two since it is the index in the
1315      * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1316      * address range comparator _pairs_.
1317      *
1318      * Therefore:
1319      *  index 0 -> compatator pair 0
1320      *  index 2 -> comparator pair 1
1321      *  index 4 -> comparator pair 2
1322      *  ...
1323      *  index 14 -> comparator pair 7
1324      */
1325     config->viiectlr |= BIT(comparator / 2);
1326 }
1327 
1328 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1329                        u64 address, int comparator,
1330                        enum etm_addr_type type)
1331 {
1332     int shift;
1333     u64 access_type = etm4_get_comparator_access_type(config);
1334 
1335     /* Configure the comparator */
1336     config->addr_val[comparator] = address;
1337     config->addr_acc[comparator] = access_type;
1338     config->addr_type[comparator] = type;
1339 
1340     /*
1341      * Configure ViewInst Start-Stop control register.
1342      * Addresses configured to start tracing go from bit 0 to n-1,
1343      * while those configured to stop tracing from 16 to 16 + n-1.
1344      */
1345     shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1346     config->vissctlr |= BIT(shift + comparator);
1347 }
1348 
1349 static void etm4_set_default_filter(struct etmv4_config *config)
1350 {
1351     /* Trace everything 'default' filter achieved by no filtering */
1352     config->viiectlr = 0x0;
1353 
1354     /*
1355      * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1356      * in the started state
1357      */
1358     config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1359     config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1360 
1361     /* No start-stop filtering for ViewInst */
1362     config->vissctlr = 0x0;
1363 }
1364 
1365 static void etm4_set_default(struct etmv4_config *config)
1366 {
1367     if (WARN_ON_ONCE(!config))
1368         return;
1369 
1370     /*
1371      * Make default initialisation trace everything
1372      *
1373      * This is done by a minimum default config sufficient to enable
1374      * full instruction trace - with a default filter for trace all
1375      * achieved by having no filtering.
1376      */
1377     etm4_set_default_config(config);
1378     etm4_set_default_filter(config);
1379 }
1380 
1381 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1382 {
1383     int nr_comparator, index = 0;
1384     struct etmv4_config *config = &drvdata->config;
1385 
1386     /*
1387      * nr_addr_cmp holds the number of comparator _pair_, so time 2
1388      * for the total number of comparators.
1389      */
1390     nr_comparator = drvdata->nr_addr_cmp * 2;
1391 
1392     /* Go through the tally of comparators looking for a free one. */
1393     while (index < nr_comparator) {
1394         switch (type) {
1395         case ETM_ADDR_TYPE_RANGE:
1396             if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1397                 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1398                 return index;
1399 
1400             /* Address range comparators go in pairs */
1401             index += 2;
1402             break;
1403         case ETM_ADDR_TYPE_START:
1404         case ETM_ADDR_TYPE_STOP:
1405             if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1406                 return index;
1407 
1408             /* Start/stop address can have odd indexes */
1409             index += 1;
1410             break;
1411         default:
1412             return -EINVAL;
1413         }
1414     }
1415 
1416     /* If we are here all the comparators have been used. */
1417     return -ENOSPC;
1418 }
1419 
1420 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1421                   struct perf_event *event)
1422 {
1423     int i, comparator, ret = 0;
1424     u64 address;
1425     struct etmv4_config *config = &drvdata->config;
1426     struct etm_filters *filters = event->hw.addr_filters;
1427 
1428     if (!filters)
1429         goto default_filter;
1430 
1431     /* Sync events with what Perf got */
1432     perf_event_addr_filters_sync(event);
1433 
1434     /*
1435      * If there are no filters to deal with simply go ahead with
1436      * the default filter, i.e the entire address range.
1437      */
1438     if (!filters->nr_filters)
1439         goto default_filter;
1440 
1441     for (i = 0; i < filters->nr_filters; i++) {
1442         struct etm_filter *filter = &filters->etm_filter[i];
1443         enum etm_addr_type type = filter->type;
1444 
1445         /* See if a comparator is free. */
1446         comparator = etm4_get_next_comparator(drvdata, type);
1447         if (comparator < 0) {
1448             ret = comparator;
1449             goto out;
1450         }
1451 
1452         switch (type) {
1453         case ETM_ADDR_TYPE_RANGE:
1454             etm4_set_comparator_filter(config,
1455                            filter->start_addr,
1456                            filter->stop_addr,
1457                            comparator);
1458             /*
1459              * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1460              * in the started state
1461              */
1462             config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1463 
1464             /* No start-stop filtering for ViewInst */
1465             config->vissctlr = 0x0;
1466             break;
1467         case ETM_ADDR_TYPE_START:
1468         case ETM_ADDR_TYPE_STOP:
1469             /* Get the right start or stop address */
1470             address = (type == ETM_ADDR_TYPE_START ?
1471                    filter->start_addr :
1472                    filter->stop_addr);
1473 
1474             /* Configure comparator */
1475             etm4_set_start_stop_filter(config, address,
1476                            comparator, type);
1477 
1478             /*
1479              * If filters::ssstatus == 1, trace acquisition was
1480              * started but the process was yanked away before the
1481              * the stop address was hit.  As such the start/stop
1482              * logic needs to be re-started so that tracing can
1483              * resume where it left.
1484              *
1485              * The start/stop logic status when a process is
1486              * scheduled out is checked in function
1487              * etm4_disable_perf().
1488              */
1489             if (filters->ssstatus)
1490                 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1491 
1492             /* No include/exclude filtering for ViewInst */
1493             config->viiectlr = 0x0;
1494             break;
1495         default:
1496             ret = -EINVAL;
1497             goto out;
1498         }
1499     }
1500 
1501     goto out;
1502 
1503 
1504 default_filter:
1505     etm4_set_default_filter(config);
1506 
1507 out:
1508     return ret;
1509 }
1510 
1511 void etm4_config_trace_mode(struct etmv4_config *config)
1512 {
1513     u32 mode;
1514 
1515     mode = config->mode;
1516     mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1517 
1518     /* excluding kernel AND user space doesn't make sense */
1519     WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1520 
1521     /* nothing to do if neither flags are set */
1522     if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1523         return;
1524 
1525     etm4_set_victlr_access(config);
1526 }
1527 
1528 static int etm4_online_cpu(unsigned int cpu)
1529 {
1530     if (!etmdrvdata[cpu])
1531         return 0;
1532 
1533     if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1534         coresight_enable(etmdrvdata[cpu]->csdev);
1535     return 0;
1536 }
1537 
1538 static int etm4_starting_cpu(unsigned int cpu)
1539 {
1540     if (!etmdrvdata[cpu])
1541         return 0;
1542 
1543     spin_lock(&etmdrvdata[cpu]->spinlock);
1544     if (!etmdrvdata[cpu]->os_unlock)
1545         etm4_os_unlock(etmdrvdata[cpu]);
1546 
1547     if (local_read(&etmdrvdata[cpu]->mode))
1548         etm4_enable_hw(etmdrvdata[cpu]);
1549     spin_unlock(&etmdrvdata[cpu]->spinlock);
1550     return 0;
1551 }
1552 
1553 static int etm4_dying_cpu(unsigned int cpu)
1554 {
1555     if (!etmdrvdata[cpu])
1556         return 0;
1557 
1558     spin_lock(&etmdrvdata[cpu]->spinlock);
1559     if (local_read(&etmdrvdata[cpu]->mode))
1560         etm4_disable_hw(etmdrvdata[cpu]);
1561     spin_unlock(&etmdrvdata[cpu]->spinlock);
1562     return 0;
1563 }
1564 
1565 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1566 {
1567     drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1568 }
1569 
1570 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1571 {
1572     int i, ret = 0;
1573     struct etmv4_save_state *state;
1574     struct coresight_device *csdev = drvdata->csdev;
1575     struct csdev_access *csa;
1576     struct device *etm_dev;
1577 
1578     if (WARN_ON(!csdev))
1579         return -ENODEV;
1580 
1581     etm_dev = &csdev->dev;
1582     csa = &csdev->access;
1583 
1584     /*
1585      * As recommended by 3.4.1 ("The procedure when powering down the PE")
1586      * of ARM IHI 0064D
1587      */
1588     dsb(sy);
1589     isb();
1590 
1591     etm4_cs_unlock(drvdata, csa);
1592     /* Lock the OS lock to disable trace and external debugger access */
1593     etm4_os_lock(drvdata);
1594 
1595     /* wait for TRCSTATR.PMSTABLE to go up */
1596     if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1597         dev_err(etm_dev,
1598             "timeout while waiting for PM Stable Status\n");
1599         etm4_os_unlock(drvdata);
1600         ret = -EBUSY;
1601         goto out;
1602     }
1603 
1604     state = drvdata->save_state;
1605 
1606     state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1607     if (drvdata->nr_pe)
1608         state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1609     state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1610     state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1611     state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1612     state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1613     if (drvdata->stallctl)
1614         state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1615     state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1616     state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1617     state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1618     state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1619     state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1620     state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1621 
1622     state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1623     state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1624     state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1625     if (drvdata->nr_pe_cmp)
1626         state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1627     state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1628     state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1629     state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1630 
1631     for (i = 0; i < drvdata->nrseqstate - 1; i++)
1632         state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1633 
1634     state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1635     state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1636     state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1637 
1638     for (i = 0; i < drvdata->nr_cntr; i++) {
1639         state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1640         state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1641         state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1642     }
1643 
1644     for (i = 0; i < drvdata->nr_resource * 2; i++)
1645         state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1646 
1647     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1648         state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1649         state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1650         if (etm4x_sspcicrn_present(drvdata, i))
1651             state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1652     }
1653 
1654     for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1655         state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1656         state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1657     }
1658 
1659     /*
1660      * Data trace stream is architecturally prohibited for A profile cores
1661      * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1662      * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1663      * unit") of ARM IHI 0064D.
1664      */
1665 
1666     for (i = 0; i < drvdata->numcidc; i++)
1667         state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1668 
1669     for (i = 0; i < drvdata->numvmidc; i++)
1670         state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1671 
1672     state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1673     if (drvdata->numcidc > 4)
1674         state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1675 
1676     state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1677     if (drvdata->numvmidc > 4)
1678         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1679 
1680     state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1681 
1682     if (!drvdata->skip_power_up)
1683         state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1684 
1685     /* wait for TRCSTATR.IDLE to go up */
1686     if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1687         dev_err(etm_dev,
1688             "timeout while waiting for Idle Trace Status\n");
1689         etm4_os_unlock(drvdata);
1690         ret = -EBUSY;
1691         goto out;
1692     }
1693 
1694     drvdata->state_needs_restore = true;
1695 
1696     /*
1697      * Power can be removed from the trace unit now. We do this to
1698      * potentially save power on systems that respect the TRCPDCR_PU
1699      * despite requesting software to save/restore state.
1700      */
1701     if (!drvdata->skip_power_up)
1702         etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1703                       TRCPDCR);
1704 out:
1705     etm4_cs_lock(drvdata, csa);
1706     return ret;
1707 }
1708 
1709 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1710 {
1711     int ret = 0;
1712 
1713     /* Save the TRFCR irrespective of whether the ETM is ON */
1714     if (drvdata->trfcr)
1715         drvdata->save_trfcr = read_trfcr();
1716     /*
1717      * Save and restore the ETM Trace registers only if
1718      * the ETM is active.
1719      */
1720     if (local_read(&drvdata->mode) && drvdata->save_state)
1721         ret = __etm4_cpu_save(drvdata);
1722     return ret;
1723 }
1724 
1725 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1726 {
1727     int i;
1728     struct etmv4_save_state *state = drvdata->save_state;
1729     struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1730     struct csdev_access *csa = &tmp_csa;
1731 
1732     etm4_cs_unlock(drvdata, csa);
1733     etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1734 
1735     etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1736     if (drvdata->nr_pe)
1737         etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1738     etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1739     etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1740     etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1741     etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1742     if (drvdata->stallctl)
1743         etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1744     etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1745     etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1746     etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1747     etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1748     etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1749     etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1750 
1751     etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1752     etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1753     etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1754     if (drvdata->nr_pe_cmp)
1755         etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1756     etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1757     etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1758     etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1759 
1760     for (i = 0; i < drvdata->nrseqstate - 1; i++)
1761         etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1762 
1763     etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1764     etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1765     etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1766 
1767     for (i = 0; i < drvdata->nr_cntr; i++) {
1768         etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1769         etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1770         etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1771     }
1772 
1773     for (i = 0; i < drvdata->nr_resource * 2; i++)
1774         etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1775 
1776     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1777         etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1778         etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1779         if (etm4x_sspcicrn_present(drvdata, i))
1780             etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1781     }
1782 
1783     for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1784         etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1785         etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1786     }
1787 
1788     for (i = 0; i < drvdata->numcidc; i++)
1789         etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1790 
1791     for (i = 0; i < drvdata->numvmidc; i++)
1792         etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1793 
1794     etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1795     if (drvdata->numcidc > 4)
1796         etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1797 
1798     etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1799     if (drvdata->numvmidc > 4)
1800         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1801 
1802     etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1803 
1804     if (!drvdata->skip_power_up)
1805         etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1806 
1807     drvdata->state_needs_restore = false;
1808 
1809     /*
1810      * As recommended by section 4.3.7 ("Synchronization when using the
1811      * memory-mapped interface") of ARM IHI 0064D
1812      */
1813     dsb(sy);
1814     isb();
1815 
1816     /* Unlock the OS lock to re-enable trace and external debug access */
1817     etm4_os_unlock(drvdata);
1818     etm4_cs_lock(drvdata, csa);
1819 }
1820 
1821 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1822 {
1823     if (drvdata->trfcr)
1824         write_trfcr(drvdata->save_trfcr);
1825     if (drvdata->state_needs_restore)
1826         __etm4_cpu_restore(drvdata);
1827 }
1828 
1829 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1830                   void *v)
1831 {
1832     struct etmv4_drvdata *drvdata;
1833     unsigned int cpu = smp_processor_id();
1834 
1835     if (!etmdrvdata[cpu])
1836         return NOTIFY_OK;
1837 
1838     drvdata = etmdrvdata[cpu];
1839 
1840     if (WARN_ON_ONCE(drvdata->cpu != cpu))
1841         return NOTIFY_BAD;
1842 
1843     switch (cmd) {
1844     case CPU_PM_ENTER:
1845         if (etm4_cpu_save(drvdata))
1846             return NOTIFY_BAD;
1847         break;
1848     case CPU_PM_EXIT:
1849     case CPU_PM_ENTER_FAILED:
1850         etm4_cpu_restore(drvdata);
1851         break;
1852     default:
1853         return NOTIFY_DONE;
1854     }
1855 
1856     return NOTIFY_OK;
1857 }
1858 
1859 static struct notifier_block etm4_cpu_pm_nb = {
1860     .notifier_call = etm4_cpu_pm_notify,
1861 };
1862 
1863 /* Setup PM. Deals with error conditions and counts */
1864 static int __init etm4_pm_setup(void)
1865 {
1866     int ret;
1867 
1868     ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1869     if (ret)
1870         return ret;
1871 
1872     ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1873                     "arm/coresight4:starting",
1874                     etm4_starting_cpu, etm4_dying_cpu);
1875 
1876     if (ret)
1877         goto unregister_notifier;
1878 
1879     ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1880                     "arm/coresight4:online",
1881                     etm4_online_cpu, NULL);
1882 
1883     /* HP dyn state ID returned in ret on success */
1884     if (ret > 0) {
1885         hp_online = ret;
1886         return 0;
1887     }
1888 
1889     /* failed dyn state - remove others */
1890     cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1891 
1892 unregister_notifier:
1893     cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1894     return ret;
1895 }
1896 
1897 static void etm4_pm_clear(void)
1898 {
1899     cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1900     cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1901     if (hp_online) {
1902         cpuhp_remove_state_nocalls(hp_online);
1903         hp_online = 0;
1904     }
1905 }
1906 
1907 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1908 {
1909     int ret;
1910     struct coresight_platform_data *pdata = NULL;
1911     struct etmv4_drvdata *drvdata;
1912     struct coresight_desc desc = { 0 };
1913     struct etm4_init_arg init_arg = { 0 };
1914     u8 major, minor;
1915     char *type_name;
1916 
1917     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1918     if (!drvdata)
1919         return -ENOMEM;
1920 
1921     dev_set_drvdata(dev, drvdata);
1922 
1923     if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1924         pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1925                    PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1926 
1927     if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1928         drvdata->save_state = devm_kmalloc(dev,
1929                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1930         if (!drvdata->save_state)
1931             return -ENOMEM;
1932     }
1933 
1934     drvdata->base = base;
1935 
1936     spin_lock_init(&drvdata->spinlock);
1937 
1938     drvdata->cpu = coresight_get_cpu(dev);
1939     if (drvdata->cpu < 0)
1940         return drvdata->cpu;
1941 
1942     init_arg.drvdata = drvdata;
1943     init_arg.csa = &desc.access;
1944     init_arg.pid = etm_pid;
1945 
1946     if (smp_call_function_single(drvdata->cpu,
1947                 etm4_init_arch_data,  &init_arg, 1))
1948         dev_err(dev, "ETM arch init failed\n");
1949 
1950     if (!drvdata->arch)
1951         return -EINVAL;
1952 
1953     /* TRCPDCR is not accessible with system instructions. */
1954     if (!desc.access.io_mem ||
1955         fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1956         drvdata->skip_power_up = true;
1957 
1958     major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1959     minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1960 
1961     if (etm4x_is_ete(drvdata)) {
1962         type_name = "ete";
1963         /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1964         major -= 4;
1965     } else {
1966         type_name = "etm";
1967     }
1968 
1969     desc.name = devm_kasprintf(dev, GFP_KERNEL,
1970                    "%s%d", type_name, drvdata->cpu);
1971     if (!desc.name)
1972         return -ENOMEM;
1973 
1974     etm4_init_trace_id(drvdata);
1975     etm4_set_default(&drvdata->config);
1976 
1977     pdata = coresight_get_platform_data(dev);
1978     if (IS_ERR(pdata))
1979         return PTR_ERR(pdata);
1980 
1981     dev->platform_data = pdata;
1982 
1983     desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1984     desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1985     desc.ops = &etm4_cs_ops;
1986     desc.pdata = pdata;
1987     desc.dev = dev;
1988     desc.groups = coresight_etmv4_groups;
1989     drvdata->csdev = coresight_register(&desc);
1990     if (IS_ERR(drvdata->csdev))
1991         return PTR_ERR(drvdata->csdev);
1992 
1993     ret = etm_perf_symlink(drvdata->csdev, true);
1994     if (ret) {
1995         coresight_unregister(drvdata->csdev);
1996         return ret;
1997     }
1998 
1999     /* register with config infrastructure & load any current features */
2000     ret = etm4_cscfg_register(drvdata->csdev);
2001     if (ret) {
2002         coresight_unregister(drvdata->csdev);
2003         return ret;
2004     }
2005 
2006     etmdrvdata[drvdata->cpu] = drvdata;
2007 
2008     dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2009          drvdata->cpu, type_name, major, minor);
2010 
2011     if (boot_enable) {
2012         coresight_enable(drvdata->csdev);
2013         drvdata->boot_enable = true;
2014     }
2015 
2016     return 0;
2017 }
2018 
2019 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2020 {
2021     void __iomem *base;
2022     struct device *dev = &adev->dev;
2023     struct resource *res = &adev->res;
2024     int ret;
2025 
2026     /* Validity for the resource is already checked by the AMBA core */
2027     base = devm_ioremap_resource(dev, res);
2028     if (IS_ERR(base))
2029         return PTR_ERR(base);
2030 
2031     ret = etm4_probe(dev, base, id->id);
2032     if (!ret)
2033         pm_runtime_put(&adev->dev);
2034 
2035     return ret;
2036 }
2037 
2038 static int etm4_probe_platform_dev(struct platform_device *pdev)
2039 {
2040     int ret;
2041 
2042     pm_runtime_get_noresume(&pdev->dev);
2043     pm_runtime_set_active(&pdev->dev);
2044     pm_runtime_enable(&pdev->dev);
2045 
2046     /*
2047      * System register based devices could match the
2048      * HW by reading appropriate registers on the HW
2049      * and thus we could skip the PID.
2050      */
2051     ret = etm4_probe(&pdev->dev, NULL, 0);
2052 
2053     pm_runtime_put(&pdev->dev);
2054     return ret;
2055 }
2056 
2057 static struct amba_cs_uci_id uci_id_etm4[] = {
2058     {
2059         /*  ETMv4 UCI data */
2060         .devarch    = ETM_DEVARCH_ETMv4x_ARCH,
2061         .devarch_mask   = ETM_DEVARCH_ID_MASK,
2062         .devtype    = 0x00000013,
2063     }
2064 };
2065 
2066 static void clear_etmdrvdata(void *info)
2067 {
2068     int cpu = *(int *)info;
2069 
2070     etmdrvdata[cpu] = NULL;
2071 }
2072 
2073 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2074 {
2075     etm_perf_symlink(drvdata->csdev, false);
2076     /*
2077      * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2078      * and CPU hotplug call backs.
2079      */
2080     cpus_read_lock();
2081     /*
2082      * The readers for etmdrvdata[] are CPU hotplug call backs
2083      * and PM notification call backs. Change etmdrvdata[i] on
2084      * CPU i ensures these call backs has consistent view
2085      * inside one call back function.
2086      */
2087     if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2088         etmdrvdata[drvdata->cpu] = NULL;
2089 
2090     cpus_read_unlock();
2091 
2092     cscfg_unregister_csdev(drvdata->csdev);
2093     coresight_unregister(drvdata->csdev);
2094 
2095     return 0;
2096 }
2097 
2098 static void __exit etm4_remove_amba(struct amba_device *adev)
2099 {
2100     struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2101 
2102     if (drvdata)
2103         etm4_remove_dev(drvdata);
2104 }
2105 
2106 static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2107 {
2108     int ret = 0;
2109     struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2110 
2111     if (drvdata)
2112         ret = etm4_remove_dev(drvdata);
2113     pm_runtime_disable(&pdev->dev);
2114     return ret;
2115 }
2116 
2117 static const struct amba_id etm4_ids[] = {
2118     CS_AMBA_ID(0x000bb95d),         /* Cortex-A53 */
2119     CS_AMBA_ID(0x000bb95e),         /* Cortex-A57 */
2120     CS_AMBA_ID(0x000bb95a),         /* Cortex-A72 */
2121     CS_AMBA_ID(0x000bb959),         /* Cortex-A73 */
2122     CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2123     CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2124     CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2125     CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2126     CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2127     CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2128     CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2129     CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2130     CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2131     CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2132     CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2133     CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2134     CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2135     CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2136     CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2137     {},
2138 };
2139 
2140 MODULE_DEVICE_TABLE(amba, etm4_ids);
2141 
2142 static struct amba_driver etm4x_amba_driver = {
2143     .drv = {
2144         .name   = "coresight-etm4x",
2145         .owner  = THIS_MODULE,
2146         .suppress_bind_attrs = true,
2147     },
2148     .probe      = etm4_probe_amba,
2149     .remove         = etm4_remove_amba,
2150     .id_table   = etm4_ids,
2151 };
2152 
2153 static const struct of_device_id etm4_sysreg_match[] = {
2154     { .compatible   = "arm,coresight-etm4x-sysreg" },
2155     { .compatible   = "arm,embedded-trace-extension" },
2156     {}
2157 };
2158 
2159 static struct platform_driver etm4_platform_driver = {
2160     .probe      = etm4_probe_platform_dev,
2161     .remove     = etm4_remove_platform_dev,
2162     .driver         = {
2163         .name           = "coresight-etm4x",
2164         .of_match_table     = etm4_sysreg_match,
2165         .suppress_bind_attrs    = true,
2166     },
2167 };
2168 
2169 static int __init etm4x_init(void)
2170 {
2171     int ret;
2172 
2173     ret = etm4_pm_setup();
2174 
2175     /* etm4_pm_setup() does its own cleanup - exit on error */
2176     if (ret)
2177         return ret;
2178 
2179     ret = amba_driver_register(&etm4x_amba_driver);
2180     if (ret) {
2181         pr_err("Error registering etm4x AMBA driver\n");
2182         goto clear_pm;
2183     }
2184 
2185     ret = platform_driver_register(&etm4_platform_driver);
2186     if (!ret)
2187         return 0;
2188 
2189     pr_err("Error registering etm4x platform driver\n");
2190     amba_driver_unregister(&etm4x_amba_driver);
2191 
2192 clear_pm:
2193     etm4_pm_clear();
2194     return ret;
2195 }
2196 
2197 static void __exit etm4x_exit(void)
2198 {
2199     amba_driver_unregister(&etm4x_amba_driver);
2200     platform_driver_unregister(&etm4_platform_driver);
2201     etm4_pm_clear();
2202 }
2203 
2204 module_init(etm4x_init);
2205 module_exit(etm4x_exit);
2206 
2207 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2208 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2209 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2210 MODULE_LICENSE("GPL v2");
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