hwtracing/coresight/coresight-etm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _CORESIGHT_CORESIGHT_ETM_H
0007 #define _CORESIGHT_CORESIGHT_ETM_H
0008
0009 #include <asm/local.h>
0010 #include <linux/spinlock.h>
0011 #include "coresight-priv.h"
0012
0013 /*
0014  * Device registers:
0015  * 0x000 - 0x2FC: Trace         registers
0016  * 0x300 - 0x314: Management    registers
0017  * 0x318 - 0xEFC: Trace         registers
0018  *
0019  * Coresight registers
0020  * 0xF00 - 0xF9C: Management    registers
0021  * 0xFA0 - 0xFA4: Management    registers in PFTv1.0
0022  *                Trace         registers in PFTv1.1
0023  * 0xFA8 - 0xFFC: Management    registers
0024  */
0025
0026 /* Trace registers (0x000-0x2FC) */
0027 #define ETMCR           0x000
0028 #define ETMCCR          0x004
0029 #define ETMTRIGGER      0x008
0030 #define ETMSR           0x010
0031 #define ETMSCR          0x014
0032 #define ETMTSSCR        0x018
0033 #define ETMTECR2        0x01c
0034 #define ETMTEEVR        0x020
0035 #define ETMTECR1        0x024
0036 #define ETMFFLR         0x02c
0037 #define ETMACVRn(n)     (0x040 + (n * 4))
0038 #define ETMACTRn(n)     (0x080 + (n * 4))
0039 #define ETMCNTRLDVRn(n)     (0x140 + (n * 4))
0040 #define ETMCNTENRn(n)       (0x150 + (n * 4))
0041 #define ETMCNTRLDEVRn(n)    (0x160 + (n * 4))
0042 #define ETMCNTVRn(n)        (0x170 + (n * 4))
0043 #define ETMSQ12EVR      0x180
0044 #define ETMSQ21EVR      0x184
0045 #define ETMSQ23EVR      0x188
0046 #define ETMSQ31EVR      0x18c
0047 #define ETMSQ32EVR      0x190
0048 #define ETMSQ13EVR      0x194
0049 #define ETMSQR          0x19c
0050 #define ETMEXTOUTEVRn(n)    (0x1a0 + (n * 4))
0051 #define ETMCIDCVRn(n)       (0x1b0 + (n * 4))
0052 #define ETMCIDCMR       0x1bc
0053 #define ETMIMPSPEC0     0x1c0
0054 #define ETMIMPSPEC1     0x1c4
0055 #define ETMIMPSPEC2     0x1c8
0056 #define ETMIMPSPEC3     0x1cc
0057 #define ETMIMPSPEC4     0x1d0
0058 #define ETMIMPSPEC5     0x1d4
0059 #define ETMIMPSPEC6     0x1d8
0060 #define ETMIMPSPEC7     0x1dc
0061 #define ETMSYNCFR       0x1e0
0062 #define ETMIDR          0x1e4
0063 #define ETMCCER         0x1e8
0064 #define ETMEXTINSELR        0x1ec
0065 #define ETMTESSEICR     0x1f0
0066 #define ETMEIBCR        0x1f4
0067 #define ETMTSEVR        0x1f8
0068 #define ETMAUXCR        0x1fc
0069 #define ETMTRACEIDR     0x200
0070 #define ETMVMIDCVR      0x240
0071 /* Management registers (0x300-0x314) */
0072 #define ETMOSLAR        0x300
0073 #define ETMOSLSR        0x304
0074 #define ETMOSSRR        0x308
0075 #define ETMPDCR         0x310
0076 #define ETMPDSR         0x314
0077 #define ETM_MAX_ADDR_CMP    16
0078 #define ETM_MAX_CNTR        4
0079 #define ETM_MAX_CTXID_CMP   3
0080
0081 /* Register definition */
0082 /* ETMCR - 0x00 */
0083 #define ETMCR_PWD_DWN       BIT(0)
0084 #define ETMCR_STALL_MODE    BIT(7)
0085 #define ETMCR_BRANCH_BROADCAST  BIT(8)
0086 #define ETMCR_ETM_PRG       BIT(10)
0087 #define ETMCR_ETM_EN        BIT(11)
0088 #define ETMCR_CYC_ACC       BIT(12)
0089 #define ETMCR_CTXID_SIZE    (BIT(14)|BIT(15))
0090 #define ETMCR_TIMESTAMP_EN  BIT(28)
0091 #define ETMCR_RETURN_STACK  BIT(29)
0092 /* ETMCCR - 0x04 */
0093 #define ETMCCR_FIFOFULL     BIT(23)
0094 /* ETMPDCR - 0x310 */
0095 #define ETMPDCR_PWD_UP      BIT(3)
0096 /* ETMTECR1 - 0x024 */
0097 #define ETMTECR1_ADDR_COMP_1    BIT(0)
0098 #define ETMTECR1_INC_EXC    BIT(24)
0099 #define ETMTECR1_START_STOP BIT(25)
0100 /* ETMCCER - 0x1E8 */
0101 #define ETMCCER_TIMESTAMP   BIT(22)
0102 #define ETMCCER_RETSTACK    BIT(23)
0103
0104 #define ETM_MODE_EXCLUDE    BIT(0)
0105 #define ETM_MODE_CYCACC     BIT(1)
0106 #define ETM_MODE_STALL      BIT(2)
0107 #define ETM_MODE_TIMESTAMP  BIT(3)
0108 #define ETM_MODE_CTXID      BIT(4)
0109 #define ETM_MODE_BBROAD     BIT(5)
0110 #define ETM_MODE_RET_STACK  BIT(6)
0111 #define ETM_MODE_ALL        (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \
0112                  ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \
0113                  ETM_MODE_BBROAD | ETM_MODE_RET_STACK | \
0114                  ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \
0115                  ETM_MODE_EXCL_USER)
0116
0117 #define ETM_SQR_MASK        0x3
0118 #define ETM_TRACEID_MASK    0x3f
0119 #define ETM_EVENT_MASK      0x1ffff
0120 #define ETM_SYNC_MASK       0xfff
0121 #define ETM_ALL_MASK        0xffffffff
0122
0123 #define ETMSR_PROG_BIT      1
0124 #define ETM_SEQ_STATE_MAX_VAL   (0x2)
0125 #define PORT_SIZE_MASK      (GENMASK(21, 21) | GENMASK(6, 4))
0126
0127 #define ETM_HARD_WIRE_RES_A /* Hard wired, always true */   \
0128                 ((0x0f << 0)    |       \
0129                 /* Resource index A */      \
0130                 (0x06 << 4))
0131
0132 #define ETM_ADD_COMP_0      /* Single addr comparator 1 */  \
0133                 ((0x00 << 7)    |       \
0134                 /* Resource index B */      \
0135                 (0x00 << 11))
0136
0137 #define ETM_EVENT_NOT_A     BIT(14) /* NOT(A) */
0138
0139 #define ETM_DEFAULT_EVENT_VAL   (ETM_HARD_WIRE_RES_A    |   \
0140                  ETM_ADD_COMP_0     |   \
0141                  ETM_EVENT_NOT_A)
0142
0143 /**
0144  * struct etm_config - configuration information related to an ETM
0145  * @mode:   controls various modes supported by this ETM/PTM.
0146  * @ctrl:   used in conjunction with @mode.
0147  * @trigger_event: setting for register ETMTRIGGER.
0148  * @startstop_ctrl: setting for register ETMTSSCR.
0149  * @enable_event: setting for register ETMTEEVR.
0150  * @enable_ctrl1: setting for register ETMTECR1.
0151  * @enable_ctrl2: setting for register ETMTECR2.
0152  * @fifofull_level: setting for register ETMFFLR.
0153  * @addr_idx:   index for the address comparator selection.
0154  * @addr_val:   value for address comparator register.
0155  * @addr_acctype: access type for address comparator register.
0156  * @addr_type:  current status of the comparator register.
0157  * @cntr_idx:   index for the counter register selection.
0158  * @cntr_rld_val: reload value of a counter register.
0159  * @cntr_event: control for counter enable register.
0160  * @cntr_rld_event: value for counter reload event register.
0161  * @cntr_val:   counter value register.
0162  * @seq_12_event: event causing the transition from 1 to 2.
0163  * @seq_21_event: event causing the transition from 2 to 1.
0164  * @seq_23_event: event causing the transition from 2 to 3.
0165  * @seq_31_event: event causing the transition from 3 to 1.
0166  * @seq_32_event: event causing the transition from 3 to 2.
0167  * @seq_13_event: event causing the transition from 1 to 3.
0168  * @seq_curr_state: current value of the sequencer register.
0169  * @ctxid_idx: index for the context ID registers.
0170  * @ctxid_pid: value for the context ID to trigger on.
0171  * @ctxid_mask: mask applicable to all the context IDs.
0172  * @sync_freq:  Synchronisation frequency.
0173  * @timestamp_event: Defines an event that requests the insertion
0174  *           of a timestamp into the trace stream.
0175  */
0176 struct etm_config {
0177     u32             mode;
0178     u32             ctrl;
0179     u32             trigger_event;
0180     u32             startstop_ctrl;
0181     u32             enable_event;
0182     u32             enable_ctrl1;
0183     u32             enable_ctrl2;
0184     u32             fifofull_level;
0185     u8              addr_idx;
0186     u32             addr_val[ETM_MAX_ADDR_CMP];
0187     u32             addr_acctype[ETM_MAX_ADDR_CMP];
0188     u32             addr_type[ETM_MAX_ADDR_CMP];
0189     u8              cntr_idx;
0190     u32             cntr_rld_val[ETM_MAX_CNTR];
0191     u32             cntr_event[ETM_MAX_CNTR];
0192     u32             cntr_rld_event[ETM_MAX_CNTR];
0193     u32             cntr_val[ETM_MAX_CNTR];
0194     u32             seq_12_event;
0195     u32             seq_21_event;
0196     u32             seq_23_event;
0197     u32             seq_31_event;
0198     u32             seq_32_event;
0199     u32             seq_13_event;
0200     u32             seq_curr_state;
0201     u8              ctxid_idx;
0202     u32             ctxid_pid[ETM_MAX_CTXID_CMP];
0203     u32             ctxid_mask;
0204     u32             sync_freq;
0205     u32             timestamp_event;
0206 };
0207
0208 /**
0209  * struct etm_drvdata - specifics associated to an ETM component
0210  * @base:   memory mapped base address for this component.
0211  * @atclk:  optional clock for the core parts of the ETM.
0212  * @csdev:  component vitals needed by the framework.
0213  * @spinlock:   only one at a time pls.
0214  * @cpu:    the cpu this component is affined to.
0215  * @port_size:  port size as reported by ETMCR bit 4-6 and 21.
0216  * @arch:   ETM/PTM version number.
0217  * @use_cpu14:  true if management registers need to be accessed via CP14.
0218  * @mode:   this tracer's mode, i.e sysFS, Perf or disabled.
0219  * @sticky_enable: true if ETM base configuration has been done.
0220  * @boot_enable:true if we should start tracing at boot time.
0221  * @os_unlock:  true if access to management registers is allowed.
0222  * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
0223  * @nr_cntr:    Number of counters as found in ETMCCR bit 13-15.
0224  * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
0225  * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
0226  * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
0227  * @etmccr: value of register ETMCCR.
0228  * @etmccer:    value of register ETMCCER.
0229  * @traceid:    value of the current ID for this component.
0230  * @config: structure holding configuration parameters.
0231  */
0232 struct etm_drvdata {
0233     void __iomem            *base;
0234     struct clk          *atclk;
0235     struct coresight_device     *csdev;
0236     spinlock_t          spinlock;
0237     int             cpu;
0238     int             port_size;
0239     u8              arch;
0240     bool                use_cp14;
0241     local_t             mode;
0242     bool                sticky_enable;
0243     bool                boot_enable;
0244     bool                os_unlock;
0245     u8              nr_addr_cmp;
0246     u8              nr_cntr;
0247     u8              nr_ext_inp;
0248     u8              nr_ext_out;
0249     u8              nr_ctxid_cmp;
0250     u32             etmccr;
0251     u32             etmccer;
0252     u32             traceid;
0253     struct etm_config       config;
0254 };
0255
0256 static inline void etm_writel(struct etm_drvdata *drvdata,
0257                   u32 val, u32 off)
0258 {
0259     if (drvdata->use_cp14) {
0260         if (etm_writel_cp14(off, val)) {
0261             dev_err(&drvdata->csdev->dev,
0262                 "invalid CP14 access to ETM reg: %#x", off);
0263         }
0264     } else {
0265         writel_relaxed(val, drvdata->base + off);
0266     }
0267 }
0268
0269 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
0270 {
0271     u32 val;
0272
0273     if (drvdata->use_cp14) {
0274         if (etm_readl_cp14(off, &val)) {
0275             dev_err(&drvdata->csdev->dev,
0276                 "invalid CP14 access to ETM reg: %#x", off);
0277         }
0278     } else {
0279         val = readl_relaxed(drvdata->base + off);
0280     }
0281
0282     return val;
0283 }
0284
0285 extern const struct attribute_group *coresight_etm_groups[];
0286 int etm_get_trace_id(struct etm_drvdata *drvdata);
0287 void etm_set_default(struct etm_config *config);
0288 void etm_config_trace_mode(struct etm_config *config);
0289 struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
0290 #endif