hwtracing/coresight/coresight-cti.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018 Linaro Limited, All rights reserved.
0004  * Author: Mike Leach <mike.leach@linaro.org>
0005  */
0006
0007 #ifndef _CORESIGHT_CORESIGHT_CTI_H
0008 #define _CORESIGHT_CORESIGHT_CTI_H
0009
0010 #include <linux/coresight.h>
0011 #include <linux/device.h>
0012 #include <linux/fwnode.h>
0013 #include <linux/list.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/types.h>
0017
0018 #include "coresight-priv.h"
0019
0020 /*
0021  * Device registers
0022  * 0x000 - 0x144: CTI programming and status
0023  * 0xEDC - 0xEF8: CTI integration test.
0024  * 0xF00 - 0xFFC: Coresight management registers.
0025  */
0026 /* CTI programming registers */
0027 #define CTICONTROL      0x000
0028 #define CTIINTACK       0x010
0029 #define CTIAPPSET       0x014
0030 #define CTIAPPCLEAR     0x018
0031 #define CTIAPPPULSE     0x01C
0032 #define CTIINEN(n)      (0x020 + (4 * n))
0033 #define CTIOUTEN(n)     (0x0A0 + (4 * n))
0034 #define CTITRIGINSTATUS     0x130
0035 #define CTITRIGOUTSTATUS    0x134
0036 #define CTICHINSTATUS       0x138
0037 #define CTICHOUTSTATUS      0x13C
0038 #define CTIGATE         0x140
0039 #define ASICCTL         0x144
0040 /* Integration test registers */
0041 #define ITCHINACK       0xEDC /* WO CTI CSSoc 400 only*/
0042 #define ITTRIGINACK     0xEE0 /* WO CTI CSSoc 400 only*/
0043 #define ITCHOUT         0xEE4 /* WO RW-600 */
0044 #define ITTRIGOUT       0xEE8 /* WO RW-600 */
0045 #define ITCHOUTACK      0xEEC /* RO CTI CSSoc 400 only*/
0046 #define ITTRIGOUTACK        0xEF0 /* RO CTI CSSoc 400 only*/
0047 #define ITCHIN          0xEF4 /* RO */
0048 #define ITTRIGIN        0xEF8 /* RO */
0049 /* management registers */
0050 #define CTIDEVAFF0      0xFA8
0051 #define CTIDEVAFF1      0xFAC
0052
0053 /*
0054  * CTI CSSoc 600 has a max of 32 trigger signals per direction.
0055  * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
0056  * Max of in and out defined in the DEVID register.
0057  * - pick up actual number used from .dts parameters if present.
0058  */
0059 #define CTIINOUTEN_MAX      32
0060
0061 /**
0062  * Group of related trigger signals
0063  *
0064  * @nr_sigs: number of signals in the group.
0065  * @used_mask: bitmask representing the signal indexes in the group.
0066  * @sig_types: array of types for the signals, length nr_sigs.
0067  */
0068 struct cti_trig_grp {
0069     int nr_sigs;
0070     u32 used_mask;
0071     int sig_types[];
0072 };
0073
0074 /**
0075  * Trigger connection - connection between a CTI and other (coresight) device
0076  * lists input and output trigger signals for the device
0077  *
0078  * @con_in: connected CTIIN signals for the device.
0079  * @con_out: connected CTIOUT signals for the device.
0080  * @con_dev: coresight device connected to the CTI, NULL if not CS device
0081  * @con_dev_name: name of connected device (CS or CPU)
0082  * @node: entry node in list of connections.
0083  * @con_attrs: Dynamic sysfs attributes specific to this connection.
0084  * @attr_group: Dynamic attribute group created for this connection.
0085  */
0086 struct cti_trig_con {
0087     struct cti_trig_grp *con_in;
0088     struct cti_trig_grp *con_out;
0089     struct coresight_device *con_dev;
0090     const char *con_dev_name;
0091     struct list_head node;
0092     struct attribute **con_attrs;
0093     struct attribute_group *attr_group;
0094 };
0095
0096 /**
0097  * struct cti_device - description of CTI device properties.
0098  *
0099  * @nt_trig_con: Number of external devices connected to this device.
0100  * @ctm_id: which CTM this device is connected to (by default it is
0101  *          assumed there is a single CTM per SoC, ID 0).
0102  * @trig_cons: list of connections to this device.
0103  * @cpu: CPU ID if associated with CPU, -1 otherwise.
0104  * @con_groups: combined static and dynamic sysfs groups for trigger
0105  *      connections.
0106  */
0107 struct cti_device {
0108     int nr_trig_con;
0109     u32 ctm_id;
0110     struct list_head trig_cons;
0111     int cpu;
0112     const struct attribute_group **con_groups;
0113 };
0114
0115 /**
0116  * struct cti_config - configuration of the CTI device hardware
0117  *
0118  * @nr_trig_max: Max number of trigger signals implemented on device.
0119  *       (max of trig_in or trig_out) - from ID register.
0120  * @nr_ctm_channels: number of available CTM channels - from ID register.
0121  * @enable_req_count: CTI is enabled alongside >=1 associated devices.
0122  * @hw_enabled: true if hw is currently enabled.
0123  * @hw_powered: true if associated cpu powered on, or no cpu.
0124  * @trig_in_use: bitfield of in triggers registered as in use.
0125  * @trig_out_use: bitfield of out triggers registered as in use.
0126  * @trig_out_filter: bitfield of out triggers that are blocked if filter
0127  *           enabled. Typically this would be dbgreq / restart on
0128  *           a core CTI.
0129  * @trig_filter_enable: 1 if filtering enabled.
0130  * @xtrig_rchan_sel: channel selection for xtrigger connection show.
0131  * @ctiappset: CTI Software application channel set.
0132  * @ctiinout_sel: register selector for INEN and OUTEN regs.
0133  * @ctiinen: enable input trigger to a channel.
0134  * @ctiouten: enable output trigger from a channel.
0135  * @ctigate: gate channel output from CTI to CTM.
0136  * @asicctl: asic control register.
0137  */
0138 struct cti_config {
0139     /* hardware description */
0140     int nr_ctm_channels;
0141     int nr_trig_max;
0142
0143     /* cti enable control */
0144     atomic_t enable_req_count;
0145     bool hw_enabled;
0146     bool hw_powered;
0147
0148     /* registered triggers and filtering */
0149     u32 trig_in_use;
0150     u32 trig_out_use;
0151     u32 trig_out_filter;
0152     bool trig_filter_enable;
0153     u8 xtrig_rchan_sel;
0154
0155     /* cti cross trig programmable regs */
0156     u32 ctiappset;
0157     u8 ctiinout_sel;
0158     u32 ctiinen[CTIINOUTEN_MAX];
0159     u32 ctiouten[CTIINOUTEN_MAX];
0160     u32 ctigate;
0161     u32 asicctl;
0162 };
0163
0164 /**
0165  * struct cti_drvdata - specifics for the CTI device
0166  * @base:   Memory mapped base address for this component..
0167  * @csdev:  Standard CoreSight device information.
0168  * @ctidev: Extra information needed by the CTI/CTM framework.
0169  * @spinlock:   Control data access to one at a time.
0170  * @config: Configuration data for this CTI device.
0171  * @node:   List entry of this device in the list of CTI devices.
0172  * @csdev_release: release function for underlying coresight_device.
0173  */
0174 struct cti_drvdata {
0175     void __iomem *base;
0176     struct coresight_device *csdev;
0177     struct cti_device ctidev;
0178     spinlock_t spinlock;
0179     struct cti_config config;
0180     struct list_head node;
0181     void (*csdev_release)(struct device *dev);
0182 };
0183
0184 /*
0185  * Channel operation types.
0186  */
0187 enum cti_chan_op {
0188     CTI_CHAN_ATTACH,
0189     CTI_CHAN_DETACH,
0190 };
0191
0192 enum cti_trig_dir {
0193     CTI_TRIG_IN,
0194     CTI_TRIG_OUT,
0195 };
0196
0197 enum cti_chan_gate_op {
0198     CTI_GATE_CHAN_ENABLE,
0199     CTI_GATE_CHAN_DISABLE,
0200 };
0201
0202 enum cti_chan_set_op {
0203     CTI_CHAN_SET,
0204     CTI_CHAN_CLR,
0205     CTI_CHAN_PULSE,
0206 };
0207
0208 /* private cti driver fns & vars */
0209 extern const struct attribute_group *coresight_cti_groups[];
0210 int cti_add_default_connection(struct device *dev,
0211                    struct cti_drvdata *drvdata);
0212 int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,
0213                  struct cti_trig_con *tc,
0214                  struct coresight_device *csdev,
0215                  const char *assoc_dev_name);
0216 struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
0217                        int out_sigs);
0218 int cti_enable(struct coresight_device *csdev);
0219 int cti_disable(struct coresight_device *csdev);
0220 void cti_write_all_hw_regs(struct cti_drvdata *drvdata);
0221 void cti_write_intack(struct device *dev, u32 ackval);
0222 void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value);
0223 int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
0224             enum cti_trig_dir direction, u32 channel_idx,
0225             u32 trigger_idx);
0226 int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op,
0227             u32 channel_idx);
0228 int cti_channel_setop(struct device *dev, enum cti_chan_set_op op,
0229               u32 channel_idx);
0230 int cti_create_cons_sysfs(struct device *dev, struct cti_drvdata *drvdata);
0231 struct coresight_platform_data *
0232 coresight_cti_get_platform_data(struct device *dev);
0233 const char *cti_plat_get_node_name(struct fwnode_handle *fwnode);
0234
0235 /* cti powered and enabled */
0236 static inline bool cti_active(struct cti_config *cfg)
0237 {
0238     return cfg->hw_powered && cfg->hw_enabled;
0239 }
0240
0241 #endif  /* _CORESIGHT_CORESIGHT_CTI_H */