hwtracing/coresight/coresight-catu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 Arm Limited. All rights reserved.
0004  *
0005  * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
0006  */
0007
0008 #ifndef _CORESIGHT_CATU_H
0009 #define _CORESIGHT_CATU_H
0010
0011 #include "coresight-priv.h"
0012
0013 /* Register offset from base */
0014 #define CATU_CONTROL        0x000
0015 #define CATU_MODE       0x004
0016 #define CATU_AXICTRL        0x008
0017 #define CATU_IRQEN      0x00c
0018 #define CATU_SLADDRLO       0x020
0019 #define CATU_SLADDRHI       0x024
0020 #define CATU_INADDRLO       0x028
0021 #define CATU_INADDRHI       0x02c
0022 #define CATU_STATUS     0x100
0023 #define CATU_DEVARCH        0xfbc
0024
0025 #define CATU_CONTROL_ENABLE 0
0026
0027 #define CATU_MODE_PASS_THROUGH  0U
0028 #define CATU_MODE_TRANSLATE 1U
0029
0030 #define CATU_AXICTRL_ARCACHE_SHIFT  4
0031 #define CATU_AXICTRL_ARCACHE_MASK   0xf
0032 #define CATU_AXICTRL_ARPROT_MASK    0x3
0033 #define CATU_AXICTRL_ARCACHE(arcache)       \
0034     (((arcache) & CATU_AXICTRL_ARCACHE_MASK) << CATU_AXICTRL_ARCACHE_SHIFT)
0035
0036 #define CATU_AXICTRL_VAL(arcache, arprot)   \
0037     (CATU_AXICTRL_ARCACHE(arcache) | ((arprot) & CATU_AXICTRL_ARPROT_MASK))
0038
0039 #define AXI3_AxCACHE_WB_READ_ALLOC  0x7
0040 /*
0041  * AXI - ARPROT bits:
0042  * See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
0043  * sectionA4.7 Access Permissions.
0044  *
0045  * Bit 0: 0 - Unprivileged access, 1 - Privileged access
0046  * Bit 1: 0 - Secure access, 1 - Non-secure access.
0047  * Bit 2: 0 - Data access, 1 - instruction access.
0048  *
0049  * CATU AXICTRL:ARPROT[2] is res0 as we always access data.
0050  */
0051 #define CATU_OS_ARPROT          0x2
0052
0053 #define CATU_OS_AXICTRL     \
0054     CATU_AXICTRL_VAL(AXI3_AxCACHE_WB_READ_ALLOC, CATU_OS_ARPROT)
0055
0056 #define CATU_STATUS_READY   8
0057 #define CATU_STATUS_ADRERR  0
0058 #define CATU_STATUS_AXIERR  4
0059
0060 #define CATU_IRQEN_ON       0x1
0061 #define CATU_IRQEN_OFF      0x0
0062
0063 struct catu_drvdata {
0064     void __iomem *base;
0065     struct coresight_device *csdev;
0066     int irq;
0067 };
0068
0069 #define CATU_REG32(name, offset)                    \
0070 static inline u32                           \
0071 catu_read_##name(struct catu_drvdata *drvdata)              \
0072 {                                   \
0073     return coresight_read_reg_pair(drvdata->base, offset, -1);  \
0074 }                                   \
0075 static inline void                          \
0076 catu_write_##name(struct catu_drvdata *drvdata, u32 val)        \
0077 {                                   \
0078     coresight_write_reg_pair(drvdata->base, val, offset, -1);   \
0079 }
0080
0081 #define CATU_REG_PAIR(name, lo_off, hi_off)             \
0082 static inline u64                           \
0083 catu_read_##name(struct catu_drvdata *drvdata)              \
0084 {                                   \
0085     return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);  \
0086 }                                   \
0087 static inline void                          \
0088 catu_write_##name(struct catu_drvdata *drvdata, u64 val)        \
0089 {                                   \
0090     coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);   \
0091 }
0092
0093 CATU_REG32(control, CATU_CONTROL);
0094 CATU_REG32(mode, CATU_MODE);
0095 CATU_REG32(irqen, CATU_IRQEN);
0096 CATU_REG32(axictrl, CATU_AXICTRL);
0097 CATU_REG_PAIR(sladdr, CATU_SLADDRLO, CATU_SLADDRHI)
0098 CATU_REG_PAIR(inaddr, CATU_INADDRLO, CATU_INADDRHI)
0099
0100 static inline bool coresight_is_catu_device(struct coresight_device *csdev)
0101 {
0102     if (!IS_ENABLED(CONFIG_CORESIGHT_CATU))
0103         return false;
0104     if (csdev->type != CORESIGHT_DEV_TYPE_HELPER)
0105         return false;
0106     if (csdev->subtype.helper_subtype != CORESIGHT_DEV_SUBTYPE_HELPER_CATU)
0107         return false;
0108     return true;
0109 }
0110
0111 #endif