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0007 #include <linux/hwspinlock.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #include "hwspinlock_internal.h"
0018
0019 #define QCOM_MUTEX_APPS_PROC_ID 1
0020 #define QCOM_MUTEX_NUM_LOCKS 32
0021
0022 struct qcom_hwspinlock_of_data {
0023 u32 offset;
0024 u32 stride;
0025 };
0026
0027 static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
0028 {
0029 struct regmap_field *field = lock->priv;
0030 u32 lock_owner;
0031 int ret;
0032
0033 ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID);
0034 if (ret)
0035 return ret;
0036
0037 ret = regmap_field_read(field, &lock_owner);
0038 if (ret)
0039 return ret;
0040
0041 return lock_owner == QCOM_MUTEX_APPS_PROC_ID;
0042 }
0043
0044 static void qcom_hwspinlock_unlock(struct hwspinlock *lock)
0045 {
0046 struct regmap_field *field = lock->priv;
0047 u32 lock_owner;
0048 int ret;
0049
0050 ret = regmap_field_read(field, &lock_owner);
0051 if (ret) {
0052 pr_err("%s: unable to query spinlock owner\n", __func__);
0053 return;
0054 }
0055
0056 if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) {
0057 pr_err("%s: spinlock not owned by us (actual owner is %d)\n",
0058 __func__, lock_owner);
0059 }
0060
0061 ret = regmap_field_write(field, 0);
0062 if (ret)
0063 pr_err("%s: failed to unlock spinlock\n", __func__);
0064 }
0065
0066 static const struct hwspinlock_ops qcom_hwspinlock_ops = {
0067 .trylock = qcom_hwspinlock_trylock,
0068 .unlock = qcom_hwspinlock_unlock,
0069 };
0070
0071 static const struct qcom_hwspinlock_of_data of_sfpb_mutex = {
0072 .offset = 0x4,
0073 .stride = 0x4,
0074 };
0075
0076
0077 static const struct qcom_hwspinlock_of_data of_tcsr_mutex = {
0078 .offset = 0,
0079 .stride = 0x1000,
0080 };
0081
0082 static const struct of_device_id qcom_hwspinlock_of_match[] = {
0083 { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
0084 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
0085 { }
0086 };
0087 MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
0088
0089 static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
0090 u32 *base, u32 *stride)
0091 {
0092 struct device_node *syscon;
0093 struct regmap *regmap;
0094 int ret;
0095
0096 syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
0097 if (!syscon)
0098 return ERR_PTR(-ENODEV);
0099
0100 regmap = syscon_node_to_regmap(syscon);
0101 of_node_put(syscon);
0102 if (IS_ERR(regmap))
0103 return regmap;
0104
0105 ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
0106 if (ret < 0) {
0107 dev_err(&pdev->dev, "no offset in syscon\n");
0108 return ERR_PTR(-EINVAL);
0109 }
0110
0111 ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
0112 if (ret < 0) {
0113 dev_err(&pdev->dev, "no stride syscon\n");
0114 return ERR_PTR(-EINVAL);
0115 }
0116
0117 return regmap;
0118 }
0119
0120 static const struct regmap_config tcsr_mutex_config = {
0121 .reg_bits = 32,
0122 .reg_stride = 4,
0123 .val_bits = 32,
0124 .max_register = 0x40000,
0125 .fast_io = true,
0126 };
0127
0128 static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
0129 u32 *offset, u32 *stride)
0130 {
0131 const struct qcom_hwspinlock_of_data *data;
0132 struct device *dev = &pdev->dev;
0133 void __iomem *base;
0134
0135 data = of_device_get_match_data(dev);
0136
0137 *offset = data->offset;
0138 *stride = data->stride;
0139
0140 base = devm_platform_ioremap_resource(pdev, 0);
0141 if (IS_ERR(base))
0142 return ERR_CAST(base);
0143
0144 return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
0145 }
0146
0147 static int qcom_hwspinlock_probe(struct platform_device *pdev)
0148 {
0149 struct hwspinlock_device *bank;
0150 struct reg_field field;
0151 struct regmap *regmap;
0152 size_t array_size;
0153 u32 stride;
0154 u32 base;
0155 int i;
0156
0157 regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride);
0158 if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV)
0159 regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride);
0160
0161 if (IS_ERR(regmap))
0162 return PTR_ERR(regmap);
0163
0164 array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
0165 bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);
0166 if (!bank)
0167 return -ENOMEM;
0168
0169 platform_set_drvdata(pdev, bank);
0170
0171 for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) {
0172 field.reg = base + i * stride;
0173 field.lsb = 0;
0174 field.msb = 31;
0175
0176 bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,
0177 regmap, field);
0178 }
0179
0180 return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,
0181 0, QCOM_MUTEX_NUM_LOCKS);
0182 }
0183
0184 static struct platform_driver qcom_hwspinlock_driver = {
0185 .probe = qcom_hwspinlock_probe,
0186 .driver = {
0187 .name = "qcom_hwspinlock",
0188 .of_match_table = qcom_hwspinlock_of_match,
0189 },
0190 };
0191
0192 static int __init qcom_hwspinlock_init(void)
0193 {
0194 return platform_driver_register(&qcom_hwspinlock_driver);
0195 }
0196
0197 postcore_initcall(qcom_hwspinlock_init);
0198
0199 static void __exit qcom_hwspinlock_exit(void)
0200 {
0201 platform_driver_unregister(&qcom_hwspinlock_driver);
0202 }
0203 module_exit(qcom_hwspinlock_exit);
0204
0205 MODULE_LICENSE("GPL v2");
0206 MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs");