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0022 #include <linux/err.h>
0023 #include <linux/hwmon.h>
0024 #include <linux/i2c.h>
0025 #include <linux/init.h>
0026 #include <linux/kernel.h>
0027 #include <linux/module.h>
0028 #include <linux/regmap.h>
0029 #include <linux/slab.h>
0030 #include <linux/util_macros.h>
0031
0032
0033 #define TMP51X_SHUNT_CONFIG 0x00
0034 #define TMP51X_TEMP_CONFIG 0x01
0035 #define TMP51X_STATUS 0x02
0036 #define TMP51X_SMBUS_ALERT 0x03
0037 #define TMP51X_SHUNT_CURRENT_RESULT 0x04
0038 #define TMP51X_BUS_VOLTAGE_RESULT 0x05
0039 #define TMP51X_POWER_RESULT 0x06
0040 #define TMP51X_BUS_CURRENT_RESULT 0x07
0041 #define TMP51X_LOCAL_TEMP_RESULT 0x08
0042 #define TMP51X_REMOTE_TEMP_RESULT_1 0x09
0043 #define TMP51X_REMOTE_TEMP_RESULT_2 0x0A
0044 #define TMP51X_SHUNT_CURRENT_H_LIMIT 0x0C
0045 #define TMP51X_SHUNT_CURRENT_L_LIMIT 0x0D
0046 #define TMP51X_BUS_VOLTAGE_H_LIMIT 0x0E
0047 #define TMP51X_BUS_VOLTAGE_L_LIMIT 0x0F
0048 #define TMP51X_POWER_LIMIT 0x10
0049 #define TMP51X_LOCAL_TEMP_LIMIT 0x11
0050 #define TMP51X_REMOTE_TEMP_LIMIT_1 0x12
0051 #define TMP51X_REMOTE_TEMP_LIMIT_2 0x13
0052 #define TMP51X_SHUNT_CALIBRATION 0x15
0053 #define TMP51X_N_FACTOR_AND_HYST_1 0x16
0054 #define TMP51X_N_FACTOR_2 0x17
0055 #define TMP51X_MAN_ID_REG 0xFE
0056 #define TMP51X_DEVICE_ID_REG 0xFF
0057
0058
0059 #define TMP513_REMOTE_TEMP_RESULT_3 0x0B
0060 #define TMP513_REMOTE_TEMP_LIMIT_3 0x14
0061 #define TMP513_N_FACTOR_3 0x18
0062
0063
0064 #define TMP51X_MANUFACTURER_ID 0x55FF
0065
0066 #define TMP512_DEVICE_ID 0x22FF
0067 #define TMP513_DEVICE_ID 0x23FF
0068
0069
0070 #define TMP51X_SHUNT_CONFIG_DEFAULT 0x399F
0071 #define TMP51X_SHUNT_VALUE_DEFAULT 1000
0072 #define TMP51X_VBUS_RANGE_DEFAULT TMP51X_VBUS_RANGE_32V
0073 #define TMP51X_PGA_DEFAULT 8
0074 #define TMP51X_MAX_REGISTER_ADDR 0xFF
0075
0076 #define TMP512_TEMP_CONFIG_DEFAULT 0xBF80
0077 #define TMP513_TEMP_CONFIG_DEFAULT 0xFF80
0078
0079
0080 #define CURRENT_SENSE_VOLTAGE_320_MASK 0x1800
0081 #define CURRENT_SENSE_VOLTAGE_160_MASK 0x1000
0082 #define CURRENT_SENSE_VOLTAGE_80_MASK 0x0800
0083 #define CURRENT_SENSE_VOLTAGE_40_MASK 0
0084
0085 #define TMP51X_BUS_VOLTAGE_MASK 0x2000
0086 #define TMP51X_NFACTOR_MASK 0xFF00
0087 #define TMP51X_HYST_MASK 0x00FF
0088
0089 #define TMP51X_BUS_VOLTAGE_SHIFT 3
0090 #define TMP51X_TEMP_SHIFT 3
0091
0092
0093 #define TMP51X_SHUNT_CURRENT_H_LIMIT_POS 15
0094 #define TMP51X_SHUNT_CURRENT_L_LIMIT_POS 14
0095 #define TMP51X_BUS_VOLTAGE_H_LIMIT_POS 13
0096 #define TMP51X_BUS_VOLTAGE_L_LIMIT_POS 12
0097 #define TMP51X_POWER_LIMIT_POS 11
0098 #define TMP51X_LOCAL_TEMP_LIMIT_POS 10
0099 #define TMP51X_REMOTE_TEMP_LIMIT_1_POS 9
0100 #define TMP51X_REMOTE_TEMP_LIMIT_2_POS 8
0101 #define TMP513_REMOTE_TEMP_LIMIT_3_POS 7
0102
0103 #define TMP51X_VBUS_RANGE_32V 32000000
0104 #define TMP51X_VBUS_RANGE_16V 16000000
0105
0106
0107 #define MAX_BUS_VOLTAGE_32_LIMIT 32764
0108 #define MAX_BUS_VOLTAGE_16_LIMIT 16382
0109
0110
0111 #define MAX_TEMP_LIMIT 125000
0112 #define MIN_TEMP_LIMIT -40000
0113
0114 #define MAX_TEMP_HYST 127500
0115
0116 static const u8 TMP51X_TEMP_INPUT[4] = {
0117 TMP51X_LOCAL_TEMP_RESULT,
0118 TMP51X_REMOTE_TEMP_RESULT_1,
0119 TMP51X_REMOTE_TEMP_RESULT_2,
0120 TMP513_REMOTE_TEMP_RESULT_3
0121 };
0122
0123 static const u8 TMP51X_TEMP_CRIT[4] = {
0124 TMP51X_LOCAL_TEMP_LIMIT,
0125 TMP51X_REMOTE_TEMP_LIMIT_1,
0126 TMP51X_REMOTE_TEMP_LIMIT_2,
0127 TMP513_REMOTE_TEMP_LIMIT_3
0128 };
0129
0130 static const u8 TMP51X_TEMP_CRIT_ALARM[4] = {
0131 TMP51X_LOCAL_TEMP_LIMIT_POS,
0132 TMP51X_REMOTE_TEMP_LIMIT_1_POS,
0133 TMP51X_REMOTE_TEMP_LIMIT_2_POS,
0134 TMP513_REMOTE_TEMP_LIMIT_3_POS
0135 };
0136
0137 static const u8 TMP51X_TEMP_CRIT_HYST[4] = {
0138 TMP51X_N_FACTOR_AND_HYST_1,
0139 TMP51X_N_FACTOR_AND_HYST_1,
0140 TMP51X_N_FACTOR_AND_HYST_1,
0141 TMP51X_N_FACTOR_AND_HYST_1
0142 };
0143
0144 static const u8 TMP51X_CURR_INPUT[2] = {
0145 TMP51X_SHUNT_CURRENT_RESULT,
0146 TMP51X_BUS_CURRENT_RESULT
0147 };
0148
0149 static struct regmap_config tmp51x_regmap_config = {
0150 .reg_bits = 8,
0151 .val_bits = 16,
0152 .max_register = TMP51X_MAX_REGISTER_ADDR,
0153 };
0154
0155 enum tmp51x_ids {
0156 tmp512, tmp513
0157 };
0158
0159 struct tmp51x_data {
0160 u16 shunt_config;
0161 u16 pga_gain;
0162 u32 vbus_range_uvolt;
0163
0164 u16 temp_config;
0165 u32 nfactor[3];
0166
0167 u32 shunt_uohms;
0168
0169 u32 curr_lsb_ua;
0170 u32 pwr_lsb_uw;
0171
0172 enum tmp51x_ids id;
0173 struct regmap *regmap;
0174 };
0175
0176
0177 static inline u8 tmp51x_get_pga_shift(struct tmp51x_data *data)
0178 {
0179 return 5 - ffs(data->pga_gain);
0180 }
0181
0182 static int tmp51x_get_value(struct tmp51x_data *data, u8 reg, u8 pos,
0183 unsigned int regval, long *val)
0184 {
0185 switch (reg) {
0186 case TMP51X_STATUS:
0187 *val = (regval >> pos) & 1;
0188 break;
0189 case TMP51X_SHUNT_CURRENT_RESULT:
0190 case TMP51X_SHUNT_CURRENT_H_LIMIT:
0191 case TMP51X_SHUNT_CURRENT_L_LIMIT:
0192
0193
0194
0195
0196
0197
0198 *val = sign_extend32(regval, 17 - tmp51x_get_pga_shift(data));
0199 *val = DIV_ROUND_CLOSEST(*val * 10000, data->shunt_uohms);
0200 break;
0201 case TMP51X_BUS_VOLTAGE_RESULT:
0202 case TMP51X_BUS_VOLTAGE_H_LIMIT:
0203 case TMP51X_BUS_VOLTAGE_L_LIMIT:
0204
0205 *val = (regval >> TMP51X_BUS_VOLTAGE_SHIFT) * 4;
0206 break;
0207 case TMP51X_POWER_RESULT:
0208 case TMP51X_POWER_LIMIT:
0209
0210 *val = regval * data->pwr_lsb_uw;
0211 break;
0212 case TMP51X_BUS_CURRENT_RESULT:
0213
0214 *val = sign_extend32(regval, 16) * data->curr_lsb_ua;
0215 *val = DIV_ROUND_CLOSEST(*val, 1000);
0216 break;
0217 case TMP51X_LOCAL_TEMP_RESULT:
0218 case TMP51X_REMOTE_TEMP_RESULT_1:
0219 case TMP51X_REMOTE_TEMP_RESULT_2:
0220 case TMP513_REMOTE_TEMP_RESULT_3:
0221 case TMP51X_LOCAL_TEMP_LIMIT:
0222 case TMP51X_REMOTE_TEMP_LIMIT_1:
0223 case TMP51X_REMOTE_TEMP_LIMIT_2:
0224 case TMP513_REMOTE_TEMP_LIMIT_3:
0225
0226 *val = sign_extend32(regval, 16) >> TMP51X_TEMP_SHIFT;
0227 *val = DIV_ROUND_CLOSEST(*val * 625, 10);
0228 break;
0229 case TMP51X_N_FACTOR_AND_HYST_1:
0230
0231 *val = (regval & TMP51X_HYST_MASK) * 500;
0232 break;
0233 default:
0234
0235 WARN_ON_ONCE(1);
0236 *val = 0;
0237 return -EOPNOTSUPP;
0238 }
0239
0240 return 0;
0241 }
0242
0243 static int tmp51x_set_value(struct tmp51x_data *data, u8 reg, long val)
0244 {
0245 int regval, max_val;
0246 u32 mask = 0;
0247
0248 switch (reg) {
0249 case TMP51X_SHUNT_CURRENT_H_LIMIT:
0250 case TMP51X_SHUNT_CURRENT_L_LIMIT:
0251
0252
0253
0254
0255 val = DIV_ROUND_CLOSEST(val * data->shunt_uohms, 10000);
0256 max_val = U16_MAX >> tmp51x_get_pga_shift(data);
0257 regval = clamp_val(val, -max_val, max_val);
0258 break;
0259 case TMP51X_BUS_VOLTAGE_H_LIMIT:
0260 case TMP51X_BUS_VOLTAGE_L_LIMIT:
0261
0262 max_val = (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) ?
0263 MAX_BUS_VOLTAGE_32_LIMIT : MAX_BUS_VOLTAGE_16_LIMIT;
0264
0265 val = clamp_val(DIV_ROUND_CLOSEST(val, 4), 0, max_val);
0266 regval = val << TMP51X_BUS_VOLTAGE_SHIFT;
0267 break;
0268 case TMP51X_POWER_LIMIT:
0269 regval = clamp_val(DIV_ROUND_CLOSEST(val, data->pwr_lsb_uw), 0,
0270 U16_MAX);
0271 break;
0272 case TMP51X_LOCAL_TEMP_LIMIT:
0273 case TMP51X_REMOTE_TEMP_LIMIT_1:
0274 case TMP51X_REMOTE_TEMP_LIMIT_2:
0275 case TMP513_REMOTE_TEMP_LIMIT_3:
0276
0277 val = clamp_val(val, MIN_TEMP_LIMIT, MAX_TEMP_LIMIT);
0278 regval = DIV_ROUND_CLOSEST(val * 10, 625) << TMP51X_TEMP_SHIFT;
0279 break;
0280 case TMP51X_N_FACTOR_AND_HYST_1:
0281
0282 val = clamp_val(val, 0, MAX_TEMP_HYST);
0283 regval = DIV_ROUND_CLOSEST(val, 500);
0284 mask = TMP51X_HYST_MASK;
0285 break;
0286 default:
0287
0288 WARN_ON_ONCE(1);
0289 return -EOPNOTSUPP;
0290 }
0291
0292 if (mask == 0)
0293 return regmap_write(data->regmap, reg, regval);
0294 else
0295 return regmap_update_bits(data->regmap, reg, mask, regval);
0296 }
0297
0298 static u8 tmp51x_get_reg(enum hwmon_sensor_types type, u32 attr, int channel)
0299 {
0300 switch (type) {
0301 case hwmon_temp:
0302 switch (attr) {
0303 case hwmon_temp_input:
0304 return TMP51X_TEMP_INPUT[channel];
0305 case hwmon_temp_crit_alarm:
0306 return TMP51X_STATUS;
0307 case hwmon_temp_crit:
0308 return TMP51X_TEMP_CRIT[channel];
0309 case hwmon_temp_crit_hyst:
0310 return TMP51X_TEMP_CRIT_HYST[channel];
0311 }
0312 break;
0313 case hwmon_in:
0314 switch (attr) {
0315 case hwmon_in_input:
0316 return TMP51X_BUS_VOLTAGE_RESULT;
0317 case hwmon_in_lcrit_alarm:
0318 case hwmon_in_crit_alarm:
0319 return TMP51X_STATUS;
0320 case hwmon_in_lcrit:
0321 return TMP51X_BUS_VOLTAGE_L_LIMIT;
0322 case hwmon_in_crit:
0323 return TMP51X_BUS_VOLTAGE_H_LIMIT;
0324 }
0325 break;
0326 case hwmon_curr:
0327 switch (attr) {
0328 case hwmon_curr_input:
0329 return TMP51X_CURR_INPUT[channel];
0330 case hwmon_curr_lcrit_alarm:
0331 case hwmon_curr_crit_alarm:
0332 return TMP51X_STATUS;
0333 case hwmon_curr_lcrit:
0334 return TMP51X_SHUNT_CURRENT_L_LIMIT;
0335 case hwmon_curr_crit:
0336 return TMP51X_SHUNT_CURRENT_H_LIMIT;
0337 }
0338 break;
0339 case hwmon_power:
0340 switch (attr) {
0341 case hwmon_power_input:
0342 return TMP51X_POWER_RESULT;
0343 case hwmon_power_crit_alarm:
0344 return TMP51X_STATUS;
0345 case hwmon_power_crit:
0346 return TMP51X_POWER_LIMIT;
0347 }
0348 break;
0349 default:
0350 break;
0351 }
0352
0353 return 0;
0354 }
0355
0356 static u8 tmp51x_get_status_pos(enum hwmon_sensor_types type, u32 attr,
0357 int channel)
0358 {
0359 switch (type) {
0360 case hwmon_temp:
0361 switch (attr) {
0362 case hwmon_temp_crit_alarm:
0363 return TMP51X_TEMP_CRIT_ALARM[channel];
0364 }
0365 break;
0366 case hwmon_in:
0367 switch (attr) {
0368 case hwmon_in_lcrit_alarm:
0369 return TMP51X_BUS_VOLTAGE_L_LIMIT_POS;
0370 case hwmon_in_crit_alarm:
0371 return TMP51X_BUS_VOLTAGE_H_LIMIT_POS;
0372 }
0373 break;
0374 case hwmon_curr:
0375 switch (attr) {
0376 case hwmon_curr_lcrit_alarm:
0377 return TMP51X_SHUNT_CURRENT_L_LIMIT_POS;
0378 case hwmon_curr_crit_alarm:
0379 return TMP51X_SHUNT_CURRENT_H_LIMIT_POS;
0380 }
0381 break;
0382 case hwmon_power:
0383 switch (attr) {
0384 case hwmon_power_crit_alarm:
0385 return TMP51X_POWER_LIMIT_POS;
0386 }
0387 break;
0388 default:
0389 break;
0390 }
0391
0392 return 0;
0393 }
0394
0395 static int tmp51x_read(struct device *dev, enum hwmon_sensor_types type,
0396 u32 attr, int channel, long *val)
0397 {
0398 struct tmp51x_data *data = dev_get_drvdata(dev);
0399 int ret;
0400 u32 regval;
0401 u8 pos = 0, reg = 0;
0402
0403 reg = tmp51x_get_reg(type, attr, channel);
0404 if (reg == 0)
0405 return -EOPNOTSUPP;
0406
0407 if (reg == TMP51X_STATUS)
0408 pos = tmp51x_get_status_pos(type, attr, channel);
0409
0410 ret = regmap_read(data->regmap, reg, ®val);
0411 if (ret < 0)
0412 return ret;
0413
0414 return tmp51x_get_value(data, reg, pos, regval, val);
0415 }
0416
0417 static int tmp51x_write(struct device *dev, enum hwmon_sensor_types type,
0418 u32 attr, int channel, long val)
0419 {
0420 u8 reg = 0;
0421
0422 reg = tmp51x_get_reg(type, attr, channel);
0423 if (reg == 0)
0424 return -EOPNOTSUPP;
0425
0426 return tmp51x_set_value(dev_get_drvdata(dev), reg, val);
0427 }
0428
0429 static umode_t tmp51x_is_visible(const void *_data,
0430 enum hwmon_sensor_types type, u32 attr,
0431 int channel)
0432 {
0433 const struct tmp51x_data *data = _data;
0434
0435 switch (type) {
0436 case hwmon_temp:
0437 if (data->id == tmp512 && channel == 4)
0438 return 0;
0439 switch (attr) {
0440 case hwmon_temp_input:
0441 case hwmon_temp_crit_alarm:
0442 return 0444;
0443 case hwmon_temp_crit:
0444 return 0644;
0445 case hwmon_temp_crit_hyst:
0446 if (channel == 0)
0447 return 0644;
0448 return 0444;
0449 }
0450 break;
0451 case hwmon_in:
0452 switch (attr) {
0453 case hwmon_in_input:
0454 case hwmon_in_lcrit_alarm:
0455 case hwmon_in_crit_alarm:
0456 return 0444;
0457 case hwmon_in_lcrit:
0458 case hwmon_in_crit:
0459 return 0644;
0460 }
0461 break;
0462 case hwmon_curr:
0463 if (!data->shunt_uohms)
0464 return 0;
0465
0466 switch (attr) {
0467 case hwmon_curr_input:
0468 case hwmon_curr_lcrit_alarm:
0469 case hwmon_curr_crit_alarm:
0470 return 0444;
0471 case hwmon_curr_lcrit:
0472 case hwmon_curr_crit:
0473 return 0644;
0474 }
0475 break;
0476 case hwmon_power:
0477 if (!data->shunt_uohms)
0478 return 0;
0479
0480 switch (attr) {
0481 case hwmon_power_input:
0482 case hwmon_power_crit_alarm:
0483 return 0444;
0484 case hwmon_power_crit:
0485 return 0644;
0486 }
0487 break;
0488 default:
0489 break;
0490 }
0491 return 0;
0492 }
0493
0494 static const struct hwmon_channel_info *tmp51x_info[] = {
0495 HWMON_CHANNEL_INFO(temp,
0496 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
0497 HWMON_T_CRIT_HYST,
0498 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
0499 HWMON_T_CRIT_HYST,
0500 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
0501 HWMON_T_CRIT_HYST,
0502 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
0503 HWMON_T_CRIT_HYST),
0504 HWMON_CHANNEL_INFO(in,
0505 HWMON_I_INPUT | HWMON_I_LCRIT | HWMON_I_LCRIT_ALARM |
0506 HWMON_I_CRIT | HWMON_I_CRIT_ALARM),
0507 HWMON_CHANNEL_INFO(curr,
0508 HWMON_C_INPUT | HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM |
0509 HWMON_C_CRIT | HWMON_C_CRIT_ALARM,
0510 HWMON_C_INPUT),
0511 HWMON_CHANNEL_INFO(power,
0512 HWMON_P_INPUT | HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
0513 NULL
0514 };
0515
0516 static const struct hwmon_ops tmp51x_hwmon_ops = {
0517 .is_visible = tmp51x_is_visible,
0518 .read = tmp51x_read,
0519 .write = tmp51x_write,
0520 };
0521
0522 static const struct hwmon_chip_info tmp51x_chip_info = {
0523 .ops = &tmp51x_hwmon_ops,
0524 .info = tmp51x_info,
0525 };
0526
0527
0528
0529
0530 static int tmp51x_calibrate(struct tmp51x_data *data)
0531 {
0532 int vshunt_max = data->pga_gain * 40;
0533 u64 max_curr_ma;
0534 u32 div;
0535
0536
0537
0538
0539
0540
0541
0542 if (data->shunt_uohms == 0)
0543 return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION, 0);
0544
0545 max_curr_ma = DIV_ROUND_CLOSEST_ULL(vshunt_max * 1000 * 1000,
0546 data->shunt_uohms);
0547
0548
0549
0550
0551
0552 data->curr_lsb_ua = DIV_ROUND_CLOSEST_ULL(max_curr_ma * 1000, 32767);
0553 data->pwr_lsb_uw = 20 * data->curr_lsb_ua;
0554
0555 div = DIV_ROUND_CLOSEST_ULL(data->curr_lsb_ua * data->shunt_uohms,
0556 1000 * 1000);
0557
0558 return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION,
0559 DIV_ROUND_CLOSEST(40960, div));
0560 }
0561
0562
0563
0564
0565 static int tmp51x_init(struct tmp51x_data *data)
0566 {
0567 unsigned int regval;
0568 int ret = regmap_write(data->regmap, TMP51X_SHUNT_CONFIG,
0569 data->shunt_config);
0570 if (ret < 0)
0571 return ret;
0572
0573 ret = regmap_write(data->regmap, TMP51X_TEMP_CONFIG, data->temp_config);
0574 if (ret < 0)
0575 return ret;
0576
0577
0578 ret = regmap_update_bits(data->regmap, TMP51X_N_FACTOR_AND_HYST_1,
0579 TMP51X_NFACTOR_MASK, data->nfactor[0] << 8);
0580 if (ret < 0)
0581 return ret;
0582
0583 ret = regmap_write(data->regmap, TMP51X_N_FACTOR_2,
0584 data->nfactor[1] << 8);
0585 if (ret < 0)
0586 return ret;
0587
0588 if (data->id == tmp513) {
0589 ret = regmap_write(data->regmap, TMP513_N_FACTOR_3,
0590 data->nfactor[2] << 8);
0591 if (ret < 0)
0592 return ret;
0593 }
0594
0595 ret = tmp51x_calibrate(data);
0596 if (ret < 0)
0597 return ret;
0598
0599
0600 return regmap_read(data->regmap, TMP51X_STATUS, ®val);
0601 }
0602
0603 static const struct i2c_device_id tmp51x_id[] = {
0604 { "tmp512", tmp512 },
0605 { "tmp513", tmp513 },
0606 { }
0607 };
0608 MODULE_DEVICE_TABLE(i2c, tmp51x_id);
0609
0610 static const struct of_device_id tmp51x_of_match[] = {
0611 {
0612 .compatible = "ti,tmp512",
0613 .data = (void *)tmp512
0614 },
0615 {
0616 .compatible = "ti,tmp513",
0617 .data = (void *)tmp513
0618 },
0619 { },
0620 };
0621 MODULE_DEVICE_TABLE(of, tmp51x_of_match);
0622
0623 static int tmp51x_vbus_range_to_reg(struct device *dev,
0624 struct tmp51x_data *data)
0625 {
0626 if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) {
0627 data->shunt_config |= TMP51X_BUS_VOLTAGE_MASK;
0628 } else if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_16V) {
0629 data->shunt_config &= ~TMP51X_BUS_VOLTAGE_MASK;
0630 } else {
0631 dev_err(dev, "ti,bus-range-microvolt is invalid: %u\n",
0632 data->vbus_range_uvolt);
0633 return -EINVAL;
0634 }
0635 return 0;
0636 }
0637
0638 static int tmp51x_pga_gain_to_reg(struct device *dev, struct tmp51x_data *data)
0639 {
0640 if (data->pga_gain == 8) {
0641 data->shunt_config |= CURRENT_SENSE_VOLTAGE_320_MASK;
0642 } else if (data->pga_gain == 4) {
0643 data->shunt_config |= CURRENT_SENSE_VOLTAGE_160_MASK;
0644 } else if (data->pga_gain == 2) {
0645 data->shunt_config |= CURRENT_SENSE_VOLTAGE_80_MASK;
0646 } else if (data->pga_gain == 1) {
0647 data->shunt_config |= CURRENT_SENSE_VOLTAGE_40_MASK;
0648 } else {
0649 dev_err(dev, "ti,pga-gain is invalid: %u\n", data->pga_gain);
0650 return -EINVAL;
0651 }
0652 return 0;
0653 }
0654
0655 static int tmp51x_read_properties(struct device *dev, struct tmp51x_data *data)
0656 {
0657 int ret;
0658 u32 nfactor[3];
0659 u32 val;
0660
0661 ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms", &val);
0662 data->shunt_uohms = (ret >= 0) ? val : TMP51X_SHUNT_VALUE_DEFAULT;
0663
0664 ret = device_property_read_u32(dev, "ti,bus-range-microvolt", &val);
0665 data->vbus_range_uvolt = (ret >= 0) ? val : TMP51X_VBUS_RANGE_DEFAULT;
0666 ret = tmp51x_vbus_range_to_reg(dev, data);
0667 if (ret < 0)
0668 return ret;
0669
0670 ret = device_property_read_u32(dev, "ti,pga-gain", &val);
0671 data->pga_gain = (ret >= 0) ? val : TMP51X_PGA_DEFAULT;
0672 ret = tmp51x_pga_gain_to_reg(dev, data);
0673 if (ret < 0)
0674 return ret;
0675
0676 ret = device_property_read_u32_array(dev, "ti,nfactor", nfactor,
0677 (data->id == tmp513) ? 3 : 2);
0678 if (ret >= 0)
0679 memcpy(data->nfactor, nfactor, (data->id == tmp513) ? 3 : 2);
0680
0681
0682 if (data->shunt_uohms > data->pga_gain * 40 * 1000 * 1000) {
0683 dev_err(dev, "shunt-resistor: %u too big for pga_gain: %u\n",
0684 data->shunt_uohms, data->pga_gain);
0685 return -EINVAL;
0686 }
0687
0688 return 0;
0689 }
0690
0691 static void tmp51x_use_default(struct tmp51x_data *data)
0692 {
0693 data->vbus_range_uvolt = TMP51X_VBUS_RANGE_DEFAULT;
0694 data->pga_gain = TMP51X_PGA_DEFAULT;
0695 data->shunt_uohms = TMP51X_SHUNT_VALUE_DEFAULT;
0696 }
0697
0698 static int tmp51x_configure(struct device *dev, struct tmp51x_data *data)
0699 {
0700 data->shunt_config = TMP51X_SHUNT_CONFIG_DEFAULT;
0701 data->temp_config = (data->id == tmp513) ?
0702 TMP513_TEMP_CONFIG_DEFAULT : TMP512_TEMP_CONFIG_DEFAULT;
0703
0704 if (dev->of_node)
0705 return tmp51x_read_properties(dev, data);
0706
0707 tmp51x_use_default(data);
0708
0709 return 0;
0710 }
0711
0712 static int tmp51x_probe(struct i2c_client *client)
0713 {
0714 struct device *dev = &client->dev;
0715 struct tmp51x_data *data;
0716 struct device *hwmon_dev;
0717 int ret;
0718
0719 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0720 if (!data)
0721 return -ENOMEM;
0722
0723 if (client->dev.of_node)
0724 data->id = (enum tmp51x_ids)device_get_match_data(&client->dev);
0725 else
0726 data->id = i2c_match_id(tmp51x_id, client)->driver_data;
0727
0728 ret = tmp51x_configure(dev, data);
0729 if (ret < 0) {
0730 dev_err(dev, "error configuring the device: %d\n", ret);
0731 return ret;
0732 }
0733
0734 data->regmap = devm_regmap_init_i2c(client, &tmp51x_regmap_config);
0735 if (IS_ERR(data->regmap)) {
0736 dev_err(dev, "failed to allocate register map\n");
0737 return PTR_ERR(data->regmap);
0738 }
0739
0740 ret = tmp51x_init(data);
0741 if (ret < 0) {
0742 dev_err(dev, "error configuring the device: %d\n", ret);
0743 return -ENODEV;
0744 }
0745
0746 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
0747 data,
0748 &tmp51x_chip_info,
0749 NULL);
0750 if (IS_ERR(hwmon_dev))
0751 return PTR_ERR(hwmon_dev);
0752
0753 dev_dbg(dev, "power monitor %s\n", client->name);
0754
0755 return 0;
0756 }
0757
0758 static struct i2c_driver tmp51x_driver = {
0759 .driver = {
0760 .name = "tmp51x",
0761 .of_match_table = of_match_ptr(tmp51x_of_match),
0762 },
0763 .probe_new = tmp51x_probe,
0764 .id_table = tmp51x_id,
0765 };
0766
0767 module_i2c_driver(tmp51x_driver);
0768
0769 MODULE_AUTHOR("Eric Tremblay <etremblay@distechcontrols.com>");
0770 MODULE_DESCRIPTION("tmp51x driver");
0771 MODULE_LICENSE("GPL");