Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for SMM665 Power Controller / Monitor
0004  *
0005  * Copyright (C) 2010 Ericsson AB.
0006  *
0007  * This driver should also work for SMM465, SMM764, and SMM766, but is untested
0008  * for those chips. Only monitoring functionality is implemented.
0009  *
0010  * Datasheets:
0011  * http://www.summitmicro.com/prod_select/summary/SMM665/SMM665B_2089_20.pdf
0012  * http://www.summitmicro.com/prod_select/summary/SMM766B/SMM766B_2122.pdf
0013  */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/init.h>
0018 #include <linux/err.h>
0019 #include <linux/slab.h>
0020 #include <linux/i2c.h>
0021 #include <linux/hwmon.h>
0022 #include <linux/hwmon-sysfs.h>
0023 #include <linux/delay.h>
0024 #include <linux/jiffies.h>
0025 
0026 /* Internal reference voltage (VREF, x 1000 */
0027 #define SMM665_VREF_ADC_X1000   1250
0028 
0029 /* module parameters */
0030 static int vref = SMM665_VREF_ADC_X1000;
0031 module_param(vref, int, 0);
0032 MODULE_PARM_DESC(vref, "Reference voltage in mV");
0033 
0034 enum chips { smm465, smm665, smm665c, smm764, smm766 };
0035 
0036 /*
0037  * ADC channel addresses
0038  */
0039 #define SMM665_MISC16_ADC_DATA_A    0x00
0040 #define SMM665_MISC16_ADC_DATA_B    0x01
0041 #define SMM665_MISC16_ADC_DATA_C    0x02
0042 #define SMM665_MISC16_ADC_DATA_D    0x03
0043 #define SMM665_MISC16_ADC_DATA_E    0x04
0044 #define SMM665_MISC16_ADC_DATA_F    0x05
0045 #define SMM665_MISC16_ADC_DATA_VDD  0x06
0046 #define SMM665_MISC16_ADC_DATA_12V  0x07
0047 #define SMM665_MISC16_ADC_DATA_INT_TEMP 0x08
0048 #define SMM665_MISC16_ADC_DATA_AIN1 0x09
0049 #define SMM665_MISC16_ADC_DATA_AIN2 0x0a
0050 
0051 /*
0052  * Command registers
0053  */
0054 #define SMM665_MISC8_CMD_STS        0x80
0055 #define SMM665_MISC8_STATUS1        0x81
0056 #define SMM665_MISC8_STATUSS2       0x82
0057 #define SMM665_MISC8_IO_POLARITY    0x83
0058 #define SMM665_MISC8_PUP_POLARITY   0x84
0059 #define SMM665_MISC8_ADOC_STATUS1   0x85
0060 #define SMM665_MISC8_ADOC_STATUS2   0x86
0061 #define SMM665_MISC8_WRITE_PROT     0x87
0062 #define SMM665_MISC8_STS_TRACK      0x88
0063 
0064 /*
0065  * Configuration registers and register groups
0066  */
0067 #define SMM665_ADOC_ENABLE      0x0d
0068 #define SMM665_LIMIT_BASE       0x80    /* First limit register */
0069 
0070 /*
0071  * Limit register bit masks
0072  */
0073 #define SMM665_TRIGGER_RST      0x8000
0074 #define SMM665_TRIGGER_HEALTHY      0x4000
0075 #define SMM665_TRIGGER_POWEROFF     0x2000
0076 #define SMM665_TRIGGER_SHUTDOWN     0x1000
0077 #define SMM665_ADC_MASK         0x03ff
0078 
0079 #define smm665_is_critical(lim) ((lim) & (SMM665_TRIGGER_RST \
0080                     | SMM665_TRIGGER_POWEROFF \
0081                     | SMM665_TRIGGER_SHUTDOWN))
0082 /*
0083  * Fault register bit definitions
0084  * Values are merged from status registers 1/2,
0085  * with status register 1 providing the upper 8 bits.
0086  */
0087 #define SMM665_FAULT_A      0x0001
0088 #define SMM665_FAULT_B      0x0002
0089 #define SMM665_FAULT_C      0x0004
0090 #define SMM665_FAULT_D      0x0008
0091 #define SMM665_FAULT_E      0x0010
0092 #define SMM665_FAULT_F      0x0020
0093 #define SMM665_FAULT_VDD    0x0040
0094 #define SMM665_FAULT_12V    0x0080
0095 #define SMM665_FAULT_TEMP   0x0100
0096 #define SMM665_FAULT_AIN1   0x0200
0097 #define SMM665_FAULT_AIN2   0x0400
0098 
0099 /*
0100  * I2C Register addresses
0101  *
0102  * The configuration register needs to be the configured base register.
0103  * The command/status register address is derived from it.
0104  */
0105 #define SMM665_REGMASK      0x78
0106 #define SMM665_CMDREG_BASE  0x48
0107 #define SMM665_CONFREG_BASE 0x50
0108 
0109 /*
0110  *  Equations given by chip manufacturer to calculate voltage/temperature values
0111  *  vref = Reference voltage on VREF_ADC pin (module parameter)
0112  *  adc  = 10bit ADC value read back from registers
0113  */
0114 
0115 /* Voltage A-F and VDD */
0116 #define SMM665_VMON_ADC_TO_VOLTS(adc)  ((adc) * vref / 256)
0117 
0118 /* Voltage 12VIN */
0119 #define SMM665_12VIN_ADC_TO_VOLTS(adc) ((adc) * vref * 3 / 256)
0120 
0121 /* Voltage AIN1, AIN2 */
0122 #define SMM665_AIN_ADC_TO_VOLTS(adc)   ((adc) * vref / 512)
0123 
0124 /* Temp Sensor */
0125 #define SMM665_TEMP_ADC_TO_CELSIUS(adc) (((adc) <= 511) ?          \
0126                      ((int)(adc) * 1000 / 4) :     \
0127                      (((int)(adc) - 0x400) * 1000 / 4))
0128 
0129 #define SMM665_NUM_ADC      11
0130 
0131 /*
0132  * Chip dependent ADC conversion time, in uS
0133  */
0134 #define SMM665_ADC_WAIT_SMM665  70
0135 #define SMM665_ADC_WAIT_SMM766  185
0136 
0137 struct smm665_data {
0138     enum chips type;
0139     int conversion_time;        /* ADC conversion time */
0140     struct i2c_client *client;
0141     struct mutex update_lock;
0142     bool valid;
0143     unsigned long last_updated; /* in jiffies */
0144     u16 adc[SMM665_NUM_ADC];    /* adc values (raw) */
0145     u16 faults;         /* fault status */
0146     /* The following values are in mV */
0147     int critical_min_limit[SMM665_NUM_ADC];
0148     int alarm_min_limit[SMM665_NUM_ADC];
0149     int critical_max_limit[SMM665_NUM_ADC];
0150     int alarm_max_limit[SMM665_NUM_ADC];
0151     struct i2c_client *cmdreg;
0152 };
0153 
0154 /*
0155  * smm665_read16()
0156  *
0157  * Read 16 bit value from <reg>, <reg+1>. Upper 8 bits are in <reg>.
0158  */
0159 static int smm665_read16(struct i2c_client *client, int reg)
0160 {
0161     int rv, val;
0162 
0163     rv = i2c_smbus_read_byte_data(client, reg);
0164     if (rv < 0)
0165         return rv;
0166     val = rv << 8;
0167     rv = i2c_smbus_read_byte_data(client, reg + 1);
0168     if (rv < 0)
0169         return rv;
0170     val |= rv;
0171     return val;
0172 }
0173 
0174 /*
0175  * Read adc value.
0176  */
0177 static int smm665_read_adc(struct smm665_data *data, int adc)
0178 {
0179     struct i2c_client *client = data->cmdreg;
0180     int rv;
0181     int radc;
0182 
0183     /*
0184      * Algorithm for reading ADC, per SMM665 datasheet
0185      *
0186      *  {[S][addr][W][Ack]} {[offset][Ack]} {[S][addr][R][Nack]}
0187      * [wait conversion time]
0188      *  {[S][addr][R][Ack]} {[datahi][Ack]} {[datalo][Ack][P]}
0189      *
0190      * To implement the first part of this exchange,
0191      * do a full read transaction and expect a failure/Nack.
0192      * This sets up the address pointer on the SMM665
0193      * and starts the ADC conversion.
0194      * Then do a two-byte read transaction.
0195      */
0196     rv = i2c_smbus_read_byte_data(client, adc << 3);
0197     if (rv != -ENXIO) {
0198         /*
0199          * We expect ENXIO to reflect NACK
0200          * (per Documentation/i2c/fault-codes.rst).
0201          * Everything else is an error.
0202          */
0203         dev_dbg(&client->dev,
0204             "Unexpected return code %d when setting ADC index", rv);
0205         return (rv < 0) ? rv : -EIO;
0206     }
0207 
0208     udelay(data->conversion_time);
0209 
0210     /*
0211      * Now read two bytes.
0212      *
0213      * Neither i2c_smbus_read_byte() nor
0214      * i2c_smbus_read_block_data() worked here,
0215      * so use i2c_smbus_read_word_swapped() instead.
0216      * We could also try to use i2c_master_recv(),
0217      * but that is not always supported.
0218      */
0219     rv = i2c_smbus_read_word_swapped(client, 0);
0220     if (rv < 0) {
0221         dev_dbg(&client->dev, "Failed to read ADC value: error %d", rv);
0222         return rv;
0223     }
0224     /*
0225      * Validate/verify readback adc channel (in bit 11..14).
0226      */
0227     radc = (rv >> 11) & 0x0f;
0228     if (radc != adc) {
0229         dev_dbg(&client->dev, "Unexpected RADC: Expected %d got %d",
0230             adc, radc);
0231         return -EIO;
0232     }
0233 
0234     return rv & SMM665_ADC_MASK;
0235 }
0236 
0237 static struct smm665_data *smm665_update_device(struct device *dev)
0238 {
0239     struct smm665_data *data = dev_get_drvdata(dev);
0240     struct i2c_client *client = data->client;
0241     struct smm665_data *ret = data;
0242 
0243     mutex_lock(&data->update_lock);
0244 
0245     if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
0246         int i, val;
0247 
0248         /*
0249          * read status registers
0250          */
0251         val = smm665_read16(client, SMM665_MISC8_STATUS1);
0252         if (unlikely(val < 0)) {
0253             ret = ERR_PTR(val);
0254             goto abort;
0255         }
0256         data->faults = val;
0257 
0258         /* Read adc registers */
0259         for (i = 0; i < SMM665_NUM_ADC; i++) {
0260             val = smm665_read_adc(data, i);
0261             if (unlikely(val < 0)) {
0262                 ret = ERR_PTR(val);
0263                 goto abort;
0264             }
0265             data->adc[i] = val;
0266         }
0267         data->last_updated = jiffies;
0268         data->valid = true;
0269     }
0270 abort:
0271     mutex_unlock(&data->update_lock);
0272     return ret;
0273 }
0274 
0275 /* Return converted value from given adc */
0276 static int smm665_convert(u16 adcval, int index)
0277 {
0278     int val = 0;
0279 
0280     switch (index) {
0281     case SMM665_MISC16_ADC_DATA_12V:
0282         val = SMM665_12VIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
0283         break;
0284 
0285     case SMM665_MISC16_ADC_DATA_VDD:
0286     case SMM665_MISC16_ADC_DATA_A:
0287     case SMM665_MISC16_ADC_DATA_B:
0288     case SMM665_MISC16_ADC_DATA_C:
0289     case SMM665_MISC16_ADC_DATA_D:
0290     case SMM665_MISC16_ADC_DATA_E:
0291     case SMM665_MISC16_ADC_DATA_F:
0292         val = SMM665_VMON_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
0293         break;
0294 
0295     case SMM665_MISC16_ADC_DATA_AIN1:
0296     case SMM665_MISC16_ADC_DATA_AIN2:
0297         val = SMM665_AIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
0298         break;
0299 
0300     case SMM665_MISC16_ADC_DATA_INT_TEMP:
0301         val = SMM665_TEMP_ADC_TO_CELSIUS(adcval & SMM665_ADC_MASK);
0302         break;
0303 
0304     default:
0305         /* If we get here, the developer messed up */
0306         WARN_ON_ONCE(1);
0307         break;
0308     }
0309 
0310     return val;
0311 }
0312 
0313 static int smm665_get_min(struct device *dev, int index)
0314 {
0315     struct smm665_data *data = dev_get_drvdata(dev);
0316 
0317     return data->alarm_min_limit[index];
0318 }
0319 
0320 static int smm665_get_max(struct device *dev, int index)
0321 {
0322     struct smm665_data *data = dev_get_drvdata(dev);
0323 
0324     return data->alarm_max_limit[index];
0325 }
0326 
0327 static int smm665_get_lcrit(struct device *dev, int index)
0328 {
0329     struct smm665_data *data = dev_get_drvdata(dev);
0330 
0331     return data->critical_min_limit[index];
0332 }
0333 
0334 static int smm665_get_crit(struct device *dev, int index)
0335 {
0336     struct smm665_data *data = dev_get_drvdata(dev);
0337 
0338     return data->critical_max_limit[index];
0339 }
0340 
0341 static ssize_t smm665_show_crit_alarm(struct device *dev,
0342                       struct device_attribute *da, char *buf)
0343 {
0344     struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
0345     struct smm665_data *data = smm665_update_device(dev);
0346     int val = 0;
0347 
0348     if (IS_ERR(data))
0349         return PTR_ERR(data);
0350 
0351     if (data->faults & (1 << attr->index))
0352         val = 1;
0353 
0354     return sysfs_emit(buf, "%d\n", val);
0355 }
0356 
0357 static ssize_t smm665_show_input(struct device *dev,
0358                  struct device_attribute *da, char *buf)
0359 {
0360     struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
0361     struct smm665_data *data = smm665_update_device(dev);
0362     int adc = attr->index;
0363     int val;
0364 
0365     if (IS_ERR(data))
0366         return PTR_ERR(data);
0367 
0368     val = smm665_convert(data->adc[adc], adc);
0369     return sysfs_emit(buf, "%d\n", val);
0370 }
0371 
0372 #define SMM665_SHOW(what) \
0373 static ssize_t smm665_show_##what(struct device *dev, \
0374                     struct device_attribute *da, char *buf) \
0375 { \
0376     struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
0377     const int val = smm665_get_##what(dev, attr->index); \
0378     return snprintf(buf, PAGE_SIZE, "%d\n", val); \
0379 }
0380 
0381 SMM665_SHOW(min);
0382 SMM665_SHOW(max);
0383 SMM665_SHOW(lcrit);
0384 SMM665_SHOW(crit);
0385 
0386 /*
0387  * These macros are used below in constructing device attribute objects
0388  * for use with sysfs_create_group() to make a sysfs device file
0389  * for each register.
0390  */
0391 
0392 #define SMM665_ATTR(name, type, cmd_idx) \
0393     static SENSOR_DEVICE_ATTR(name##_##type, S_IRUGO, \
0394                   smm665_show_##type, NULL, cmd_idx)
0395 
0396 /* Construct a sensor_device_attribute structure for each register */
0397 
0398 /* Input voltages */
0399 SMM665_ATTR(in1, input, SMM665_MISC16_ADC_DATA_12V);
0400 SMM665_ATTR(in2, input, SMM665_MISC16_ADC_DATA_VDD);
0401 SMM665_ATTR(in3, input, SMM665_MISC16_ADC_DATA_A);
0402 SMM665_ATTR(in4, input, SMM665_MISC16_ADC_DATA_B);
0403 SMM665_ATTR(in5, input, SMM665_MISC16_ADC_DATA_C);
0404 SMM665_ATTR(in6, input, SMM665_MISC16_ADC_DATA_D);
0405 SMM665_ATTR(in7, input, SMM665_MISC16_ADC_DATA_E);
0406 SMM665_ATTR(in8, input, SMM665_MISC16_ADC_DATA_F);
0407 SMM665_ATTR(in9, input, SMM665_MISC16_ADC_DATA_AIN1);
0408 SMM665_ATTR(in10, input, SMM665_MISC16_ADC_DATA_AIN2);
0409 
0410 /* Input voltages min */
0411 SMM665_ATTR(in1, min, SMM665_MISC16_ADC_DATA_12V);
0412 SMM665_ATTR(in2, min, SMM665_MISC16_ADC_DATA_VDD);
0413 SMM665_ATTR(in3, min, SMM665_MISC16_ADC_DATA_A);
0414 SMM665_ATTR(in4, min, SMM665_MISC16_ADC_DATA_B);
0415 SMM665_ATTR(in5, min, SMM665_MISC16_ADC_DATA_C);
0416 SMM665_ATTR(in6, min, SMM665_MISC16_ADC_DATA_D);
0417 SMM665_ATTR(in7, min, SMM665_MISC16_ADC_DATA_E);
0418 SMM665_ATTR(in8, min, SMM665_MISC16_ADC_DATA_F);
0419 SMM665_ATTR(in9, min, SMM665_MISC16_ADC_DATA_AIN1);
0420 SMM665_ATTR(in10, min, SMM665_MISC16_ADC_DATA_AIN2);
0421 
0422 /* Input voltages max */
0423 SMM665_ATTR(in1, max, SMM665_MISC16_ADC_DATA_12V);
0424 SMM665_ATTR(in2, max, SMM665_MISC16_ADC_DATA_VDD);
0425 SMM665_ATTR(in3, max, SMM665_MISC16_ADC_DATA_A);
0426 SMM665_ATTR(in4, max, SMM665_MISC16_ADC_DATA_B);
0427 SMM665_ATTR(in5, max, SMM665_MISC16_ADC_DATA_C);
0428 SMM665_ATTR(in6, max, SMM665_MISC16_ADC_DATA_D);
0429 SMM665_ATTR(in7, max, SMM665_MISC16_ADC_DATA_E);
0430 SMM665_ATTR(in8, max, SMM665_MISC16_ADC_DATA_F);
0431 SMM665_ATTR(in9, max, SMM665_MISC16_ADC_DATA_AIN1);
0432 SMM665_ATTR(in10, max, SMM665_MISC16_ADC_DATA_AIN2);
0433 
0434 /* Input voltages lcrit */
0435 SMM665_ATTR(in1, lcrit, SMM665_MISC16_ADC_DATA_12V);
0436 SMM665_ATTR(in2, lcrit, SMM665_MISC16_ADC_DATA_VDD);
0437 SMM665_ATTR(in3, lcrit, SMM665_MISC16_ADC_DATA_A);
0438 SMM665_ATTR(in4, lcrit, SMM665_MISC16_ADC_DATA_B);
0439 SMM665_ATTR(in5, lcrit, SMM665_MISC16_ADC_DATA_C);
0440 SMM665_ATTR(in6, lcrit, SMM665_MISC16_ADC_DATA_D);
0441 SMM665_ATTR(in7, lcrit, SMM665_MISC16_ADC_DATA_E);
0442 SMM665_ATTR(in8, lcrit, SMM665_MISC16_ADC_DATA_F);
0443 SMM665_ATTR(in9, lcrit, SMM665_MISC16_ADC_DATA_AIN1);
0444 SMM665_ATTR(in10, lcrit, SMM665_MISC16_ADC_DATA_AIN2);
0445 
0446 /* Input voltages crit */
0447 SMM665_ATTR(in1, crit, SMM665_MISC16_ADC_DATA_12V);
0448 SMM665_ATTR(in2, crit, SMM665_MISC16_ADC_DATA_VDD);
0449 SMM665_ATTR(in3, crit, SMM665_MISC16_ADC_DATA_A);
0450 SMM665_ATTR(in4, crit, SMM665_MISC16_ADC_DATA_B);
0451 SMM665_ATTR(in5, crit, SMM665_MISC16_ADC_DATA_C);
0452 SMM665_ATTR(in6, crit, SMM665_MISC16_ADC_DATA_D);
0453 SMM665_ATTR(in7, crit, SMM665_MISC16_ADC_DATA_E);
0454 SMM665_ATTR(in8, crit, SMM665_MISC16_ADC_DATA_F);
0455 SMM665_ATTR(in9, crit, SMM665_MISC16_ADC_DATA_AIN1);
0456 SMM665_ATTR(in10, crit, SMM665_MISC16_ADC_DATA_AIN2);
0457 
0458 /* critical alarms */
0459 SMM665_ATTR(in1, crit_alarm, SMM665_FAULT_12V);
0460 SMM665_ATTR(in2, crit_alarm, SMM665_FAULT_VDD);
0461 SMM665_ATTR(in3, crit_alarm, SMM665_FAULT_A);
0462 SMM665_ATTR(in4, crit_alarm, SMM665_FAULT_B);
0463 SMM665_ATTR(in5, crit_alarm, SMM665_FAULT_C);
0464 SMM665_ATTR(in6, crit_alarm, SMM665_FAULT_D);
0465 SMM665_ATTR(in7, crit_alarm, SMM665_FAULT_E);
0466 SMM665_ATTR(in8, crit_alarm, SMM665_FAULT_F);
0467 SMM665_ATTR(in9, crit_alarm, SMM665_FAULT_AIN1);
0468 SMM665_ATTR(in10, crit_alarm, SMM665_FAULT_AIN2);
0469 
0470 /* Temperature */
0471 SMM665_ATTR(temp1, input, SMM665_MISC16_ADC_DATA_INT_TEMP);
0472 SMM665_ATTR(temp1, min, SMM665_MISC16_ADC_DATA_INT_TEMP);
0473 SMM665_ATTR(temp1, max, SMM665_MISC16_ADC_DATA_INT_TEMP);
0474 SMM665_ATTR(temp1, lcrit, SMM665_MISC16_ADC_DATA_INT_TEMP);
0475 SMM665_ATTR(temp1, crit, SMM665_MISC16_ADC_DATA_INT_TEMP);
0476 SMM665_ATTR(temp1, crit_alarm, SMM665_FAULT_TEMP);
0477 
0478 /*
0479  * Finally, construct an array of pointers to members of the above objects,
0480  * as required for sysfs_create_group()
0481  */
0482 static struct attribute *smm665_attrs[] = {
0483     &sensor_dev_attr_in1_input.dev_attr.attr,
0484     &sensor_dev_attr_in1_min.dev_attr.attr,
0485     &sensor_dev_attr_in1_max.dev_attr.attr,
0486     &sensor_dev_attr_in1_lcrit.dev_attr.attr,
0487     &sensor_dev_attr_in1_crit.dev_attr.attr,
0488     &sensor_dev_attr_in1_crit_alarm.dev_attr.attr,
0489 
0490     &sensor_dev_attr_in2_input.dev_attr.attr,
0491     &sensor_dev_attr_in2_min.dev_attr.attr,
0492     &sensor_dev_attr_in2_max.dev_attr.attr,
0493     &sensor_dev_attr_in2_lcrit.dev_attr.attr,
0494     &sensor_dev_attr_in2_crit.dev_attr.attr,
0495     &sensor_dev_attr_in2_crit_alarm.dev_attr.attr,
0496 
0497     &sensor_dev_attr_in3_input.dev_attr.attr,
0498     &sensor_dev_attr_in3_min.dev_attr.attr,
0499     &sensor_dev_attr_in3_max.dev_attr.attr,
0500     &sensor_dev_attr_in3_lcrit.dev_attr.attr,
0501     &sensor_dev_attr_in3_crit.dev_attr.attr,
0502     &sensor_dev_attr_in3_crit_alarm.dev_attr.attr,
0503 
0504     &sensor_dev_attr_in4_input.dev_attr.attr,
0505     &sensor_dev_attr_in4_min.dev_attr.attr,
0506     &sensor_dev_attr_in4_max.dev_attr.attr,
0507     &sensor_dev_attr_in4_lcrit.dev_attr.attr,
0508     &sensor_dev_attr_in4_crit.dev_attr.attr,
0509     &sensor_dev_attr_in4_crit_alarm.dev_attr.attr,
0510 
0511     &sensor_dev_attr_in5_input.dev_attr.attr,
0512     &sensor_dev_attr_in5_min.dev_attr.attr,
0513     &sensor_dev_attr_in5_max.dev_attr.attr,
0514     &sensor_dev_attr_in5_lcrit.dev_attr.attr,
0515     &sensor_dev_attr_in5_crit.dev_attr.attr,
0516     &sensor_dev_attr_in5_crit_alarm.dev_attr.attr,
0517 
0518     &sensor_dev_attr_in6_input.dev_attr.attr,
0519     &sensor_dev_attr_in6_min.dev_attr.attr,
0520     &sensor_dev_attr_in6_max.dev_attr.attr,
0521     &sensor_dev_attr_in6_lcrit.dev_attr.attr,
0522     &sensor_dev_attr_in6_crit.dev_attr.attr,
0523     &sensor_dev_attr_in6_crit_alarm.dev_attr.attr,
0524 
0525     &sensor_dev_attr_in7_input.dev_attr.attr,
0526     &sensor_dev_attr_in7_min.dev_attr.attr,
0527     &sensor_dev_attr_in7_max.dev_attr.attr,
0528     &sensor_dev_attr_in7_lcrit.dev_attr.attr,
0529     &sensor_dev_attr_in7_crit.dev_attr.attr,
0530     &sensor_dev_attr_in7_crit_alarm.dev_attr.attr,
0531 
0532     &sensor_dev_attr_in8_input.dev_attr.attr,
0533     &sensor_dev_attr_in8_min.dev_attr.attr,
0534     &sensor_dev_attr_in8_max.dev_attr.attr,
0535     &sensor_dev_attr_in8_lcrit.dev_attr.attr,
0536     &sensor_dev_attr_in8_crit.dev_attr.attr,
0537     &sensor_dev_attr_in8_crit_alarm.dev_attr.attr,
0538 
0539     &sensor_dev_attr_in9_input.dev_attr.attr,
0540     &sensor_dev_attr_in9_min.dev_attr.attr,
0541     &sensor_dev_attr_in9_max.dev_attr.attr,
0542     &sensor_dev_attr_in9_lcrit.dev_attr.attr,
0543     &sensor_dev_attr_in9_crit.dev_attr.attr,
0544     &sensor_dev_attr_in9_crit_alarm.dev_attr.attr,
0545 
0546     &sensor_dev_attr_in10_input.dev_attr.attr,
0547     &sensor_dev_attr_in10_min.dev_attr.attr,
0548     &sensor_dev_attr_in10_max.dev_attr.attr,
0549     &sensor_dev_attr_in10_lcrit.dev_attr.attr,
0550     &sensor_dev_attr_in10_crit.dev_attr.attr,
0551     &sensor_dev_attr_in10_crit_alarm.dev_attr.attr,
0552 
0553     &sensor_dev_attr_temp1_input.dev_attr.attr,
0554     &sensor_dev_attr_temp1_min.dev_attr.attr,
0555     &sensor_dev_attr_temp1_max.dev_attr.attr,
0556     &sensor_dev_attr_temp1_lcrit.dev_attr.attr,
0557     &sensor_dev_attr_temp1_crit.dev_attr.attr,
0558     &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
0559 
0560     NULL,
0561 };
0562 
0563 ATTRIBUTE_GROUPS(smm665);
0564 
0565 static const struct i2c_device_id smm665_id[];
0566 
0567 static int smm665_probe(struct i2c_client *client)
0568 {
0569     struct i2c_adapter *adapter = client->adapter;
0570     struct smm665_data *data;
0571     struct device *hwmon_dev;
0572     int i, ret;
0573 
0574     if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA
0575                      | I2C_FUNC_SMBUS_WORD_DATA))
0576         return -ENODEV;
0577 
0578     if (i2c_smbus_read_byte_data(client, SMM665_ADOC_ENABLE) < 0)
0579         return -ENODEV;
0580 
0581     data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
0582     if (!data)
0583         return -ENOMEM;
0584 
0585     i2c_set_clientdata(client, data);
0586     mutex_init(&data->update_lock);
0587 
0588     data->client = client;
0589     data->type = i2c_match_id(smm665_id, client)->driver_data;
0590     data->cmdreg = i2c_new_dummy_device(adapter, (client->addr & ~SMM665_REGMASK)
0591                      | SMM665_CMDREG_BASE);
0592     if (IS_ERR(data->cmdreg))
0593         return PTR_ERR(data->cmdreg);
0594 
0595     switch (data->type) {
0596     case smm465:
0597     case smm665:
0598         data->conversion_time = SMM665_ADC_WAIT_SMM665;
0599         break;
0600     case smm665c:
0601     case smm764:
0602     case smm766:
0603         data->conversion_time = SMM665_ADC_WAIT_SMM766;
0604         break;
0605     }
0606 
0607     ret = -ENODEV;
0608     if (i2c_smbus_read_byte_data(data->cmdreg, SMM665_MISC8_CMD_STS) < 0)
0609         goto out_unregister;
0610 
0611     /*
0612      * Read limits.
0613      *
0614      * Limit registers start with register SMM665_LIMIT_BASE.
0615      * Each channel uses 8 registers, providing four limit values
0616      * per channel. Each limit value requires two registers, with the
0617      * high byte in the first register and the low byte in the second
0618      * register. The first two limits are under limit values, followed
0619      * by two over limit values.
0620      *
0621      * Limit register order matches the ADC register order, so we use
0622      * ADC register defines throughout the code to index limit registers.
0623      *
0624      * We save the first retrieved value both as "critical" and "alarm"
0625      * value. The second value overwrites either the critical or the
0626      * alarm value, depending on its configuration. This ensures that both
0627      * critical and alarm values are initialized, even if both registers are
0628      * configured as critical or non-critical.
0629      */
0630     for (i = 0; i < SMM665_NUM_ADC; i++) {
0631         int val;
0632 
0633         val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8);
0634         if (unlikely(val < 0))
0635             goto out_unregister;
0636         data->critical_min_limit[i] = data->alarm_min_limit[i]
0637           = smm665_convert(val, i);
0638         val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 2);
0639         if (unlikely(val < 0))
0640             goto out_unregister;
0641         if (smm665_is_critical(val))
0642             data->critical_min_limit[i] = smm665_convert(val, i);
0643         else
0644             data->alarm_min_limit[i] = smm665_convert(val, i);
0645         val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 4);
0646         if (unlikely(val < 0))
0647             goto out_unregister;
0648         data->critical_max_limit[i] = data->alarm_max_limit[i]
0649           = smm665_convert(val, i);
0650         val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 6);
0651         if (unlikely(val < 0))
0652             goto out_unregister;
0653         if (smm665_is_critical(val))
0654             data->critical_max_limit[i] = smm665_convert(val, i);
0655         else
0656             data->alarm_max_limit[i] = smm665_convert(val, i);
0657     }
0658 
0659     hwmon_dev = devm_hwmon_device_register_with_groups(&client->dev,
0660                                client->name, data,
0661                                smm665_groups);
0662     if (IS_ERR(hwmon_dev)) {
0663         ret = PTR_ERR(hwmon_dev);
0664         goto out_unregister;
0665     }
0666 
0667     return 0;
0668 
0669 out_unregister:
0670     i2c_unregister_device(data->cmdreg);
0671     return ret;
0672 }
0673 
0674 static int smm665_remove(struct i2c_client *client)
0675 {
0676     struct smm665_data *data = i2c_get_clientdata(client);
0677 
0678     i2c_unregister_device(data->cmdreg);
0679     return 0;
0680 }
0681 
0682 static const struct i2c_device_id smm665_id[] = {
0683     {"smm465", smm465},
0684     {"smm665", smm665},
0685     {"smm665c", smm665c},
0686     {"smm764", smm764},
0687     {"smm766", smm766},
0688     {}
0689 };
0690 
0691 MODULE_DEVICE_TABLE(i2c, smm665_id);
0692 
0693 /* This is the driver that will be inserted */
0694 static struct i2c_driver smm665_driver = {
0695     .driver = {
0696            .name = "smm665",
0697            },
0698     .probe_new = smm665_probe,
0699     .remove = smm665_remove,
0700     .id_table = smm665_id,
0701 };
0702 
0703 module_i2c_driver(smm665_driver);
0704 
0705 MODULE_AUTHOR("Guenter Roeck");
0706 MODULE_DESCRIPTION("SMM665 driver");
0707 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!