hwmon/occ/p8_i2c.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Copyright IBM Corp 2019
0003
0004 #include <linux/device.h>
0005 #include <linux/errno.h>
0006 #include <linux/fsi-occ.h>
0007 #include <linux/i2c.h>
0008 #include <linux/jiffies.h>
0009 #include <linux/module.h>
0010 #include <linux/sched.h>
0011 #include <asm/unaligned.h>
0012
0013 #include "common.h"
0014
0015 #define OCC_TIMEOUT_MS          1000
0016 #define OCC_CMD_IN_PRG_WAIT_MS      50
0017
0018 /* OCB (on-chip control bridge - interface to OCC) registers */
0019 #define OCB_DATA1           0x6B035
0020 #define OCB_ADDR            0x6B070
0021 #define OCB_DATA3           0x6B075
0022
0023 /* OCC SRAM address space */
0024 #define OCC_SRAM_ADDR_CMD       0xFFFF6000
0025 #define OCC_SRAM_ADDR_RESP      0xFFFF7000
0026
0027 #define OCC_DATA_ATTN           0x20010000
0028
0029 struct p8_i2c_occ {
0030     struct occ occ;
0031     struct i2c_client *client;
0032 };
0033
0034 #define to_p8_i2c_occ(x)    container_of((x), struct p8_i2c_occ, occ)
0035
0036 static int p8_i2c_occ_getscom(struct i2c_client *client, u32 address, u8 *data)
0037 {
0038     ssize_t rc;
0039     __be64 buf;
0040     struct i2c_msg msgs[2];
0041
0042     /* p8 i2c slave requires shift */
0043     address <<= 1;
0044
0045     msgs[0].addr = client->addr;
0046     msgs[0].flags = client->flags & I2C_M_TEN;
0047     msgs[0].len = sizeof(u32);
0048     /* address is a scom address; bus-endian */
0049     msgs[0].buf = (char *)&address;
0050
0051     /* data from OCC is big-endian */
0052     msgs[1].addr = client->addr;
0053     msgs[1].flags = (client->flags & I2C_M_TEN) | I2C_M_RD;
0054     msgs[1].len = sizeof(u64);
0055     msgs[1].buf = (char *)&buf;
0056
0057     rc = i2c_transfer(client->adapter, msgs, 2);
0058     if (rc < 0)
0059         return rc;
0060
0061     *(u64 *)data = be64_to_cpu(buf);
0062
0063     return 0;
0064 }
0065
0066 static int p8_i2c_occ_putscom(struct i2c_client *client, u32 address, u8 *data)
0067 {
0068     u32 buf[3];
0069     ssize_t rc;
0070
0071     /* p8 i2c slave requires shift */
0072     address <<= 1;
0073
0074     /* address is bus-endian; data passed through from user as-is */
0075     buf[0] = address;
0076     memcpy(&buf[1], &data[4], sizeof(u32));
0077     memcpy(&buf[2], data, sizeof(u32));
0078
0079     rc = i2c_master_send(client, (const char *)buf, sizeof(buf));
0080     if (rc < 0)
0081         return rc;
0082     else if (rc != sizeof(buf))
0083         return -EIO;
0084
0085     return 0;
0086 }
0087
0088 static int p8_i2c_occ_putscom_u32(struct i2c_client *client, u32 address,
0089                   u32 data0, u32 data1)
0090 {
0091     u8 buf[8];
0092
0093     memcpy(buf, &data0, 4);
0094     memcpy(buf + 4, &data1, 4);
0095
0096     return p8_i2c_occ_putscom(client, address, buf);
0097 }
0098
0099 static int p8_i2c_occ_putscom_be(struct i2c_client *client, u32 address,
0100                  u8 *data, size_t len)
0101 {
0102     __be32 data0 = 0, data1 = 0;
0103
0104     memcpy(&data0, data, min_t(size_t, len, 4));
0105     if (len > 4) {
0106         len -= 4;
0107         memcpy(&data1, data + 4, min_t(size_t, len, 4));
0108     }
0109
0110     return p8_i2c_occ_putscom_u32(client, address, be32_to_cpu(data0),
0111                       be32_to_cpu(data1));
0112 }
0113
0114 static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd, size_t len,
0115                    void *resp, size_t resp_len)
0116 {
0117     int i, rc;
0118     unsigned long start;
0119     u16 data_length;
0120     const unsigned long timeout = msecs_to_jiffies(OCC_TIMEOUT_MS);
0121     const long wait_time = msecs_to_jiffies(OCC_CMD_IN_PRG_WAIT_MS);
0122     struct p8_i2c_occ *ctx = to_p8_i2c_occ(occ);
0123     struct i2c_client *client = ctx->client;
0124     struct occ_response *or = (struct occ_response *)resp;
0125
0126     start = jiffies;
0127
0128     /* set sram address for command */
0129     rc = p8_i2c_occ_putscom_u32(client, OCB_ADDR, OCC_SRAM_ADDR_CMD, 0);
0130     if (rc)
0131         return rc;
0132
0133     /* write command (expected to already be BE), we need bus-endian... */
0134     rc = p8_i2c_occ_putscom_be(client, OCB_DATA3, cmd, len);
0135     if (rc)
0136         return rc;
0137
0138     /* trigger OCC attention */
0139     rc = p8_i2c_occ_putscom_u32(client, OCB_DATA1, OCC_DATA_ATTN, 0);
0140     if (rc)
0141         return rc;
0142
0143     do {
0144         /* set sram address for response */
0145         rc = p8_i2c_occ_putscom_u32(client, OCB_ADDR,
0146                         OCC_SRAM_ADDR_RESP, 0);
0147         if (rc)
0148             return rc;
0149
0150         rc = p8_i2c_occ_getscom(client, OCB_DATA3, (u8 *)resp);
0151         if (rc)
0152             return rc;
0153
0154         /* wait for OCC */
0155         if (or->return_status == OCC_RESP_CMD_IN_PRG) {
0156             rc = -EALREADY;
0157
0158             if (time_after(jiffies, start + timeout))
0159                 break;
0160
0161             set_current_state(TASK_INTERRUPTIBLE);
0162             schedule_timeout(wait_time);
0163         }
0164     } while (rc);
0165
0166     /* check the OCC response */
0167     switch (or->return_status) {
0168     case OCC_RESP_CMD_IN_PRG:
0169         rc = -ETIMEDOUT;
0170         break;
0171     case OCC_RESP_SUCCESS:
0172         rc = 0;
0173         break;
0174     case OCC_RESP_CMD_INVAL:
0175     case OCC_RESP_CMD_LEN_INVAL:
0176     case OCC_RESP_DATA_INVAL:
0177     case OCC_RESP_CHKSUM_ERR:
0178         rc = -EINVAL;
0179         break;
0180     case OCC_RESP_INT_ERR:
0181     case OCC_RESP_BAD_STATE:
0182     case OCC_RESP_CRIT_EXCEPT:
0183     case OCC_RESP_CRIT_INIT:
0184     case OCC_RESP_CRIT_WATCHDOG:
0185     case OCC_RESP_CRIT_OCB:
0186     case OCC_RESP_CRIT_HW:
0187         rc = -EREMOTEIO;
0188         break;
0189     default:
0190         rc = -EPROTO;
0191     }
0192
0193     if (rc < 0)
0194         return rc;
0195
0196     data_length = get_unaligned_be16(&or->data_length);
0197     if ((data_length + 7) > resp_len)
0198         return -EMSGSIZE;
0199
0200     /* fetch the rest of the response data */
0201     for (i = 8; i < data_length + 7; i += 8) {
0202         rc = p8_i2c_occ_getscom(client, OCB_DATA3, ((u8 *)resp) + i);
0203         if (rc)
0204             return rc;
0205     }
0206
0207     return 0;
0208 }
0209
0210 static int p8_i2c_occ_probe(struct i2c_client *client)
0211 {
0212     struct occ *occ;
0213     struct p8_i2c_occ *ctx = devm_kzalloc(&client->dev, sizeof(*ctx),
0214                           GFP_KERNEL);
0215     if (!ctx)
0216         return -ENOMEM;
0217
0218     ctx->client = client;
0219     occ = &ctx->occ;
0220     occ->bus_dev = &client->dev;
0221     dev_set_drvdata(&client->dev, occ);
0222
0223     occ->powr_sample_time_us = 250;
0224     occ->poll_cmd_data = 0x10;      /* P8 OCC poll data */
0225     occ->send_cmd = p8_i2c_occ_send_cmd;
0226
0227     return occ_setup(occ);
0228 }
0229
0230 static int p8_i2c_occ_remove(struct i2c_client *client)
0231 {
0232     struct occ *occ = dev_get_drvdata(&client->dev);
0233
0234     occ_shutdown(occ);
0235
0236     return 0;
0237 }
0238
0239 static const struct of_device_id p8_i2c_occ_of_match[] = {
0240     { .compatible = "ibm,p8-occ-hwmon" },
0241     {}
0242 };
0243 MODULE_DEVICE_TABLE(of, p8_i2c_occ_of_match);
0244
0245 static struct i2c_driver p8_i2c_occ_driver = {
0246     .class = I2C_CLASS_HWMON,
0247     .driver = {
0248         .name = "occ-hwmon",
0249         .of_match_table = p8_i2c_occ_of_match,
0250     },
0251     .probe_new = p8_i2c_occ_probe,
0252     .remove = p8_i2c_occ_remove,
0253 };
0254
0255 module_i2c_driver(p8_i2c_occ_driver);
0256
0257 MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
0258 MODULE_DESCRIPTION("BMC P8 OCC hwmon driver");
0259 MODULE_LICENSE("GPL");