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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
0003 
0004 #include <linux/clk.h>
0005 #include <linux/device.h>
0006 #include <linux/hwmon.h>
0007 #include <linux/hwmon-sysfs.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/thermal.h>
0017 
0018 /* NPCM7XX PWM registers */
0019 #define NPCM7XX_PWM_REG_BASE(base, n)    ((base) + ((n) * 0x1000L))
0020 
0021 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
0022 #define NPCM7XX_PWM_REG_CSR(base, n)    (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
0023 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
0024 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
0025             (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
0026 #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
0027             (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
0028 #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
0029             (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
0030 #define NPCM7XX_PWM_REG_PIER(base, n)   (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
0031 #define NPCM7XX_PWM_REG_PIIR(base, n)   (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
0032 
0033 #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT       BIT(3)
0034 #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT       BIT(11)
0035 #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT       BIT(15)
0036 #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT       BIT(19)
0037 
0038 #define NPCM7XX_PWM_CTRL_CH0_INV_BIT        BIT(2)
0039 #define NPCM7XX_PWM_CTRL_CH1_INV_BIT        BIT(10)
0040 #define NPCM7XX_PWM_CTRL_CH2_INV_BIT        BIT(14)
0041 #define NPCM7XX_PWM_CTRL_CH3_INV_BIT        BIT(18)
0042 
0043 #define NPCM7XX_PWM_CTRL_CH0_EN_BIT     BIT(0)
0044 #define NPCM7XX_PWM_CTRL_CH1_EN_BIT     BIT(8)
0045 #define NPCM7XX_PWM_CTRL_CH2_EN_BIT     BIT(12)
0046 #define NPCM7XX_PWM_CTRL_CH3_EN_BIT     BIT(16)
0047 
0048 /* Define the maximum PWM channel number */
0049 #define NPCM7XX_PWM_MAX_CHN_NUM         8
0050 #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
0051 #define NPCM7XX_PWM_MAX_MODULES                 2
0052 
0053 /* Define the Counter Register, value = 100 for match 100% */
0054 #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM     255
0055 #define NPCM7XX_PWM_CMR_DEFAULT_NUM     255
0056 #define NPCM7XX_PWM_CMR_MAX         255
0057 
0058 /* default all PWM channels PRESCALE2 = 1 */
0059 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0   0x4
0060 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1   0x40
0061 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2   0x400
0062 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3   0x4000
0063 
0064 #define PWM_OUTPUT_FREQ_25KHZ           25000
0065 #define PWN_CNT_DEFAULT             256
0066 #define MIN_PRESCALE1               2
0067 #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01     8
0068 
0069 #define NPCM7XX_PWM_PRESCALE2_DEFAULT   (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
0070                     NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
0071                     NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
0072                     NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
0073 
0074 #define NPCM7XX_PWM_CTRL_MODE_DEFAULT   (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
0075                     NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
0076                     NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
0077                     NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
0078 
0079 /* NPCM7XX FAN Tacho registers */
0080 #define NPCM7XX_FAN_REG_BASE(base, n)   ((base) + ((n) * 0x1000L))
0081 
0082 #define NPCM7XX_FAN_REG_TCNT1(base, n)    (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
0083 #define NPCM7XX_FAN_REG_TCRA(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
0084 #define NPCM7XX_FAN_REG_TCRB(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
0085 #define NPCM7XX_FAN_REG_TCNT2(base, n)    (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
0086 #define NPCM7XX_FAN_REG_TPRSC(base, n)    (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
0087 #define NPCM7XX_FAN_REG_TCKC(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
0088 #define NPCM7XX_FAN_REG_TMCTRL(base, n)   (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
0089 #define NPCM7XX_FAN_REG_TICTRL(base, n)   (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
0090 #define NPCM7XX_FAN_REG_TICLR(base, n)    (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
0091 #define NPCM7XX_FAN_REG_TIEN(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
0092 #define NPCM7XX_FAN_REG_TCPA(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
0093 #define NPCM7XX_FAN_REG_TCPB(base, n)     (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
0094 #define NPCM7XX_FAN_REG_TCPCFG(base, n)   (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
0095 #define NPCM7XX_FAN_REG_TINASEL(base, n)  (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
0096 #define NPCM7XX_FAN_REG_TINBSEL(base, n)  (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
0097 
0098 #define NPCM7XX_FAN_TCKC_CLKX_NONE  0
0099 #define NPCM7XX_FAN_TCKC_CLK1_APB   BIT(0)
0100 #define NPCM7XX_FAN_TCKC_CLK2_APB   BIT(3)
0101 
0102 #define NPCM7XX_FAN_TMCTRL_TBEN     BIT(6)
0103 #define NPCM7XX_FAN_TMCTRL_TAEN     BIT(5)
0104 #define NPCM7XX_FAN_TMCTRL_TBEDG    BIT(4)
0105 #define NPCM7XX_FAN_TMCTRL_TAEDG    BIT(3)
0106 #define NPCM7XX_FAN_TMCTRL_MODE_5   BIT(2)
0107 
0108 #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
0109 #define NPCM7XX_FAN_TICLR_TFCLR     BIT(5)
0110 #define NPCM7XX_FAN_TICLR_TECLR     BIT(4)
0111 #define NPCM7XX_FAN_TICLR_TDCLR     BIT(3)
0112 #define NPCM7XX_FAN_TICLR_TCCLR     BIT(2)
0113 #define NPCM7XX_FAN_TICLR_TBCLR     BIT(1)
0114 #define NPCM7XX_FAN_TICLR_TACLR     BIT(0)
0115 
0116 #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
0117 #define NPCM7XX_FAN_TIEN_TFIEN      BIT(5)
0118 #define NPCM7XX_FAN_TIEN_TEIEN      BIT(4)
0119 #define NPCM7XX_FAN_TIEN_TDIEN      BIT(3)
0120 #define NPCM7XX_FAN_TIEN_TCIEN      BIT(2)
0121 #define NPCM7XX_FAN_TIEN_TBIEN      BIT(1)
0122 #define NPCM7XX_FAN_TIEN_TAIEN      BIT(0)
0123 
0124 #define NPCM7XX_FAN_TICTRL_TFPND    BIT(5)
0125 #define NPCM7XX_FAN_TICTRL_TEPND    BIT(4)
0126 #define NPCM7XX_FAN_TICTRL_TDPND    BIT(3)
0127 #define NPCM7XX_FAN_TICTRL_TCPND    BIT(2)
0128 #define NPCM7XX_FAN_TICTRL_TBPND    BIT(1)
0129 #define NPCM7XX_FAN_TICTRL_TAPND    BIT(0)
0130 
0131 #define NPCM7XX_FAN_TCPCFG_HIBEN    BIT(7)
0132 #define NPCM7XX_FAN_TCPCFG_EQBEN    BIT(6)
0133 #define NPCM7XX_FAN_TCPCFG_LOBEN    BIT(5)
0134 #define NPCM7XX_FAN_TCPCFG_CPBSEL   BIT(4)
0135 #define NPCM7XX_FAN_TCPCFG_HIAEN    BIT(3)
0136 #define NPCM7XX_FAN_TCPCFG_EQAEN    BIT(2)
0137 #define NPCM7XX_FAN_TCPCFG_LOAEN    BIT(1)
0138 #define NPCM7XX_FAN_TCPCFG_CPASEL   BIT(0)
0139 
0140 /* FAN General Definition */
0141 /* Define the maximum FAN channel number */
0142 #define NPCM7XX_FAN_MAX_MODULE          8
0143 #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
0144 #define NPCM7XX_FAN_MAX_CHN_NUM         16
0145 
0146 /*
0147  * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
0148  * Timeout 94ms ~= 0x5000
0149  * (The minimum FAN speed could to support ~640RPM/pulse 1,
0150  * 320RPM/pulse 2, ...-- 10.6Hz)
0151  */
0152 #define NPCM7XX_FAN_TIMEOUT 0x5000
0153 #define NPCM7XX_FAN_TCNT    0xFFFF
0154 #define NPCM7XX_FAN_TCPA    (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
0155 #define NPCM7XX_FAN_TCPB    (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
0156 
0157 #define NPCM7XX_FAN_POLL_TIMER_200MS            200
0158 #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION    2
0159 #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT       0
0160 #define NPCM7XX_FAN_CLK_PRESCALE            255
0161 
0162 #define NPCM7XX_FAN_CMPA                0
0163 #define NPCM7XX_FAN_CMPB                1
0164 
0165 /* Obtain the fan number */
0166 #define NPCM7XX_FAN_INPUT(fan, cmp)     (((fan) << 1) + (cmp))
0167 
0168 /* fan sample status */
0169 #define FAN_DISABLE             0xFF
0170 #define FAN_INIT                0x00
0171 #define FAN_PREPARE_TO_GET_FIRST_CAPTURE    0x01
0172 #define FAN_ENOUGH_SAMPLE           0x02
0173 
0174 struct npcm7xx_fan_dev {
0175     u8 fan_st_flg;
0176     u8 fan_pls_per_rev;
0177     u16 fan_cnt;
0178     u32 fan_cnt_tmp;
0179 };
0180 
0181 struct npcm7xx_cooling_device {
0182     char name[THERMAL_NAME_LENGTH];
0183     struct npcm7xx_pwm_fan_data *data;
0184     struct thermal_cooling_device *tcdev;
0185     int pwm_port;
0186     u8 *cooling_levels;
0187     u8 max_state;
0188     u8 cur_state;
0189 };
0190 
0191 struct npcm7xx_pwm_fan_data {
0192     void __iomem *pwm_base;
0193     void __iomem *fan_base;
0194     unsigned long pwm_clk_freq;
0195     unsigned long fan_clk_freq;
0196     struct clk *pwm_clk;
0197     struct clk *fan_clk;
0198     struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];
0199     spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
0200     int fan_irq[NPCM7XX_FAN_MAX_MODULE];
0201     bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
0202     bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
0203     u32 input_clk_freq;
0204     struct timer_list fan_timer;
0205     struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
0206     struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
0207     u8 fan_select;
0208 };
0209 
0210 static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
0211                   int channel, u16 val)
0212 {
0213     u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
0214     u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
0215     u32 tmp_buf, ctrl_en_bit, env_bit;
0216 
0217     /*
0218      * Config PWM Comparator register for setting duty cycle
0219      */
0220     mutex_lock(&data->pwm_lock[module]);
0221 
0222     /* write new CMR value  */
0223     iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
0224     tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
0225 
0226     switch (pwm_ch) {
0227     case 0:
0228         ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
0229         env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
0230         break;
0231     case 1:
0232         ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
0233         env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
0234         break;
0235     case 2:
0236         ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
0237         env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
0238         break;
0239     case 3:
0240         ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
0241         env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
0242         break;
0243     default:
0244         mutex_unlock(&data->pwm_lock[module]);
0245         return -ENODEV;
0246     }
0247 
0248     if (val == 0) {
0249         /* Disable PWM */
0250         tmp_buf &= ~ctrl_en_bit;
0251         tmp_buf |= env_bit;
0252     } else {
0253         /* Enable PWM */
0254         tmp_buf |= ctrl_en_bit;
0255         tmp_buf &= ~env_bit;
0256     }
0257 
0258     iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
0259     mutex_unlock(&data->pwm_lock[module]);
0260 
0261     return 0;
0262 }
0263 
0264 static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
0265                          u8 fan, u8 cmp)
0266 {
0267     u8 fan_id;
0268     u8 reg_mode;
0269     u8 reg_int;
0270     unsigned long flags;
0271 
0272     fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
0273 
0274     /* to check whether any fan tach is enable */
0275     if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
0276         /* reset status */
0277         spin_lock_irqsave(&data->fan_lock[fan], flags);
0278 
0279         data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
0280         reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0281 
0282         /*
0283          * the interrupt enable bits do not need to be cleared before
0284          * it sets, the interrupt enable bits are cleared only on reset.
0285          * the clock unit control register is behaving in the same
0286          * manner that the interrupt enable register behave.
0287          */
0288         if (cmp == NPCM7XX_FAN_CMPA) {
0289             /* enable interrupt */
0290             iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
0291                         NPCM7XX_FAN_TIEN_TEIEN),
0292                  NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0293 
0294             reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
0295                 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
0296                                    fan));
0297 
0298             /* start to Capture */
0299             iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
0300                                 fan));
0301         } else {
0302             /* enable interrupt */
0303             iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
0304                         NPCM7XX_FAN_TIEN_TFIEN),
0305                  NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0306 
0307             reg_mode =
0308                 NPCM7XX_FAN_TCKC_CLK2_APB
0309                 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
0310                                    fan));
0311 
0312             /* start to Capture */
0313             iowrite8(reg_mode,
0314                  NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
0315         }
0316 
0317         spin_unlock_irqrestore(&data->fan_lock[fan], flags);
0318     }
0319 }
0320 
0321 /*
0322  * Enable a background timer to poll fan tach value, (200ms * 4)
0323  * to polling all fan
0324  */
0325 static void npcm7xx_fan_polling(struct timer_list *t)
0326 {
0327     struct npcm7xx_pwm_fan_data *data;
0328     int i;
0329 
0330     data = from_timer(data, t, fan_timer);
0331 
0332     /*
0333      * Polling two module per one round,
0334      * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
0335      */
0336     for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
0337           i = i + 4) {
0338         /* clear the flag and reset the counter (TCNT) */
0339         iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
0340              NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
0341 
0342         if (data->fan_present[i * 2]) {
0343             iowrite16(NPCM7XX_FAN_TCNT,
0344                   NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
0345             npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
0346         }
0347         if (data->fan_present[(i * 2) + 1]) {
0348             iowrite16(NPCM7XX_FAN_TCNT,
0349                   NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
0350             npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
0351         }
0352     }
0353 
0354     data->fan_select++;
0355     data->fan_select &= 0x3;
0356 
0357     /* reset the timer interval */
0358     data->fan_timer.expires = jiffies +
0359         msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
0360     add_timer(&data->fan_timer);
0361 }
0362 
0363 static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
0364                        u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
0365                        u8 flag_mode, u8 flag_clear)
0366 {
0367     u8  reg_int;
0368     u8  reg_mode;
0369     u16 fan_cap;
0370 
0371     if (cmp == NPCM7XX_FAN_CMPA)
0372         fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
0373     else
0374         fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
0375 
0376     /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
0377     iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
0378 
0379     if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
0380         /* First capture, drop it */
0381         data->fan_dev[fan_id].fan_st_flg =
0382             FAN_PREPARE_TO_GET_FIRST_CAPTURE;
0383 
0384         /* reset counter */
0385         data->fan_dev[fan_id].fan_cnt_tmp = 0;
0386     } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
0387         /*
0388          * collect the enough sample,
0389          * (ex: 2 pulse fan need to get 2 sample)
0390          */
0391         data->fan_dev[fan_id].fan_cnt_tmp +=
0392             (NPCM7XX_FAN_TCNT - fan_cap);
0393 
0394         data->fan_dev[fan_id].fan_st_flg++;
0395     } else {
0396         /* get enough sample or fan disable */
0397         if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
0398             data->fan_dev[fan_id].fan_cnt_tmp +=
0399                 (NPCM7XX_FAN_TCNT - fan_cap);
0400 
0401             /* compute finial average cnt per pulse */
0402             data->fan_dev[fan_id].fan_cnt =
0403                 data->fan_dev[fan_id].fan_cnt_tmp /
0404                 FAN_ENOUGH_SAMPLE;
0405 
0406             data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
0407         }
0408 
0409         reg_int =  ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0410 
0411         /* disable interrupt */
0412         iowrite8((reg_int & ~flag_int),
0413              NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0414         reg_mode =  ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
0415 
0416         /* stop capturing */
0417         iowrite8((reg_mode & ~flag_mode),
0418              NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
0419     }
0420 }
0421 
0422 static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
0423                      u8 fan, u8 cmp, u8 flag)
0424 {
0425     u8 reg_int;
0426     u8 reg_mode;
0427     u8 flag_timeout;
0428     u8 flag_cap;
0429     u8 flag_clear;
0430     u8 flag_int;
0431     u8 flag_mode;
0432     u8 fan_id;
0433 
0434     fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
0435 
0436     if (cmp == NPCM7XX_FAN_CMPA) {
0437         flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
0438         flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
0439         flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
0440         flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
0441         flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
0442     } else {
0443         flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
0444         flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
0445         flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
0446         flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
0447         flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
0448     }
0449 
0450     if (flag & flag_timeout) {
0451         reg_int =  ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0452 
0453         /* disable interrupt */
0454         iowrite8((reg_int & ~flag_int),
0455              NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
0456 
0457         /* clear interrupt flag */
0458         iowrite8(flag_clear,
0459              NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
0460 
0461         reg_mode =  ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
0462 
0463         /* stop capturing */
0464         iowrite8((reg_mode & ~flag_mode),
0465              NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
0466 
0467         /*
0468          *  If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
0469          *  connect or speed is lower than 10.6Hz (320RPM/pulse2).
0470          *  In these situation, the RPM output should be zero.
0471          */
0472         data->fan_dev[fan_id].fan_cnt = 0;
0473     } else {
0474         /* input capture is occurred */
0475         if (flag & flag_cap)
0476             npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
0477                         flag_mode, flag_clear);
0478     }
0479 }
0480 
0481 static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
0482 {
0483     struct npcm7xx_pwm_fan_data *data = dev_id;
0484     unsigned long flags;
0485     int module;
0486     u8 flag;
0487 
0488     module = irq - data->fan_irq[0];
0489     spin_lock_irqsave(&data->fan_lock[module], flags);
0490 
0491     flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
0492     if (flag > 0) {
0493         npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
0494         npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
0495         spin_unlock_irqrestore(&data->fan_lock[module], flags);
0496         return IRQ_HANDLED;
0497     }
0498 
0499     spin_unlock_irqrestore(&data->fan_lock[module], flags);
0500 
0501     return IRQ_NONE;
0502 }
0503 
0504 static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
0505                 long *val)
0506 {
0507     struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
0508     u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
0509     u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
0510 
0511     switch (attr) {
0512     case hwmon_pwm_input:
0513         *val = ioread32
0514             (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
0515         return 0;
0516     default:
0517         return -EOPNOTSUPP;
0518     }
0519 }
0520 
0521 static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
0522                  long val)
0523 {
0524     struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
0525     int err;
0526 
0527     switch (attr) {
0528     case hwmon_pwm_input:
0529         if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
0530             return -EINVAL;
0531         err = npcm7xx_pwm_config_set(data, channel, (u16)val);
0532         break;
0533     default:
0534         err = -EOPNOTSUPP;
0535         break;
0536     }
0537 
0538     return err;
0539 }
0540 
0541 static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
0542 {
0543     const struct npcm7xx_pwm_fan_data *data = _data;
0544 
0545     if (!data->pwm_present[channel])
0546         return 0;
0547 
0548     switch (attr) {
0549     case hwmon_pwm_input:
0550         return 0644;
0551     default:
0552         return 0;
0553     }
0554 }
0555 
0556 static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
0557                 long *val)
0558 {
0559     struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
0560 
0561     switch (attr) {
0562     case hwmon_fan_input:
0563         *val = 0;
0564         if (data->fan_dev[channel].fan_cnt <= 0)
0565             return data->fan_dev[channel].fan_cnt;
0566 
0567         /* Convert the raw reading to RPM */
0568         if (data->fan_dev[channel].fan_cnt > 0 &&
0569             data->fan_dev[channel].fan_pls_per_rev > 0)
0570             *val = ((data->input_clk_freq * 60) /
0571                 (data->fan_dev[channel].fan_cnt *
0572                  data->fan_dev[channel].fan_pls_per_rev));
0573         return 0;
0574     default:
0575         return -EOPNOTSUPP;
0576     }
0577 }
0578 
0579 static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
0580 {
0581     const struct npcm7xx_pwm_fan_data *data = _data;
0582 
0583     if (!data->fan_present[channel])
0584         return 0;
0585 
0586     switch (attr) {
0587     case hwmon_fan_input:
0588         return 0444;
0589     default:
0590         return 0;
0591     }
0592 }
0593 
0594 static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
0595             u32 attr, int channel, long *val)
0596 {
0597     switch (type) {
0598     case hwmon_pwm:
0599         return npcm7xx_read_pwm(dev, attr, channel, val);
0600     case hwmon_fan:
0601         return npcm7xx_read_fan(dev, attr, channel, val);
0602     default:
0603         return -EOPNOTSUPP;
0604     }
0605 }
0606 
0607 static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
0608              u32 attr, int channel, long val)
0609 {
0610     switch (type) {
0611     case hwmon_pwm:
0612         return npcm7xx_write_pwm(dev, attr, channel, val);
0613     default:
0614         return -EOPNOTSUPP;
0615     }
0616 }
0617 
0618 static umode_t npcm7xx_is_visible(const void *data,
0619                   enum hwmon_sensor_types type,
0620                   u32 attr, int channel)
0621 {
0622     switch (type) {
0623     case hwmon_pwm:
0624         return npcm7xx_pwm_is_visible(data, attr, channel);
0625     case hwmon_fan:
0626         return npcm7xx_fan_is_visible(data, attr, channel);
0627     default:
0628         return 0;
0629     }
0630 }
0631 
0632 static const struct hwmon_channel_info *npcm7xx_info[] = {
0633     HWMON_CHANNEL_INFO(pwm,
0634                HWMON_PWM_INPUT,
0635                HWMON_PWM_INPUT,
0636                HWMON_PWM_INPUT,
0637                HWMON_PWM_INPUT,
0638                HWMON_PWM_INPUT,
0639                HWMON_PWM_INPUT,
0640                HWMON_PWM_INPUT,
0641                HWMON_PWM_INPUT),
0642     HWMON_CHANNEL_INFO(fan,
0643                HWMON_F_INPUT,
0644                HWMON_F_INPUT,
0645                HWMON_F_INPUT,
0646                HWMON_F_INPUT,
0647                HWMON_F_INPUT,
0648                HWMON_F_INPUT,
0649                HWMON_F_INPUT,
0650                HWMON_F_INPUT,
0651                HWMON_F_INPUT,
0652                HWMON_F_INPUT,
0653                HWMON_F_INPUT,
0654                HWMON_F_INPUT,
0655                HWMON_F_INPUT,
0656                HWMON_F_INPUT,
0657                HWMON_F_INPUT,
0658                HWMON_F_INPUT),
0659     NULL
0660 };
0661 
0662 static const struct hwmon_ops npcm7xx_hwmon_ops = {
0663     .is_visible = npcm7xx_is_visible,
0664     .read = npcm7xx_read,
0665     .write = npcm7xx_write,
0666 };
0667 
0668 static const struct hwmon_chip_info npcm7xx_chip_info = {
0669     .ops = &npcm7xx_hwmon_ops,
0670     .info = npcm7xx_info,
0671 };
0672 
0673 static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
0674 {
0675     int m, ch;
0676     u32 prescale_val, output_freq;
0677 
0678     data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
0679 
0680     /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
0681     output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
0682     prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
0683 
0684     /* If prescale_val = 0, then the prescale output clock is stopped */
0685     if (prescale_val < MIN_PRESCALE1)
0686         prescale_val = MIN_PRESCALE1;
0687     /*
0688      * prescale_val need to decrement in one because in the PWM Prescale
0689      * register the Prescale value increment by one
0690      */
0691     prescale_val--;
0692 
0693     /* Setting PWM Prescale Register value register to both modules */
0694     prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
0695 
0696     for (m = 0; m < NPCM7XX_PWM_MAX_MODULES  ; m++) {
0697         iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
0698         iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
0699               NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
0700         iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
0701               NPCM7XX_PWM_REG_CR(data->pwm_base, m));
0702 
0703         for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
0704             iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
0705                   NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
0706         }
0707     }
0708 
0709     return output_freq / ((prescale_val & 0xf) + 1);
0710 }
0711 
0712 static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
0713 {
0714     int md;
0715     int ch;
0716     int i;
0717     u32 apb_clk_freq;
0718 
0719     for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
0720         /* stop FAN0~7 clock */
0721         iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
0722              NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
0723 
0724         /* disable all interrupt */
0725         iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
0726 
0727         /* clear all interrupt */
0728         iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
0729              NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
0730 
0731         /* set FAN0~7 clock prescaler */
0732         iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
0733              NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
0734 
0735         /* set FAN0~7 mode (high-to-low transition) */
0736         iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
0737               NPCM7XX_FAN_TMCTRL_TAEN),
0738              NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
0739 
0740         /* set FAN0~7 Initial Count/Cap */
0741         iowrite16(NPCM7XX_FAN_TCNT,
0742               NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
0743         iowrite16(NPCM7XX_FAN_TCNT,
0744               NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
0745 
0746         /* set FAN0~7 compare (equal to count) */
0747         iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
0748              NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
0749 
0750         /* set FAN0~7 compare value */
0751         iowrite16(NPCM7XX_FAN_TCPA,
0752               NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
0753         iowrite16(NPCM7XX_FAN_TCPB,
0754               NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
0755 
0756         /* set FAN0~7 fan input FANIN 0~15 */
0757         iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
0758              NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
0759         iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
0760              NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
0761 
0762         for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
0763             ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
0764             data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
0765             data->fan_dev[ch].fan_pls_per_rev =
0766                 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
0767             data->fan_dev[ch].fan_cnt = 0;
0768         }
0769     }
0770 
0771     apb_clk_freq = clk_get_rate(data->fan_clk);
0772 
0773     /* Fan tach input clock = APB clock / prescalar, default is 255. */
0774     data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
0775 }
0776 
0777 static int
0778 npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
0779                  unsigned long *state)
0780 {
0781     struct npcm7xx_cooling_device *cdev = tcdev->devdata;
0782 
0783     *state = cdev->max_state;
0784 
0785     return 0;
0786 }
0787 
0788 static int
0789 npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
0790                  unsigned long *state)
0791 {
0792     struct npcm7xx_cooling_device *cdev = tcdev->devdata;
0793 
0794     *state = cdev->cur_state;
0795 
0796     return 0;
0797 }
0798 
0799 static int
0800 npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
0801                  unsigned long state)
0802 {
0803     struct npcm7xx_cooling_device *cdev = tcdev->devdata;
0804     int ret;
0805 
0806     if (state > cdev->max_state)
0807         return -EINVAL;
0808 
0809     cdev->cur_state = state;
0810     ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
0811                      cdev->cooling_levels[cdev->cur_state]);
0812 
0813     return ret;
0814 }
0815 
0816 static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
0817     .get_max_state = npcm7xx_pwm_cz_get_max_state,
0818     .get_cur_state = npcm7xx_pwm_cz_get_cur_state,
0819     .set_cur_state = npcm7xx_pwm_cz_set_cur_state,
0820 };
0821 
0822 static int npcm7xx_create_pwm_cooling(struct device *dev,
0823                       struct device_node *child,
0824                       struct npcm7xx_pwm_fan_data *data,
0825                       u32 pwm_port, u8 num_levels)
0826 {
0827     int ret;
0828     struct npcm7xx_cooling_device *cdev;
0829 
0830     cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
0831     if (!cdev)
0832         return -ENOMEM;
0833 
0834     cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
0835     if (!cdev->cooling_levels)
0836         return -ENOMEM;
0837 
0838     cdev->max_state = num_levels - 1;
0839     ret = of_property_read_u8_array(child, "cooling-levels",
0840                     cdev->cooling_levels,
0841                     num_levels);
0842     if (ret) {
0843         dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
0844         return ret;
0845     }
0846     snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
0847          pwm_port);
0848 
0849     cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
0850                 cdev->name, cdev, &npcm7xx_pwm_cool_ops);
0851     if (IS_ERR(cdev->tcdev))
0852         return PTR_ERR(cdev->tcdev);
0853 
0854     cdev->data = data;
0855     cdev->pwm_port = pwm_port;
0856 
0857     data->cdev[pwm_port] = cdev;
0858 
0859     return 0;
0860 }
0861 
0862 static int npcm7xx_en_pwm_fan(struct device *dev,
0863                   struct device_node *child,
0864                   struct npcm7xx_pwm_fan_data *data)
0865 {
0866     u8 *fan_ch;
0867     u32 pwm_port;
0868     int ret, fan_cnt;
0869     u8 index, ch;
0870 
0871     ret = of_property_read_u32(child, "reg", &pwm_port);
0872     if (ret)
0873         return ret;
0874 
0875     data->pwm_present[pwm_port] = true;
0876     ret = npcm7xx_pwm_config_set(data, pwm_port,
0877                      NPCM7XX_PWM_CMR_DEFAULT_NUM);
0878 
0879     ret = of_property_count_u8_elems(child, "cooling-levels");
0880     if (ret > 0) {
0881         ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
0882                          ret);
0883         if (ret)
0884             return ret;
0885     }
0886 
0887     fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
0888     if (fan_cnt < 1)
0889         return -EINVAL;
0890 
0891     fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
0892     if (!fan_ch)
0893         return -ENOMEM;
0894 
0895     ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
0896     if (ret)
0897         return ret;
0898 
0899     for (ch = 0; ch < fan_cnt; ch++) {
0900         index = fan_ch[ch];
0901         data->fan_present[index] = true;
0902         data->fan_dev[index].fan_st_flg = FAN_INIT;
0903     }
0904 
0905     return 0;
0906 }
0907 
0908 static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
0909 {
0910     struct device *dev = &pdev->dev;
0911     struct device_node *np, *child;
0912     struct npcm7xx_pwm_fan_data *data;
0913     struct resource *res;
0914     struct device *hwmon;
0915     char name[20];
0916     int ret, cnt;
0917     u32 output_freq;
0918     u32 i;
0919 
0920     np = dev->of_node;
0921 
0922     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0923     if (!data)
0924         return -ENOMEM;
0925 
0926     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
0927     if (!res) {
0928         dev_err(dev, "pwm resource not found\n");
0929         return -ENODEV;
0930     }
0931 
0932     data->pwm_base = devm_ioremap_resource(dev, res);
0933     dev_dbg(dev, "pwm base resource is %pR\n", res);
0934     if (IS_ERR(data->pwm_base))
0935         return PTR_ERR(data->pwm_base);
0936 
0937     data->pwm_clk = devm_clk_get(dev, "pwm");
0938     if (IS_ERR(data->pwm_clk)) {
0939         dev_err(dev, "couldn't get pwm clock\n");
0940         return PTR_ERR(data->pwm_clk);
0941     }
0942 
0943     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
0944     if (!res) {
0945         dev_err(dev, "fan resource not found\n");
0946         return -ENODEV;
0947     }
0948 
0949     data->fan_base = devm_ioremap_resource(dev, res);
0950     dev_dbg(dev, "fan base resource is %pR\n", res);
0951     if (IS_ERR(data->fan_base))
0952         return PTR_ERR(data->fan_base);
0953 
0954     data->fan_clk = devm_clk_get(dev, "fan");
0955     if (IS_ERR(data->fan_clk)) {
0956         dev_err(dev, "couldn't get fan clock\n");
0957         return PTR_ERR(data->fan_clk);
0958     }
0959 
0960     output_freq = npcm7xx_pwm_init(data);
0961     npcm7xx_fan_init(data);
0962 
0963     for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES  ; cnt++)
0964         mutex_init(&data->pwm_lock[cnt]);
0965 
0966     for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
0967         spin_lock_init(&data->fan_lock[i]);
0968 
0969         data->fan_irq[i] = platform_get_irq(pdev, i);
0970         if (data->fan_irq[i] < 0)
0971             return data->fan_irq[i];
0972 
0973         sprintf(name, "NPCM7XX-FAN-MD%d", i);
0974         ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
0975                        0, name, (void *)data);
0976         if (ret) {
0977             dev_err(dev, "register IRQ fan%d failed\n", i);
0978             return ret;
0979         }
0980     }
0981 
0982     for_each_child_of_node(np, child) {
0983         ret = npcm7xx_en_pwm_fan(dev, child, data);
0984         if (ret) {
0985             dev_err(dev, "enable pwm and fan failed\n");
0986             of_node_put(child);
0987             return ret;
0988         }
0989     }
0990 
0991     hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
0992                              data, &npcm7xx_chip_info,
0993                              NULL);
0994     if (IS_ERR(hwmon)) {
0995         dev_err(dev, "unable to register hwmon device\n");
0996         return PTR_ERR(hwmon);
0997     }
0998 
0999     for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
1000         if (data->fan_present[i]) {
1001             /* fan timer initialization */
1002             data->fan_timer.expires = jiffies +
1003                 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
1004             timer_setup(&data->fan_timer,
1005                     npcm7xx_fan_polling, 0);
1006             add_timer(&data->fan_timer);
1007             break;
1008         }
1009     }
1010 
1011     pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
1012         output_freq, data->input_clk_freq);
1013 
1014     return 0;
1015 }
1016 
1017 static const struct of_device_id of_pwm_fan_match_table[] = {
1018     { .compatible = "nuvoton,npcm750-pwm-fan", },
1019     {},
1020 };
1021 MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
1022 
1023 static struct platform_driver npcm7xx_pwm_fan_driver = {
1024     .probe      = npcm7xx_pwm_fan_probe,
1025     .driver     = {
1026         .name   = "npcm7xx_pwm_fan",
1027         .of_match_table = of_pwm_fan_match_table,
1028     },
1029 };
1030 
1031 module_platform_driver(npcm7xx_pwm_fan_driver);
1032 
1033 MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
1034 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
1035 MODULE_LICENSE("GPL v2");
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