Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * nct7904.c - driver for Nuvoton NCT7904D.
0004  *
0005  * Copyright (c) 2015 Kontron
0006  * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
0007  *
0008  * Copyright (c) 2019 Advantech
0009  * Author: Amy.Shih <amy.shih@advantech.com.tw>
0010  *
0011  * Copyright (c) 2020 Advantech
0012  * Author: Yuechao Zhao <yuechao.zhao@advantech.com.cn>
0013  *
0014  * Supports the following chips:
0015  *
0016  * Chip        #vin  #fan  #pwm  #temp  #dts  chip ID
0017  * nct7904d     20    12    4     5      8    0xc5
0018  */
0019 
0020 #include <linux/module.h>
0021 #include <linux/device.h>
0022 #include <linux/init.h>
0023 #include <linux/i2c.h>
0024 #include <linux/mutex.h>
0025 #include <linux/hwmon.h>
0026 #include <linux/watchdog.h>
0027 
0028 #define VENDOR_ID_REG       0x7A    /* Any bank */
0029 #define NUVOTON_ID      0x50
0030 #define CHIP_ID_REG     0x7B    /* Any bank */
0031 #define NCT7904_ID      0xC5
0032 #define DEVICE_ID_REG       0x7C    /* Any bank */
0033 
0034 #define BANK_SEL_REG        0xFF
0035 #define BANK_0          0x00
0036 #define BANK_1          0x01
0037 #define BANK_2          0x02
0038 #define BANK_3          0x03
0039 #define BANK_4          0x04
0040 #define BANK_MAX        0x04
0041 
0042 #define FANIN_MAX       12  /* Counted from 1 */
0043 #define VSEN_MAX        21  /* VSEN1..14, 3VDD, VBAT, V3VSB,
0044                        LTD (not a voltage), VSEN17..19 */
0045 #define FANCTL_MAX      4   /* Counted from 1 */
0046 #define TCPU_MAX        8   /* Counted from 1 */
0047 #define TEMP_MAX        4   /* Counted from 1 */
0048 #define SMI_STS_MAX     10  /* Counted from 1 */
0049 
0050 #define VT_ADC_CTRL0_REG    0x20    /* Bank 0 */
0051 #define VT_ADC_CTRL1_REG    0x21    /* Bank 0 */
0052 #define VT_ADC_CTRL2_REG    0x22    /* Bank 0 */
0053 #define FANIN_CTRL0_REG     0x24
0054 #define FANIN_CTRL1_REG     0x25
0055 #define DTS_T_CTRL0_REG     0x26
0056 #define DTS_T_CTRL1_REG     0x27
0057 #define VT_ADC_MD_REG       0x2E
0058 
0059 #define VSEN1_HV_LL_REG     0x02    /* Bank 1; 2 regs (HV/LV) per sensor */
0060 #define VSEN1_LV_LL_REG     0x03    /* Bank 1; 2 regs (HV/LV) per sensor */
0061 #define VSEN1_HV_HL_REG     0x00    /* Bank 1; 2 regs (HV/LV) per sensor */
0062 #define VSEN1_LV_HL_REG     0x01    /* Bank 1; 2 regs (HV/LV) per sensor */
0063 #define SMI_STS1_REG        0xC1    /* Bank 0; SMI Status Register */
0064 #define SMI_STS3_REG        0xC3    /* Bank 0; SMI Status Register */
0065 #define SMI_STS5_REG        0xC5    /* Bank 0; SMI Status Register */
0066 #define SMI_STS7_REG        0xC7    /* Bank 0; SMI Status Register */
0067 #define SMI_STS8_REG        0xC8    /* Bank 0; SMI Status Register */
0068 
0069 #define VSEN1_HV_REG        0x40    /* Bank 0; 2 regs (HV/LV) per sensor */
0070 #define TEMP_CH1_HV_REG     0x42    /* Bank 0; same as VSEN2_HV */
0071 #define LTD_HV_REG      0x62    /* Bank 0; 2 regs in VSEN range */
0072 #define LTD_HV_HL_REG       0x44    /* Bank 1; 1 reg for LTD */
0073 #define LTD_LV_HL_REG       0x45    /* Bank 1; 1 reg for LTD */
0074 #define LTD_HV_LL_REG       0x46    /* Bank 1; 1 reg for LTD */
0075 #define LTD_LV_LL_REG       0x47    /* Bank 1; 1 reg for LTD */
0076 #define TEMP_CH1_CH_REG     0x05    /* Bank 1; 1 reg for LTD */
0077 #define TEMP_CH1_W_REG      0x06    /* Bank 1; 1 reg for LTD */
0078 #define TEMP_CH1_WH_REG     0x07    /* Bank 1; 1 reg for LTD */
0079 #define TEMP_CH1_C_REG      0x04    /* Bank 1; 1 reg per sensor */
0080 #define DTS_T_CPU1_C_REG    0x90    /* Bank 1; 1 reg per sensor */
0081 #define DTS_T_CPU1_CH_REG   0x91    /* Bank 1; 1 reg per sensor */
0082 #define DTS_T_CPU1_W_REG    0x92    /* Bank 1; 1 reg per sensor */
0083 #define DTS_T_CPU1_WH_REG   0x93    /* Bank 1; 1 reg per sensor */
0084 #define FANIN1_HV_REG       0x80    /* Bank 0; 2 regs (HV/LV) per sensor */
0085 #define FANIN1_HV_HL_REG    0x60    /* Bank 1; 2 regs (HV/LV) per sensor */
0086 #define FANIN1_LV_HL_REG    0x61    /* Bank 1; 2 regs (HV/LV) per sensor */
0087 #define T_CPU1_HV_REG       0xA0    /* Bank 0; 2 regs (HV/LV) per sensor */
0088 
0089 #define PRTS_REG        0x03    /* Bank 2 */
0090 #define PFE_REG         0x00    /* Bank 2; PECI Function Enable */
0091 #define TSI_CTRL_REG        0x50    /* Bank 2; TSI Control Register */
0092 #define FANCTL1_FMR_REG     0x00    /* Bank 3; 1 reg per channel */
0093 #define FANCTL1_OUT_REG     0x10    /* Bank 3; 1 reg per channel */
0094 
0095 #define WDT_LOCK_REG        0xE0    /* W/O Lock Watchdog Register */
0096 #define WDT_EN_REG      0xE1    /* R/O Watchdog Enable Register */
0097 #define WDT_STS_REG     0xE2    /* R/O Watchdog Status Register */
0098 #define WDT_TIMER_REG       0xE3    /* R/W Watchdog Timer Register */
0099 #define WDT_SOFT_EN     0x55    /* Enable soft watchdog timer */
0100 #define WDT_SOFT_DIS        0xAA    /* Disable soft watchdog timer */
0101 
0102 #define VOLT_MONITOR_MODE   0x0
0103 #define THERMAL_DIODE_MODE  0x1
0104 #define THERMISTOR_MODE     0x3
0105 
0106 #define ENABLE_TSI  BIT(1)
0107 
0108 #define WATCHDOG_TIMEOUT    1   /* 1 minute default timeout */
0109 
0110 /*The timeout range is 1-255 minutes*/
0111 #define MIN_TIMEOUT     (1 * 60)
0112 #define MAX_TIMEOUT     (255 * 60)
0113 
0114 static int timeout;
0115 module_param(timeout, int, 0);
0116 MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes. 1 <= timeout <= 255, default="
0117             __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
0118 
0119 static bool nowayout = WATCHDOG_NOWAYOUT;
0120 module_param(nowayout, bool, 0);
0121 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0122             __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0123 
0124 static const unsigned short normal_i2c[] = {
0125     0x2d, 0x2e, I2C_CLIENT_END
0126 };
0127 
0128 struct nct7904_data {
0129     struct i2c_client *client;
0130     struct watchdog_device wdt;
0131     struct mutex bank_lock;
0132     int bank_sel;
0133     u32 fanin_mask;
0134     u32 vsen_mask;
0135     u32 tcpu_mask;
0136     u8 fan_mode[FANCTL_MAX];
0137     u8 enable_dts;
0138     u8 has_dts;
0139     u8 temp_mode; /* 0: TR mode, 1: TD mode */
0140     u8 fan_alarm[2];
0141     u8 vsen_alarm[3];
0142 };
0143 
0144 /* Access functions */
0145 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
0146 {
0147     int ret;
0148 
0149     mutex_lock(&data->bank_lock);
0150     if (data->bank_sel == bank)
0151         return 0;
0152     ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
0153     if (ret == 0)
0154         data->bank_sel = bank;
0155     else
0156         data->bank_sel = -1;
0157     return ret;
0158 }
0159 
0160 static inline void nct7904_bank_release(struct nct7904_data *data)
0161 {
0162     mutex_unlock(&data->bank_lock);
0163 }
0164 
0165 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
0166 static int nct7904_read_reg(struct nct7904_data *data,
0167                 unsigned int bank, unsigned int reg)
0168 {
0169     struct i2c_client *client = data->client;
0170     int ret;
0171 
0172     ret = nct7904_bank_lock(data, bank);
0173     if (ret == 0)
0174         ret = i2c_smbus_read_byte_data(client, reg);
0175 
0176     nct7904_bank_release(data);
0177     return ret;
0178 }
0179 
0180 /*
0181  * Read 2-byte register. Returns register in big-endian format or
0182  * -ERRNO on error.
0183  */
0184 static int nct7904_read_reg16(struct nct7904_data *data,
0185                   unsigned int bank, unsigned int reg)
0186 {
0187     struct i2c_client *client = data->client;
0188     int ret, hi;
0189 
0190     ret = nct7904_bank_lock(data, bank);
0191     if (ret == 0) {
0192         ret = i2c_smbus_read_byte_data(client, reg);
0193         if (ret >= 0) {
0194             hi = ret;
0195             ret = i2c_smbus_read_byte_data(client, reg + 1);
0196             if (ret >= 0)
0197                 ret |= hi << 8;
0198         }
0199     }
0200 
0201     nct7904_bank_release(data);
0202     return ret;
0203 }
0204 
0205 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
0206 static int nct7904_write_reg(struct nct7904_data *data,
0207                  unsigned int bank, unsigned int reg, u8 val)
0208 {
0209     struct i2c_client *client = data->client;
0210     int ret;
0211 
0212     ret = nct7904_bank_lock(data, bank);
0213     if (ret == 0)
0214         ret = i2c_smbus_write_byte_data(client, reg, val);
0215 
0216     nct7904_bank_release(data);
0217     return ret;
0218 }
0219 
0220 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
0221                 long *val)
0222 {
0223     struct nct7904_data *data = dev_get_drvdata(dev);
0224     unsigned int cnt, rpm;
0225     int ret;
0226 
0227     switch (attr) {
0228     case hwmon_fan_input:
0229         ret = nct7904_read_reg16(data, BANK_0,
0230                      FANIN1_HV_REG + channel * 2);
0231         if (ret < 0)
0232             return ret;
0233         cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
0234         if (cnt == 0 || cnt == 0x1fff)
0235             rpm = 0;
0236         else
0237             rpm = 1350000 / cnt;
0238         *val = rpm;
0239         return 0;
0240     case hwmon_fan_min:
0241         ret = nct7904_read_reg16(data, BANK_1,
0242                      FANIN1_HV_HL_REG + channel * 2);
0243         if (ret < 0)
0244             return ret;
0245         cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
0246         if (cnt == 0 || cnt == 0x1fff)
0247             rpm = 0;
0248         else
0249             rpm = 1350000 / cnt;
0250         *val = rpm;
0251         return 0;
0252     case hwmon_fan_alarm:
0253         ret = nct7904_read_reg(data, BANK_0,
0254                        SMI_STS5_REG + (channel >> 3));
0255         if (ret < 0)
0256             return ret;
0257         if (!data->fan_alarm[channel >> 3])
0258             data->fan_alarm[channel >> 3] = ret & 0xff;
0259         else
0260             /* If there is new alarm showing up */
0261             data->fan_alarm[channel >> 3] |= (ret & 0xff);
0262         *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
0263         /* Needs to clean the alarm if alarm existing */
0264         if (*val)
0265             data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
0266         return 0;
0267     default:
0268         return -EOPNOTSUPP;
0269     }
0270 }
0271 
0272 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
0273 {
0274     const struct nct7904_data *data = _data;
0275 
0276     switch (attr) {
0277     case hwmon_fan_input:
0278     case hwmon_fan_alarm:
0279         if (data->fanin_mask & (1 << channel))
0280             return 0444;
0281         break;
0282     case hwmon_fan_min:
0283         if (data->fanin_mask & (1 << channel))
0284             return 0644;
0285         break;
0286     default:
0287         break;
0288     }
0289 
0290     return 0;
0291 }
0292 
0293 static u8 nct7904_chan_to_index[] = {
0294     0,  /* Not used */
0295     0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
0296     18, 19, 20, 16
0297 };
0298 
0299 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
0300                long *val)
0301 {
0302     struct nct7904_data *data = dev_get_drvdata(dev);
0303     int ret, volt, index;
0304 
0305     index = nct7904_chan_to_index[channel];
0306 
0307     switch (attr) {
0308     case hwmon_in_input:
0309         ret = nct7904_read_reg16(data, BANK_0,
0310                      VSEN1_HV_REG + index * 2);
0311         if (ret < 0)
0312             return ret;
0313         volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
0314         if (index < 14)
0315             volt *= 2; /* 0.002V scale */
0316         else
0317             volt *= 6; /* 0.006V scale */
0318         *val = volt;
0319         return 0;
0320     case hwmon_in_min:
0321         ret = nct7904_read_reg16(data, BANK_1,
0322                      VSEN1_HV_LL_REG + index * 4);
0323         if (ret < 0)
0324             return ret;
0325         volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
0326         if (index < 14)
0327             volt *= 2; /* 0.002V scale */
0328         else
0329             volt *= 6; /* 0.006V scale */
0330         *val = volt;
0331         return 0;
0332     case hwmon_in_max:
0333         ret = nct7904_read_reg16(data, BANK_1,
0334                      VSEN1_HV_HL_REG + index * 4);
0335         if (ret < 0)
0336             return ret;
0337         volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
0338         if (index < 14)
0339             volt *= 2; /* 0.002V scale */
0340         else
0341             volt *= 6; /* 0.006V scale */
0342         *val = volt;
0343         return 0;
0344     case hwmon_in_alarm:
0345         ret = nct7904_read_reg(data, BANK_0,
0346                        SMI_STS1_REG + (index >> 3));
0347         if (ret < 0)
0348             return ret;
0349         if (!data->vsen_alarm[index >> 3])
0350             data->vsen_alarm[index >> 3] = ret & 0xff;
0351         else
0352             /* If there is new alarm showing up */
0353             data->vsen_alarm[index >> 3] |= (ret & 0xff);
0354         *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
0355         /* Needs to clean the alarm if alarm existing */
0356         if (*val)
0357             data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
0358         return 0;
0359     default:
0360         return -EOPNOTSUPP;
0361     }
0362 }
0363 
0364 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
0365 {
0366     const struct nct7904_data *data = _data;
0367     int index = nct7904_chan_to_index[channel];
0368 
0369     switch (attr) {
0370     case hwmon_in_input:
0371     case hwmon_in_alarm:
0372         if (channel > 0 && (data->vsen_mask & BIT(index)))
0373             return 0444;
0374         break;
0375     case hwmon_in_min:
0376     case hwmon_in_max:
0377         if (channel > 0 && (data->vsen_mask & BIT(index)))
0378             return 0644;
0379         break;
0380     default:
0381         break;
0382     }
0383 
0384     return 0;
0385 }
0386 
0387 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
0388                  long *val)
0389 {
0390     struct nct7904_data *data = dev_get_drvdata(dev);
0391     int ret, temp;
0392     unsigned int reg1, reg2, reg3;
0393     s8 temps;
0394 
0395     switch (attr) {
0396     case hwmon_temp_input:
0397         if (channel == 4)
0398             ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
0399         else if (channel < 5)
0400             ret = nct7904_read_reg16(data, BANK_0,
0401                          TEMP_CH1_HV_REG + channel * 4);
0402         else
0403             ret = nct7904_read_reg16(data, BANK_0,
0404                          T_CPU1_HV_REG + (channel - 5)
0405                          * 2);
0406         if (ret < 0)
0407             return ret;
0408         temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
0409         *val = sign_extend32(temp, 10) * 125;
0410         return 0;
0411     case hwmon_temp_alarm:
0412         if (channel == 4) {
0413             ret = nct7904_read_reg(data, BANK_0,
0414                            SMI_STS3_REG);
0415             if (ret < 0)
0416                 return ret;
0417             *val = (ret >> 1) & 1;
0418         } else if (channel < 4) {
0419             ret = nct7904_read_reg(data, BANK_0,
0420                            SMI_STS1_REG);
0421             if (ret < 0)
0422                 return ret;
0423             *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
0424         } else {
0425             if ((channel - 5) < 4) {
0426                 ret = nct7904_read_reg(data, BANK_0,
0427                                SMI_STS7_REG +
0428                                ((channel - 5) >> 3));
0429                 if (ret < 0)
0430                     return ret;
0431                 *val = (ret >> ((channel - 5) & 0x07)) & 1;
0432             } else {
0433                 ret = nct7904_read_reg(data, BANK_0,
0434                                SMI_STS8_REG +
0435                                ((channel - 5) >> 3));
0436                 if (ret < 0)
0437                     return ret;
0438                 *val = (ret >> (((channel - 5) & 0x07) - 4))
0439                             & 1;
0440             }
0441         }
0442         return 0;
0443     case hwmon_temp_type:
0444         if (channel < 5) {
0445             if ((data->tcpu_mask >> channel) & 0x01) {
0446                 if ((data->temp_mode >> channel) & 0x01)
0447                     *val = 3; /* TD */
0448                 else
0449                     *val = 4; /* TR */
0450             } else {
0451                 *val = 0;
0452             }
0453         } else {
0454             if ((data->has_dts >> (channel - 5)) & 0x01) {
0455                 if (data->enable_dts & ENABLE_TSI)
0456                     *val = 5; /* TSI */
0457                 else
0458                     *val = 6; /* PECI */
0459             } else {
0460                 *val = 0;
0461             }
0462         }
0463         return 0;
0464     case hwmon_temp_max:
0465         reg1 = LTD_HV_LL_REG;
0466         reg2 = TEMP_CH1_W_REG;
0467         reg3 = DTS_T_CPU1_W_REG;
0468         break;
0469     case hwmon_temp_max_hyst:
0470         reg1 = LTD_LV_LL_REG;
0471         reg2 = TEMP_CH1_WH_REG;
0472         reg3 = DTS_T_CPU1_WH_REG;
0473         break;
0474     case hwmon_temp_crit:
0475         reg1 = LTD_HV_HL_REG;
0476         reg2 = TEMP_CH1_C_REG;
0477         reg3 = DTS_T_CPU1_C_REG;
0478         break;
0479     case hwmon_temp_crit_hyst:
0480         reg1 = LTD_LV_HL_REG;
0481         reg2 = TEMP_CH1_CH_REG;
0482         reg3 = DTS_T_CPU1_CH_REG;
0483         break;
0484     default:
0485         return -EOPNOTSUPP;
0486     }
0487 
0488     if (channel == 4)
0489         ret = nct7904_read_reg(data, BANK_1, reg1);
0490     else if (channel < 5)
0491         ret = nct7904_read_reg(data, BANK_1,
0492                        reg2 + channel * 8);
0493     else
0494         ret = nct7904_read_reg(data, BANK_1,
0495                        reg3 + (channel - 5) * 4);
0496 
0497     if (ret < 0)
0498         return ret;
0499     temps = ret;
0500     *val = temps * 1000;
0501     return 0;
0502 }
0503 
0504 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
0505 {
0506     const struct nct7904_data *data = _data;
0507 
0508     switch (attr) {
0509     case hwmon_temp_input:
0510     case hwmon_temp_alarm:
0511     case hwmon_temp_type:
0512         if (channel < 5) {
0513             if (data->tcpu_mask & BIT(channel))
0514                 return 0444;
0515         } else {
0516             if (data->has_dts & BIT(channel - 5))
0517                 return 0444;
0518         }
0519         break;
0520     case hwmon_temp_max:
0521     case hwmon_temp_max_hyst:
0522     case hwmon_temp_crit:
0523     case hwmon_temp_crit_hyst:
0524         if (channel < 5) {
0525             if (data->tcpu_mask & BIT(channel))
0526                 return 0644;
0527         } else {
0528             if (data->has_dts & BIT(channel - 5))
0529                 return 0644;
0530         }
0531         break;
0532     default:
0533         break;
0534     }
0535 
0536     return 0;
0537 }
0538 
0539 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
0540                 long *val)
0541 {
0542     struct nct7904_data *data = dev_get_drvdata(dev);
0543     int ret;
0544 
0545     switch (attr) {
0546     case hwmon_pwm_input:
0547         ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
0548         if (ret < 0)
0549             return ret;
0550         *val = ret;
0551         return 0;
0552     case hwmon_pwm_enable:
0553         ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
0554         if (ret < 0)
0555             return ret;
0556 
0557         *val = ret ? 2 : 1;
0558         return 0;
0559     default:
0560         return -EOPNOTSUPP;
0561     }
0562 }
0563 
0564 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
0565                   long val)
0566 {
0567     struct nct7904_data *data = dev_get_drvdata(dev);
0568     int ret;
0569     unsigned int reg1, reg2, reg3;
0570 
0571     val = clamp_val(val / 1000, -128, 127);
0572 
0573     switch (attr) {
0574     case hwmon_temp_max:
0575         reg1 = LTD_HV_LL_REG;
0576         reg2 = TEMP_CH1_W_REG;
0577         reg3 = DTS_T_CPU1_W_REG;
0578         break;
0579     case hwmon_temp_max_hyst:
0580         reg1 = LTD_LV_LL_REG;
0581         reg2 = TEMP_CH1_WH_REG;
0582         reg3 = DTS_T_CPU1_WH_REG;
0583         break;
0584     case hwmon_temp_crit:
0585         reg1 = LTD_HV_HL_REG;
0586         reg2 = TEMP_CH1_C_REG;
0587         reg3 = DTS_T_CPU1_C_REG;
0588         break;
0589     case hwmon_temp_crit_hyst:
0590         reg1 = LTD_LV_HL_REG;
0591         reg2 = TEMP_CH1_CH_REG;
0592         reg3 = DTS_T_CPU1_CH_REG;
0593         break;
0594     default:
0595         return -EOPNOTSUPP;
0596     }
0597     if (channel == 4)
0598         ret = nct7904_write_reg(data, BANK_1, reg1, val);
0599     else if (channel < 5)
0600         ret = nct7904_write_reg(data, BANK_1,
0601                     reg2 + channel * 8, val);
0602     else
0603         ret = nct7904_write_reg(data, BANK_1,
0604                     reg3 + (channel - 5) * 4, val);
0605 
0606     return ret;
0607 }
0608 
0609 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
0610                  long val)
0611 {
0612     struct nct7904_data *data = dev_get_drvdata(dev);
0613     int ret;
0614     u8 tmp;
0615 
0616     switch (attr) {
0617     case hwmon_fan_min:
0618         if (val <= 0)
0619             return -EINVAL;
0620 
0621         val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
0622         tmp = (val >> 5) & 0xff;
0623         ret = nct7904_write_reg(data, BANK_1,
0624                     FANIN1_HV_HL_REG + channel * 2, tmp);
0625         if (ret < 0)
0626             return ret;
0627         tmp = val & 0x1f;
0628         ret = nct7904_write_reg(data, BANK_1,
0629                     FANIN1_LV_HL_REG + channel * 2, tmp);
0630         return ret;
0631     default:
0632         return -EOPNOTSUPP;
0633     }
0634 }
0635 
0636 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
0637                 long val)
0638 {
0639     struct nct7904_data *data = dev_get_drvdata(dev);
0640     int ret, index, tmp;
0641 
0642     index = nct7904_chan_to_index[channel];
0643 
0644     if (index < 14)
0645         val = val / 2; /* 0.002V scale */
0646     else
0647         val = val / 6; /* 0.006V scale */
0648 
0649     val = clamp_val(val, 0, 0x7ff);
0650 
0651     switch (attr) {
0652     case hwmon_in_min:
0653         tmp = nct7904_read_reg(data, BANK_1,
0654                        VSEN1_LV_LL_REG + index * 4);
0655         if (tmp < 0)
0656             return tmp;
0657         tmp &= ~0x7;
0658         tmp |= val & 0x7;
0659         ret = nct7904_write_reg(data, BANK_1,
0660                     VSEN1_LV_LL_REG + index * 4, tmp);
0661         if (ret < 0)
0662             return ret;
0663         tmp = nct7904_read_reg(data, BANK_1,
0664                        VSEN1_HV_LL_REG + index * 4);
0665         if (tmp < 0)
0666             return tmp;
0667         tmp = (val >> 3) & 0xff;
0668         ret = nct7904_write_reg(data, BANK_1,
0669                     VSEN1_HV_LL_REG + index * 4, tmp);
0670         return ret;
0671     case hwmon_in_max:
0672         tmp = nct7904_read_reg(data, BANK_1,
0673                        VSEN1_LV_HL_REG + index * 4);
0674         if (tmp < 0)
0675             return tmp;
0676         tmp &= ~0x7;
0677         tmp |= val & 0x7;
0678         ret = nct7904_write_reg(data, BANK_1,
0679                     VSEN1_LV_HL_REG + index * 4, tmp);
0680         if (ret < 0)
0681             return ret;
0682         tmp = nct7904_read_reg(data, BANK_1,
0683                        VSEN1_HV_HL_REG + index * 4);
0684         if (tmp < 0)
0685             return tmp;
0686         tmp = (val >> 3) & 0xff;
0687         ret = nct7904_write_reg(data, BANK_1,
0688                     VSEN1_HV_HL_REG + index * 4, tmp);
0689         return ret;
0690     default:
0691         return -EOPNOTSUPP;
0692     }
0693 }
0694 
0695 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
0696                  long val)
0697 {
0698     struct nct7904_data *data = dev_get_drvdata(dev);
0699     int ret;
0700 
0701     switch (attr) {
0702     case hwmon_pwm_input:
0703         if (val < 0 || val > 255)
0704             return -EINVAL;
0705         ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
0706                     val);
0707         return ret;
0708     case hwmon_pwm_enable:
0709         if (val < 1 || val > 2 ||
0710             (val == 2 && !data->fan_mode[channel]))
0711             return -EINVAL;
0712         ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
0713                     val == 2 ? data->fan_mode[channel] : 0);
0714         return ret;
0715     default:
0716         return -EOPNOTSUPP;
0717     }
0718 }
0719 
0720 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
0721 {
0722     switch (attr) {
0723     case hwmon_pwm_input:
0724     case hwmon_pwm_enable:
0725         return 0644;
0726     default:
0727         return 0;
0728     }
0729 }
0730 
0731 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
0732             u32 attr, int channel, long *val)
0733 {
0734     switch (type) {
0735     case hwmon_in:
0736         return nct7904_read_in(dev, attr, channel, val);
0737     case hwmon_fan:
0738         return nct7904_read_fan(dev, attr, channel, val);
0739     case hwmon_pwm:
0740         return nct7904_read_pwm(dev, attr, channel, val);
0741     case hwmon_temp:
0742         return nct7904_read_temp(dev, attr, channel, val);
0743     default:
0744         return -EOPNOTSUPP;
0745     }
0746 }
0747 
0748 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
0749              u32 attr, int channel, long val)
0750 {
0751     switch (type) {
0752     case hwmon_in:
0753         return nct7904_write_in(dev, attr, channel, val);
0754     case hwmon_fan:
0755         return nct7904_write_fan(dev, attr, channel, val);
0756     case hwmon_pwm:
0757         return nct7904_write_pwm(dev, attr, channel, val);
0758     case hwmon_temp:
0759         return nct7904_write_temp(dev, attr, channel, val);
0760     default:
0761         return -EOPNOTSUPP;
0762     }
0763 }
0764 
0765 static umode_t nct7904_is_visible(const void *data,
0766                   enum hwmon_sensor_types type,
0767                   u32 attr, int channel)
0768 {
0769     switch (type) {
0770     case hwmon_in:
0771         return nct7904_in_is_visible(data, attr, channel);
0772     case hwmon_fan:
0773         return nct7904_fan_is_visible(data, attr, channel);
0774     case hwmon_pwm:
0775         return nct7904_pwm_is_visible(data, attr, channel);
0776     case hwmon_temp:
0777         return nct7904_temp_is_visible(data, attr, channel);
0778     default:
0779         return 0;
0780     }
0781 }
0782 
0783 /* Return 0 if detection is successful, -ENODEV otherwise */
0784 static int nct7904_detect(struct i2c_client *client,
0785               struct i2c_board_info *info)
0786 {
0787     struct i2c_adapter *adapter = client->adapter;
0788 
0789     if (!i2c_check_functionality(adapter,
0790                      I2C_FUNC_SMBUS_READ_BYTE |
0791                      I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
0792         return -ENODEV;
0793 
0794     /* Determine the chip type. */
0795     if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
0796         i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
0797         (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
0798         (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
0799         return -ENODEV;
0800 
0801     strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
0802 
0803     return 0;
0804 }
0805 
0806 static const struct hwmon_channel_info *nct7904_info[] = {
0807     HWMON_CHANNEL_INFO(in,
0808                /* dummy, skipped in is_visible */
0809                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0810                HWMON_I_ALARM,
0811                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0812                HWMON_I_ALARM,
0813                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0814                HWMON_I_ALARM,
0815                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0816                HWMON_I_ALARM,
0817                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0818                HWMON_I_ALARM,
0819                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0820                HWMON_I_ALARM,
0821                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0822                HWMON_I_ALARM,
0823                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0824                HWMON_I_ALARM,
0825                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0826                HWMON_I_ALARM,
0827                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0828                HWMON_I_ALARM,
0829                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0830                HWMON_I_ALARM,
0831                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0832                HWMON_I_ALARM,
0833                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0834                HWMON_I_ALARM,
0835                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0836                HWMON_I_ALARM,
0837                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0838                HWMON_I_ALARM,
0839                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0840                HWMON_I_ALARM,
0841                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0842                HWMON_I_ALARM,
0843                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0844                HWMON_I_ALARM,
0845                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0846                HWMON_I_ALARM,
0847                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0848                HWMON_I_ALARM,
0849                HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
0850                HWMON_I_ALARM),
0851     HWMON_CHANNEL_INFO(fan,
0852                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0853                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0854                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0855                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0856                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0857                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0858                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0859                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0860                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0861                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0862                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
0863                HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
0864     HWMON_CHANNEL_INFO(pwm,
0865                HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
0866                HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
0867                HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
0868                HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
0869     HWMON_CHANNEL_INFO(temp,
0870                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0871                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0872                HWMON_T_CRIT_HYST,
0873                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0874                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0875                HWMON_T_CRIT_HYST,
0876                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0877                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0878                HWMON_T_CRIT_HYST,
0879                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0880                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0881                HWMON_T_CRIT_HYST,
0882                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0883                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0884                HWMON_T_CRIT_HYST,
0885                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0886                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0887                HWMON_T_CRIT_HYST,
0888                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0889                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0890                HWMON_T_CRIT_HYST,
0891                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0892                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0893                HWMON_T_CRIT_HYST,
0894                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0895                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0896                HWMON_T_CRIT_HYST,
0897                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0898                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0899                HWMON_T_CRIT_HYST,
0900                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0901                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0902                HWMON_T_CRIT_HYST,
0903                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0904                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0905                HWMON_T_CRIT_HYST,
0906                HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
0907                HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
0908                HWMON_T_CRIT_HYST),
0909     NULL
0910 };
0911 
0912 static const struct hwmon_ops nct7904_hwmon_ops = {
0913     .is_visible = nct7904_is_visible,
0914     .read = nct7904_read,
0915     .write = nct7904_write,
0916 };
0917 
0918 static const struct hwmon_chip_info nct7904_chip_info = {
0919     .ops = &nct7904_hwmon_ops,
0920     .info = nct7904_info,
0921 };
0922 
0923 /*
0924  * Watchdog Function
0925  */
0926 static int nct7904_wdt_start(struct watchdog_device *wdt)
0927 {
0928     struct nct7904_data *data = watchdog_get_drvdata(wdt);
0929 
0930     /* Enable soft watchdog timer */
0931     return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
0932 }
0933 
0934 static int nct7904_wdt_stop(struct watchdog_device *wdt)
0935 {
0936     struct nct7904_data *data = watchdog_get_drvdata(wdt);
0937 
0938     return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
0939 }
0940 
0941 static int nct7904_wdt_set_timeout(struct watchdog_device *wdt,
0942                    unsigned int timeout)
0943 {
0944     struct nct7904_data *data = watchdog_get_drvdata(wdt);
0945     /*
0946      * The NCT7904 is very special in watchdog function.
0947      * Its minimum unit is minutes. And wdt->timeout needs
0948      * to match the actual timeout selected. So, this needs
0949      * to be: wdt->timeout = timeout / 60 * 60.
0950      * For example, if the user configures a timeout of
0951      * 119 seconds, the actual timeout will be 60 seconds.
0952      * So, wdt->timeout must then be set to 60 seconds.
0953      */
0954     wdt->timeout = timeout / 60 * 60;
0955 
0956     return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
0957                  wdt->timeout / 60);
0958 }
0959 
0960 static int nct7904_wdt_ping(struct watchdog_device *wdt)
0961 {
0962     /*
0963      * Note:
0964      * NCT7904 does not support refreshing WDT_TIMER_REG register when
0965      * the watchdog is active. Please disable watchdog before feeding
0966      * the watchdog and enable it again.
0967      */
0968     struct nct7904_data *data = watchdog_get_drvdata(wdt);
0969     int ret;
0970 
0971     /* Disable soft watchdog timer */
0972     ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
0973     if (ret < 0)
0974         return ret;
0975 
0976     /* feed watchdog */
0977     ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
0978     if (ret < 0)
0979         return ret;
0980 
0981     /* Enable soft watchdog timer */
0982     return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
0983 }
0984 
0985 static unsigned int nct7904_wdt_get_timeleft(struct watchdog_device *wdt)
0986 {
0987     struct nct7904_data *data = watchdog_get_drvdata(wdt);
0988     int ret;
0989 
0990     ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
0991     if (ret < 0)
0992         return 0;
0993 
0994     return ret * 60;
0995 }
0996 
0997 static const struct watchdog_info nct7904_wdt_info = {
0998     .options    = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
0999                 WDIOF_MAGICCLOSE,
1000     .identity   = "nct7904 watchdog",
1001 };
1002 
1003 static const struct watchdog_ops nct7904_wdt_ops = {
1004     .owner      = THIS_MODULE,
1005     .start      = nct7904_wdt_start,
1006     .stop       = nct7904_wdt_stop,
1007     .ping       = nct7904_wdt_ping,
1008     .set_timeout    = nct7904_wdt_set_timeout,
1009     .get_timeleft   = nct7904_wdt_get_timeleft,
1010 };
1011 
1012 static int nct7904_probe(struct i2c_client *client)
1013 {
1014     struct nct7904_data *data;
1015     struct device *hwmon_dev;
1016     struct device *dev = &client->dev;
1017     int ret, i;
1018     u32 mask;
1019     u8 val, bit;
1020 
1021     data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
1022     if (!data)
1023         return -ENOMEM;
1024 
1025     data->client = client;
1026     mutex_init(&data->bank_lock);
1027     data->bank_sel = -1;
1028 
1029     /* Setup sensor groups. */
1030     /* FANIN attributes */
1031     ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
1032     if (ret < 0)
1033         return ret;
1034     data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
1035 
1036     /*
1037      * VSEN attributes
1038      *
1039      * Note: voltage sensors overlap with external temperature
1040      * sensors. So, if we ever decide to support the latter
1041      * we will have to adjust 'vsen_mask' accordingly.
1042      */
1043     mask = 0;
1044     ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
1045     if (ret >= 0)
1046         mask = (ret >> 8) | ((ret & 0xff) << 8);
1047     ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1048     if (ret >= 0)
1049         mask |= (ret << 16);
1050     data->vsen_mask = mask;
1051 
1052     /* CPU_TEMP attributes */
1053     ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
1054     if (ret < 0)
1055         return ret;
1056 
1057     if ((ret & 0x6) == 0x6)
1058         data->tcpu_mask |= 1; /* TR1 */
1059     if ((ret & 0x18) == 0x18)
1060         data->tcpu_mask |= 2; /* TR2 */
1061     if ((ret & 0x20) == 0x20)
1062         data->tcpu_mask |= 4; /* TR3 */
1063     if ((ret & 0x80) == 0x80)
1064         data->tcpu_mask |= 8; /* TR4 */
1065 
1066     /* LTD */
1067     ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1068     if (ret < 0)
1069         return ret;
1070     if ((ret & 0x02) == 0x02)
1071         data->tcpu_mask |= 0x10;
1072 
1073     /* Multi-Function detecting for Volt and TR/TD */
1074     ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
1075     if (ret < 0)
1076         return ret;
1077 
1078     data->temp_mode = 0;
1079     for (i = 0; i < 4; i++) {
1080         val = (ret >> (i * 2)) & 0x03;
1081         bit = (1 << i);
1082         if (val == VOLT_MONITOR_MODE) {
1083             data->tcpu_mask &= ~bit;
1084         } else if (val == THERMAL_DIODE_MODE && i < 2) {
1085             data->temp_mode |= bit;
1086             data->vsen_mask &= ~(0x06 << (i * 2));
1087         } else if (val == THERMISTOR_MODE) {
1088             data->vsen_mask &= ~(0x02 << (i * 2));
1089         } else {
1090             /* Reserved */
1091             data->tcpu_mask &= ~bit;
1092             data->vsen_mask &= ~(0x06 << (i * 2));
1093         }
1094     }
1095 
1096     /* PECI */
1097     ret = nct7904_read_reg(data, BANK_2, PFE_REG);
1098     if (ret < 0)
1099         return ret;
1100     if (ret & 0x80) {
1101         data->enable_dts = 1; /* Enable DTS & PECI */
1102     } else {
1103         ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
1104         if (ret < 0)
1105             return ret;
1106         if (ret & 0x80)
1107             data->enable_dts = 0x3; /* Enable DTS & TSI */
1108     }
1109 
1110     /* Check DTS enable status */
1111     if (data->enable_dts) {
1112         ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
1113         if (ret < 0)
1114             return ret;
1115         data->has_dts = ret & 0xF;
1116         if (data->enable_dts & ENABLE_TSI) {
1117             ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
1118             if (ret < 0)
1119                 return ret;
1120             data->has_dts |= (ret & 0xF) << 4;
1121         }
1122     }
1123 
1124     for (i = 0; i < FANCTL_MAX; i++) {
1125         ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
1126         if (ret < 0)
1127             return ret;
1128         data->fan_mode[i] = ret;
1129     }
1130 
1131     /* Read all of SMI status register to clear alarms */
1132     for (i = 0; i < SMI_STS_MAX; i++) {
1133         ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);
1134         if (ret < 0)
1135             return ret;
1136     }
1137 
1138     hwmon_dev =
1139         devm_hwmon_device_register_with_info(dev, client->name, data,
1140                              &nct7904_chip_info, NULL);
1141     ret = PTR_ERR_OR_ZERO(hwmon_dev);
1142     if (ret)
1143         return ret;
1144 
1145     /* Watchdog initialization */
1146     data->wdt.ops = &nct7904_wdt_ops;
1147     data->wdt.info = &nct7904_wdt_info;
1148 
1149     data->wdt.timeout = WATCHDOG_TIMEOUT * 60; /* Set default timeout */
1150     data->wdt.min_timeout = MIN_TIMEOUT;
1151     data->wdt.max_timeout = MAX_TIMEOUT;
1152     data->wdt.parent = &client->dev;
1153 
1154     watchdog_init_timeout(&data->wdt, timeout * 60, &client->dev);
1155     watchdog_set_nowayout(&data->wdt, nowayout);
1156     watchdog_set_drvdata(&data->wdt, data);
1157 
1158     watchdog_stop_on_unregister(&data->wdt);
1159 
1160     return devm_watchdog_register_device(dev, &data->wdt);
1161 }
1162 
1163 static const struct i2c_device_id nct7904_id[] = {
1164     {"nct7904", 0},
1165     {}
1166 };
1167 MODULE_DEVICE_TABLE(i2c, nct7904_id);
1168 
1169 static struct i2c_driver nct7904_driver = {
1170     .class = I2C_CLASS_HWMON,
1171     .driver = {
1172         .name = "nct7904",
1173     },
1174     .probe_new = nct7904_probe,
1175     .id_table = nct7904_id,
1176     .detect = nct7904_detect,
1177     .address_list = normal_i2c,
1178 };
1179 
1180 module_i2c_driver(nct7904_driver);
1181 
1182 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1183 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1184 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!