drivers/hwmon/max6621.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Hardware monitoring driver for Maxim MAX6621
0004  *
0005  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
0006  * Copyright (c) 2017 Vadim Pasternak <vadimp@mellanox.com>
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/hwmon.h>
0011 #include <linux/hwmon-sysfs.h>
0012 #include <linux/i2c.h>
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/regmap.h>
0017
0018 #define MAX6621_DRV_NAME        "max6621"
0019 #define MAX6621_TEMP_INPUT_REG_NUM  9
0020 #define MAX6621_TEMP_INPUT_MIN      -127000
0021 #define MAX6621_TEMP_INPUT_MAX      128000
0022 #define MAX6621_TEMP_ALERT_CHAN_SHIFT   1
0023
0024 #define MAX6621_TEMP_S0D0_REG       0x00
0025 #define MAX6621_TEMP_S0D1_REG       0x01
0026 #define MAX6621_TEMP_S1D0_REG       0x02
0027 #define MAX6621_TEMP_S1D1_REG       0x03
0028 #define MAX6621_TEMP_S2D0_REG       0x04
0029 #define MAX6621_TEMP_S2D1_REG       0x05
0030 #define MAX6621_TEMP_S3D0_REG       0x06
0031 #define MAX6621_TEMP_S3D1_REG       0x07
0032 #define MAX6621_TEMP_MAX_REG        0x08
0033 #define MAX6621_TEMP_MAX_ADDR_REG   0x0a
0034 #define MAX6621_TEMP_ALERT_CAUSE_REG    0x0b
0035 #define MAX6621_CONFIG0_REG     0x0c
0036 #define MAX6621_CONFIG1_REG     0x0d
0037 #define MAX6621_CONFIG2_REG     0x0e
0038 #define MAX6621_CONFIG3_REG     0x0f
0039 #define MAX6621_TEMP_S0_ALERT_REG   0x10
0040 #define MAX6621_TEMP_S1_ALERT_REG   0x11
0041 #define MAX6621_TEMP_S2_ALERT_REG   0x12
0042 #define MAX6621_TEMP_S3_ALERT_REG   0x13
0043 #define MAX6621_CLEAR_ALERT_REG     0x15
0044 #define MAX6621_REG_MAX         (MAX6621_CLEAR_ALERT_REG + 1)
0045 #define MAX6621_REG_TEMP_SHIFT      0x06
0046
0047 #define MAX6621_ENABLE_TEMP_ALERTS_BIT  4
0048 #define MAX6621_ENABLE_I2C_CRC_BIT  5
0049 #define MAX6621_ENABLE_ALTERNATE_DATA   6
0050 #define MAX6621_ENABLE_LOCKUP_TO    7
0051 #define MAX6621_ENABLE_S0D0_BIT     8
0052 #define MAX6621_ENABLE_S3D1_BIT     15
0053 #define MAX6621_ENABLE_TEMP_ALL     GENMASK(MAX6621_ENABLE_S3D1_BIT, \
0054                         MAX6621_ENABLE_S0D0_BIT)
0055 #define MAX6621_POLL_DELAY_MASK     0x5
0056 #define MAX6621_CONFIG0_INIT        (MAX6621_ENABLE_TEMP_ALL | \
0057                      BIT(MAX6621_ENABLE_LOCKUP_TO) | \
0058                      BIT(MAX6621_ENABLE_I2C_CRC_BIT) | \
0059                      MAX6621_POLL_DELAY_MASK)
0060 #define MAX6621_PECI_BIT_TIME       0x2
0061 #define MAX6621_PECI_RETRY_NUM      0x3
0062 #define MAX6621_CONFIG1_INIT        ((MAX6621_PECI_BIT_TIME << 8) | \
0063                      MAX6621_PECI_RETRY_NUM)
0064
0065 /* Error codes */
0066 #define MAX6621_TRAN_FAILED 0x8100  /*
0067                      * PECI transaction failed for more
0068                      * than the configured number of
0069                      * consecutive retries.
0070                      */
0071 #define MAX6621_POOL_DIS    0x8101  /*
0072                      * Polling disabled for requested
0073                      * socket/domain.
0074                      */
0075 #define MAX6621_POOL_UNCOMPLETE 0x8102  /*
0076                      * First poll not yet completed for
0077                      * requested socket/domain (on
0078                      * startup).
0079                      */
0080 #define MAX6621_SD_DIS      0x8103  /*
0081                      * Read maximum temperature requested,
0082                      * but no sockets/domains enabled or
0083                      * all enabled sockets/domains have
0084                      * errors; or read maximum temperature
0085                      * address requested, but read maximum
0086                      * temperature was not called.
0087                      */
0088 #define MAX6621_ALERT_DIS   0x8104  /*
0089                      * Get alert socket/domain requested,
0090                      * but no alert active.
0091                      */
0092 #define MAX6621_PECI_ERR_MIN    0x8000  /* Intel spec PECI error min value. */
0093 #define MAX6621_PECI_ERR_MAX    0x80ff  /* Intel spec PECI error max value. */
0094
0095 static const u32 max6621_temp_regs[] = {
0096     MAX6621_TEMP_MAX_REG, MAX6621_TEMP_S0D0_REG, MAX6621_TEMP_S1D0_REG,
0097     MAX6621_TEMP_S2D0_REG, MAX6621_TEMP_S3D0_REG, MAX6621_TEMP_S0D1_REG,
0098     MAX6621_TEMP_S1D1_REG, MAX6621_TEMP_S2D1_REG, MAX6621_TEMP_S3D1_REG,
0099 };
0100
0101 static const char *const max6621_temp_labels[] = {
0102     "maximum",
0103     "socket0_0",
0104     "socket1_0",
0105     "socket2_0",
0106     "socket3_0",
0107     "socket0_1",
0108     "socket1_1",
0109     "socket2_1",
0110     "socket3_1",
0111 };
0112
0113 static const int max6621_temp_alert_chan2reg[] = {
0114     MAX6621_TEMP_S0_ALERT_REG,
0115     MAX6621_TEMP_S1_ALERT_REG,
0116     MAX6621_TEMP_S2_ALERT_REG,
0117     MAX6621_TEMP_S3_ALERT_REG,
0118 };
0119
0120 /**
0121  * struct max6621_data - private data:
0122  *
0123  * @client: I2C client;
0124  * @regmap: register map handle;
0125  * @input_chan2reg: mapping from channel to register;
0126  */
0127 struct max6621_data {
0128     struct i2c_client   *client;
0129     struct regmap       *regmap;
0130     int         input_chan2reg[MAX6621_TEMP_INPUT_REG_NUM + 1];
0131 };
0132
0133 static long max6621_temp_mc2reg(long val)
0134 {
0135     return (val / 1000L) << MAX6621_REG_TEMP_SHIFT;
0136 }
0137
0138 static umode_t
0139 max6621_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
0140            int channel)
0141 {
0142     /* Skip channels which are not physically conncted. */
0143     if (((struct max6621_data *)data)->input_chan2reg[channel] < 0)
0144         return 0;
0145
0146     switch (type) {
0147     case hwmon_temp:
0148         switch (attr) {
0149         case hwmon_temp_input:
0150         case hwmon_temp_label:
0151         case hwmon_temp_crit_alarm:
0152             return 0444;
0153         case hwmon_temp_offset:
0154         case hwmon_temp_crit:
0155             return 0644;
0156         default:
0157             break;
0158         }
0159         break;
0160     default:
0161         break;
0162     }
0163
0164     return 0;
0165 }
0166
0167 static int max6621_verify_reg_data(struct device *dev, int regval)
0168 {
0169     if (regval >= MAX6621_PECI_ERR_MIN &&
0170         regval <= MAX6621_PECI_ERR_MAX) {
0171         dev_dbg(dev, "PECI error code - err 0x%04x.\n",
0172             regval);
0173
0174         return -EIO;
0175     }
0176
0177     switch (regval) {
0178     case MAX6621_TRAN_FAILED:
0179         dev_dbg(dev, "PECI transaction failed - err 0x%04x.\n",
0180             regval);
0181         return -EIO;
0182     case MAX6621_POOL_DIS:
0183         dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval);
0184         return -EOPNOTSUPP;
0185     case MAX6621_POOL_UNCOMPLETE:
0186         dev_dbg(dev, "First poll not completed on startup - err 0x%04x.\n",
0187             regval);
0188         return -EIO;
0189     case MAX6621_SD_DIS:
0190         dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval);
0191         return -EOPNOTSUPP;
0192     case MAX6621_ALERT_DIS:
0193         dev_dbg(dev, "No alert active - err 0x%04x.\n", regval);
0194         return -EOPNOTSUPP;
0195     default:
0196         return 0;
0197     }
0198 }
0199
0200 static int
0201 max6621_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
0202          int channel, long *val)
0203 {
0204     struct max6621_data *data = dev_get_drvdata(dev);
0205     u32 regval;
0206     int reg;
0207     s8 temp;
0208     int ret;
0209
0210     switch (type) {
0211     case hwmon_temp:
0212         switch (attr) {
0213         case hwmon_temp_input:
0214             reg = data->input_chan2reg[channel];
0215             ret = regmap_read(data->regmap, reg, &regval);
0216             if (ret)
0217                 return ret;
0218
0219             ret = max6621_verify_reg_data(dev, regval);
0220             if (ret)
0221                 return ret;
0222
0223             /*
0224              * Bit MAX6621_REG_TEMP_SHIFT represents 1 degree step.
0225              * The temperature is given in two's complement and 8
0226              * bits is used for the register conversion.
0227              */
0228             temp = (regval >> MAX6621_REG_TEMP_SHIFT);
0229             *val = temp * 1000L;
0230
0231             break;
0232         case hwmon_temp_offset:
0233             ret = regmap_read(data->regmap, MAX6621_CONFIG2_REG,
0234                       &regval);
0235             if (ret)
0236                 return ret;
0237
0238             ret = max6621_verify_reg_data(dev, regval);
0239             if (ret)
0240                 return ret;
0241
0242             *val = (regval >> MAX6621_REG_TEMP_SHIFT) *
0243                    1000L;
0244
0245             break;
0246         case hwmon_temp_crit:
0247             channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
0248             reg = max6621_temp_alert_chan2reg[channel];
0249             ret = regmap_read(data->regmap, reg, &regval);
0250             if (ret)
0251                 return ret;
0252
0253             ret = max6621_verify_reg_data(dev, regval);
0254             if (ret)
0255                 return ret;
0256
0257             *val = regval * 1000L;
0258
0259             break;
0260         case hwmon_temp_crit_alarm:
0261             /*
0262              * Set val to zero to recover the case, when reading
0263              * MAX6621_TEMP_ALERT_CAUSE_REG results in for example
0264              * MAX6621_ALERT_DIS. Reading will return with error,
0265              * but in such case alarm should be returned as 0.
0266              */
0267             *val = 0;
0268             ret = regmap_read(data->regmap,
0269                       MAX6621_TEMP_ALERT_CAUSE_REG,
0270                       &regval);
0271             if (ret)
0272                 return ret;
0273
0274             ret = max6621_verify_reg_data(dev, regval);
0275             if (ret) {
0276                 /* Do not report error if alert is disabled. */
0277                 if (regval == MAX6621_ALERT_DIS)
0278                     return 0;
0279                 else
0280                     return ret;
0281             }
0282
0283             /*
0284              * Clear the alert automatically, using send-byte
0285              * smbus protocol for clearing alert.
0286              */
0287             if (regval) {
0288                 ret = i2c_smbus_write_byte(data->client,
0289                         MAX6621_CLEAR_ALERT_REG);
0290                 if (ret)
0291                     return ret;
0292             }
0293
0294             *val = !!regval;
0295
0296             break;
0297         default:
0298             return -EOPNOTSUPP;
0299         }
0300         break;
0301
0302     default:
0303         return -EOPNOTSUPP;
0304     }
0305
0306     return 0;
0307 }
0308
0309 static int
0310 max6621_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
0311           int channel, long val)
0312 {
0313     struct max6621_data *data = dev_get_drvdata(dev);
0314     u32 reg;
0315
0316     switch (type) {
0317     case hwmon_temp:
0318         switch (attr) {
0319         case hwmon_temp_offset:
0320             /* Clamp to allowed range to prevent overflow. */
0321             val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
0322                     MAX6621_TEMP_INPUT_MAX);
0323             val = max6621_temp_mc2reg(val);
0324
0325             return regmap_write(data->regmap,
0326                         MAX6621_CONFIG2_REG, val);
0327         case hwmon_temp_crit:
0328             channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
0329             reg = max6621_temp_alert_chan2reg[channel];
0330             /* Clamp to allowed range to prevent overflow. */
0331             val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
0332                     MAX6621_TEMP_INPUT_MAX);
0333             val = val / 1000L;
0334
0335             return regmap_write(data->regmap, reg, val);
0336         default:
0337             return -EOPNOTSUPP;
0338         }
0339         break;
0340
0341     default:
0342         return -EOPNOTSUPP;
0343     }
0344
0345     return -EOPNOTSUPP;
0346 }
0347
0348 static int
0349 max6621_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
0350             int channel, const char **str)
0351 {
0352     switch (type) {
0353     case hwmon_temp:
0354         switch (attr) {
0355         case hwmon_temp_label:
0356             *str = max6621_temp_labels[channel];
0357             return 0;
0358         default:
0359             return -EOPNOTSUPP;
0360         }
0361         break;
0362     default:
0363         return -EOPNOTSUPP;
0364     }
0365
0366     return -EOPNOTSUPP;
0367 }
0368
0369 static bool max6621_writeable_reg(struct device *dev, unsigned int reg)
0370 {
0371     switch (reg) {
0372     case MAX6621_CONFIG0_REG:
0373     case MAX6621_CONFIG1_REG:
0374     case MAX6621_CONFIG2_REG:
0375     case MAX6621_CONFIG3_REG:
0376     case MAX6621_TEMP_S0_ALERT_REG:
0377     case MAX6621_TEMP_S1_ALERT_REG:
0378     case MAX6621_TEMP_S2_ALERT_REG:
0379     case MAX6621_TEMP_S3_ALERT_REG:
0380     case MAX6621_TEMP_ALERT_CAUSE_REG:
0381         return true;
0382     }
0383     return false;
0384 }
0385
0386 static bool max6621_readable_reg(struct device *dev, unsigned int reg)
0387 {
0388     switch (reg) {
0389     case MAX6621_TEMP_S0D0_REG:
0390     case MAX6621_TEMP_S0D1_REG:
0391     case MAX6621_TEMP_S1D0_REG:
0392     case MAX6621_TEMP_S1D1_REG:
0393     case MAX6621_TEMP_S2D0_REG:
0394     case MAX6621_TEMP_S2D1_REG:
0395     case MAX6621_TEMP_S3D0_REG:
0396     case MAX6621_TEMP_S3D1_REG:
0397     case MAX6621_TEMP_MAX_REG:
0398     case MAX6621_TEMP_MAX_ADDR_REG:
0399     case MAX6621_CONFIG0_REG:
0400     case MAX6621_CONFIG1_REG:
0401     case MAX6621_CONFIG2_REG:
0402     case MAX6621_CONFIG3_REG:
0403     case MAX6621_TEMP_S0_ALERT_REG:
0404     case MAX6621_TEMP_S1_ALERT_REG:
0405     case MAX6621_TEMP_S2_ALERT_REG:
0406     case MAX6621_TEMP_S3_ALERT_REG:
0407         return true;
0408     }
0409     return false;
0410 }
0411
0412 static bool max6621_volatile_reg(struct device *dev, unsigned int reg)
0413 {
0414     switch (reg) {
0415     case MAX6621_TEMP_S0D0_REG:
0416     case MAX6621_TEMP_S0D1_REG:
0417     case MAX6621_TEMP_S1D0_REG:
0418     case MAX6621_TEMP_S1D1_REG:
0419     case MAX6621_TEMP_S2D0_REG:
0420     case MAX6621_TEMP_S2D1_REG:
0421     case MAX6621_TEMP_S3D0_REG:
0422     case MAX6621_TEMP_S3D1_REG:
0423     case MAX6621_TEMP_MAX_REG:
0424     case MAX6621_TEMP_S0_ALERT_REG:
0425     case MAX6621_TEMP_S1_ALERT_REG:
0426     case MAX6621_TEMP_S2_ALERT_REG:
0427     case MAX6621_TEMP_S3_ALERT_REG:
0428     case MAX6621_TEMP_ALERT_CAUSE_REG:
0429         return true;
0430     }
0431     return false;
0432 }
0433
0434 static const struct reg_default max6621_regmap_default[] = {
0435     { MAX6621_CONFIG0_REG, MAX6621_CONFIG0_INIT },
0436     { MAX6621_CONFIG1_REG, MAX6621_CONFIG1_INIT },
0437 };
0438
0439 static const struct regmap_config max6621_regmap_config = {
0440     .reg_bits = 8,
0441     .val_bits = 16,
0442     .max_register = MAX6621_REG_MAX,
0443     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0444     .cache_type = REGCACHE_FLAT,
0445     .writeable_reg = max6621_writeable_reg,
0446     .readable_reg = max6621_readable_reg,
0447     .volatile_reg = max6621_volatile_reg,
0448     .reg_defaults = max6621_regmap_default,
0449     .num_reg_defaults = ARRAY_SIZE(max6621_regmap_default),
0450 };
0451
0452 static const struct hwmon_channel_info *max6621_info[] = {
0453     HWMON_CHANNEL_INFO(chip,
0454                HWMON_C_REGISTER_TZ),
0455     HWMON_CHANNEL_INFO(temp,
0456                HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_OFFSET,
0457                HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
0458                HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
0459                HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
0460                HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
0461                HWMON_T_INPUT | HWMON_T_LABEL,
0462                HWMON_T_INPUT | HWMON_T_LABEL,
0463                HWMON_T_INPUT | HWMON_T_LABEL,
0464                HWMON_T_INPUT | HWMON_T_LABEL),
0465     NULL
0466 };
0467
0468 static const struct hwmon_ops max6621_hwmon_ops = {
0469     .read = max6621_read,
0470     .write = max6621_write,
0471     .read_string = max6621_read_string,
0472     .is_visible = max6621_is_visible,
0473 };
0474
0475 static const struct hwmon_chip_info max6621_chip_info = {
0476     .ops = &max6621_hwmon_ops,
0477     .info = max6621_info,
0478 };
0479
0480 static int max6621_probe(struct i2c_client *client)
0481 {
0482     struct device *dev = &client->dev;
0483     struct max6621_data *data;
0484     struct device *hwmon_dev;
0485     int i;
0486     int ret;
0487
0488     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0489     if (!data)
0490         return -ENOMEM;
0491
0492     data->regmap = devm_regmap_init_i2c(client, &max6621_regmap_config);
0493     if (IS_ERR(data->regmap))
0494         return PTR_ERR(data->regmap);
0495
0496     i2c_set_clientdata(client, data);
0497     data->client = client;
0498
0499     /* Set CONFIG0 register masking temperature alerts and PEC. */
0500     ret = regmap_write(data->regmap, MAX6621_CONFIG0_REG,
0501                MAX6621_CONFIG0_INIT);
0502     if (ret)
0503         return ret;
0504
0505     /* Set CONFIG1 register for PEC access retry number. */
0506     ret = regmap_write(data->regmap, MAX6621_CONFIG1_REG,
0507                MAX6621_CONFIG1_INIT);
0508     if (ret)
0509         return ret;
0510
0511     /* Sync registers with hardware. */
0512     regcache_mark_dirty(data->regmap);
0513     ret = regcache_sync(data->regmap);
0514     if (ret)
0515         return ret;
0516
0517     /* Verify which temperature input registers are enabled. */
0518     for (i = 0; i < MAX6621_TEMP_INPUT_REG_NUM; i++) {
0519         ret = i2c_smbus_read_word_data(client, max6621_temp_regs[i]);
0520         if (ret < 0)
0521             return ret;
0522         ret = max6621_verify_reg_data(dev, ret);
0523         if (ret) {
0524             data->input_chan2reg[i] = -1;
0525             continue;
0526         }
0527
0528         data->input_chan2reg[i] = max6621_temp_regs[i];
0529     }
0530
0531     hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
0532                              data,
0533                              &max6621_chip_info,
0534                              NULL);
0535
0536     return PTR_ERR_OR_ZERO(hwmon_dev);
0537 }
0538
0539 static const struct i2c_device_id max6621_id[] = {
0540     { MAX6621_DRV_NAME, 0 },
0541     { }
0542 };
0543 MODULE_DEVICE_TABLE(i2c, max6621_id);
0544
0545 static const struct of_device_id __maybe_unused max6621_of_match[] = {
0546     { .compatible = "maxim,max6621" },
0547     { }
0548 };
0549 MODULE_DEVICE_TABLE(of, max6621_of_match);
0550
0551 static struct i2c_driver max6621_driver = {
0552     .class      = I2C_CLASS_HWMON,
0553     .driver = {
0554         .name = MAX6621_DRV_NAME,
0555         .of_match_table = of_match_ptr(max6621_of_match),
0556     },
0557     .probe_new  = max6621_probe,
0558     .id_table   = max6621_id,
0559 };
0560
0561 module_i2c_driver(max6621_driver);
0562
0563 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
0564 MODULE_DESCRIPTION("Driver for Maxim MAX6621");
0565 MODULE_LICENSE("GPL");