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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003  * LTC2992 - Dual Wide Range Power Monitor
0004  *
0005  * Copyright 2020 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/bitops.h>
0010 #include <linux/err.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/hwmon.h>
0013 #include <linux/i2c.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/property.h>
0017 #include <linux/regmap.h>
0018 
0019 #define LTC2992_CTRLB           0x01
0020 #define LTC2992_FAULT1          0x03
0021 #define LTC2992_POWER1          0x05
0022 #define LTC2992_POWER1_MAX      0x08
0023 #define LTC2992_POWER1_MIN      0x0B
0024 #define LTC2992_POWER1_MAX_THRESH   0x0E
0025 #define LTC2992_POWER1_MIN_THRESH   0x11
0026 #define LTC2992_DSENSE1         0x14
0027 #define LTC2992_DSENSE1_MAX     0x16
0028 #define LTC2992_DSENSE1_MIN     0x18
0029 #define LTC2992_DSENSE1_MAX_THRESH  0x1A
0030 #define LTC2992_DSENSE1_MIN_THRESH  0x1C
0031 #define LTC2992_SENSE1          0x1E
0032 #define LTC2992_SENSE1_MAX      0x20
0033 #define LTC2992_SENSE1_MIN      0x22
0034 #define LTC2992_SENSE1_MAX_THRESH   0x24
0035 #define LTC2992_SENSE1_MIN_THRESH   0x26
0036 #define LTC2992_G1          0x28
0037 #define LTC2992_G1_MAX          0x2A
0038 #define LTC2992_G1_MIN          0x2C
0039 #define LTC2992_G1_MAX_THRESH       0x2E
0040 #define LTC2992_G1_MIN_THRESH       0x30
0041 #define LTC2992_FAULT2          0x35
0042 #define LTC2992_G2          0x5A
0043 #define LTC2992_G2_MAX          0x5C
0044 #define LTC2992_G2_MIN          0x5E
0045 #define LTC2992_G2_MAX_THRESH       0x60
0046 #define LTC2992_G2_MIN_THRESH       0x62
0047 #define LTC2992_G3          0x64
0048 #define LTC2992_G3_MAX          0x66
0049 #define LTC2992_G3_MIN          0x68
0050 #define LTC2992_G3_MAX_THRESH       0x6A
0051 #define LTC2992_G3_MIN_THRESH       0x6C
0052 #define LTC2992_G4          0x6E
0053 #define LTC2992_G4_MAX          0x70
0054 #define LTC2992_G4_MIN          0x72
0055 #define LTC2992_G4_MAX_THRESH       0x74
0056 #define LTC2992_G4_MIN_THRESH       0x76
0057 #define LTC2992_FAULT3          0x92
0058 #define LTC2992_GPIO_STATUS     0x95
0059 #define LTC2992_GPIO_IO_CTRL        0x96
0060 #define LTC2992_GPIO_CTRL       0x97
0061 
0062 #define LTC2992_POWER(x)        (LTC2992_POWER1 + ((x) * 0x32))
0063 #define LTC2992_POWER_MAX(x)        (LTC2992_POWER1_MAX + ((x) * 0x32))
0064 #define LTC2992_POWER_MIN(x)        (LTC2992_POWER1_MIN + ((x) * 0x32))
0065 #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
0066 #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
0067 #define LTC2992_DSENSE(x)       (LTC2992_DSENSE1 + ((x) * 0x32))
0068 #define LTC2992_DSENSE_MAX(x)       (LTC2992_DSENSE1_MAX + ((x) * 0x32))
0069 #define LTC2992_DSENSE_MIN(x)       (LTC2992_DSENSE1_MIN + ((x) * 0x32))
0070 #define LTC2992_DSENSE_MAX_THRESH(x)    (LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
0071 #define LTC2992_DSENSE_MIN_THRESH(x)    (LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
0072 #define LTC2992_SENSE(x)        (LTC2992_SENSE1 + ((x) * 0x32))
0073 #define LTC2992_SENSE_MAX(x)        (LTC2992_SENSE1_MAX + ((x) * 0x32))
0074 #define LTC2992_SENSE_MIN(x)        (LTC2992_SENSE1_MIN + ((x) * 0x32))
0075 #define LTC2992_SENSE_MAX_THRESH(x) (LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
0076 #define LTC2992_SENSE_MIN_THRESH(x) (LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
0077 #define LTC2992_POWER_FAULT(x)      (LTC2992_FAULT1 + ((x) * 0x32))
0078 #define LTC2992_SENSE_FAULT(x)      (LTC2992_FAULT1 + ((x) * 0x32))
0079 #define LTC2992_DSENSE_FAULT(x)     (LTC2992_FAULT1 + ((x) * 0x32))
0080 
0081 /* CTRLB register bitfields */
0082 #define LTC2992_RESET_HISTORY       BIT(3)
0083 
0084 /* FAULT1 FAULT2 registers common bitfields */
0085 #define LTC2992_POWER_FAULT_MSK(x)  (BIT(6) << (x))
0086 #define LTC2992_DSENSE_FAULT_MSK(x) (BIT(4) << (x))
0087 #define LTC2992_SENSE_FAULT_MSK(x)  (BIT(2) << (x))
0088 
0089 /* FAULT1 bitfields */
0090 #define LTC2992_GPIO1_FAULT_MSK(x)  (BIT(0) << (x))
0091 
0092 /* FAULT2 bitfields */
0093 #define LTC2992_GPIO2_FAULT_MSK(x)  (BIT(0) << (x))
0094 
0095 /* FAULT3 bitfields */
0096 #define LTC2992_GPIO3_FAULT_MSK(x)  (BIT(6) << (x))
0097 #define LTC2992_GPIO4_FAULT_MSK(x)  (BIT(4) << (x))
0098 
0099 #define LTC2992_IADC_NANOV_LSB      12500
0100 #define LTC2992_VADC_UV_LSB     25000
0101 #define LTC2992_VADC_GPIO_UV_LSB    500
0102 
0103 #define LTC2992_GPIO_NR     4
0104 #define LTC2992_GPIO1_BIT   7
0105 #define LTC2992_GPIO2_BIT   6
0106 #define LTC2992_GPIO3_BIT   0
0107 #define LTC2992_GPIO4_BIT   6
0108 #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
0109 
0110 struct ltc2992_state {
0111     struct i2c_client       *client;
0112     struct gpio_chip        gc;
0113     struct mutex            gpio_mutex; /* lock for gpio access */
0114     const char          *gpio_names[LTC2992_GPIO_NR];
0115     struct regmap           *regmap;
0116     u32             r_sense_uohm[2];
0117 };
0118 
0119 struct ltc2992_gpio_regs {
0120     u8  data;
0121     u8  max;
0122     u8  min;
0123     u8  max_thresh;
0124     u8  min_thresh;
0125     u8  alarm;
0126     u8  min_alarm_msk;
0127     u8  max_alarm_msk;
0128     u8  ctrl;
0129     u8  ctrl_bit;
0130 };
0131 
0132 static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
0133     {
0134         .data = LTC2992_G1,
0135         .max = LTC2992_G1_MAX,
0136         .min = LTC2992_G1_MIN,
0137         .max_thresh = LTC2992_G1_MAX_THRESH,
0138         .min_thresh = LTC2992_G1_MIN_THRESH,
0139         .alarm = LTC2992_FAULT1,
0140         .min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
0141         .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
0142         .ctrl = LTC2992_GPIO_IO_CTRL,
0143         .ctrl_bit = LTC2992_GPIO1_BIT,
0144     },
0145     {
0146         .data = LTC2992_G2,
0147         .max = LTC2992_G2_MAX,
0148         .min = LTC2992_G2_MIN,
0149         .max_thresh = LTC2992_G2_MAX_THRESH,
0150         .min_thresh = LTC2992_G2_MIN_THRESH,
0151         .alarm = LTC2992_FAULT2,
0152         .min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
0153         .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
0154         .ctrl = LTC2992_GPIO_IO_CTRL,
0155         .ctrl_bit = LTC2992_GPIO2_BIT,
0156     },
0157     {
0158         .data = LTC2992_G3,
0159         .max = LTC2992_G3_MAX,
0160         .min = LTC2992_G3_MIN,
0161         .max_thresh = LTC2992_G3_MAX_THRESH,
0162         .min_thresh = LTC2992_G3_MIN_THRESH,
0163         .alarm = LTC2992_FAULT3,
0164         .min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
0165         .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
0166         .ctrl = LTC2992_GPIO_IO_CTRL,
0167         .ctrl_bit = LTC2992_GPIO3_BIT,
0168     },
0169     {
0170         .data = LTC2992_G4,
0171         .max = LTC2992_G4_MAX,
0172         .min = LTC2992_G4_MIN,
0173         .max_thresh = LTC2992_G4_MAX_THRESH,
0174         .min_thresh = LTC2992_G4_MIN_THRESH,
0175         .alarm = LTC2992_FAULT3,
0176         .min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
0177         .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
0178         .ctrl = LTC2992_GPIO_CTRL,
0179         .ctrl_bit = LTC2992_GPIO4_BIT,
0180     },
0181 };
0182 
0183 static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
0184     "GPIO1", "GPIO2", "GPIO3", "GPIO4",
0185 };
0186 
0187 static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
0188 {
0189     u8 regvals[4];
0190     int val;
0191     int ret;
0192     int i;
0193 
0194     ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
0195     if (ret < 0)
0196         return ret;
0197 
0198     val = 0;
0199     for (i = 0; i < reg_len; i++)
0200         val |= regvals[reg_len - i - 1] << (i * 8);
0201 
0202     return val;
0203 }
0204 
0205 static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
0206 {
0207     u8 regvals[4];
0208     int i;
0209 
0210     for (i = 0; i < reg_len; i++)
0211         regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
0212 
0213     return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
0214 }
0215 
0216 static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
0217 {
0218     struct ltc2992_state *st = gpiochip_get_data(chip);
0219     unsigned long gpio_status;
0220     int reg;
0221 
0222     mutex_lock(&st->gpio_mutex);
0223     reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
0224     mutex_unlock(&st->gpio_mutex);
0225 
0226     if (reg < 0)
0227         return reg;
0228 
0229     gpio_status = reg;
0230 
0231     return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
0232 }
0233 
0234 static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0235                      unsigned long *bits)
0236 {
0237     struct ltc2992_state *st = gpiochip_get_data(chip);
0238     unsigned long gpio_status;
0239     unsigned int gpio_nr;
0240     int reg;
0241 
0242     mutex_lock(&st->gpio_mutex);
0243     reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
0244     mutex_unlock(&st->gpio_mutex);
0245 
0246     if (reg < 0)
0247         return reg;
0248 
0249     gpio_status = reg;
0250 
0251     for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
0252         if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
0253             set_bit(gpio_nr, bits);
0254     }
0255 
0256     return 0;
0257 }
0258 
0259 static void ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0260 {
0261     struct ltc2992_state *st = gpiochip_get_data(chip);
0262     unsigned long gpio_ctrl;
0263     int reg;
0264 
0265     mutex_lock(&st->gpio_mutex);
0266     reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
0267     if (reg < 0) {
0268         mutex_unlock(&st->gpio_mutex);
0269         return;
0270     }
0271 
0272     gpio_ctrl = reg;
0273     assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
0274 
0275     ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, gpio_ctrl);
0276     mutex_unlock(&st->gpio_mutex);
0277 }
0278 
0279 static void ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
0280                       unsigned long *bits)
0281 {
0282     struct ltc2992_state *st = gpiochip_get_data(chip);
0283     unsigned long gpio_ctrl_io = 0;
0284     unsigned long gpio_ctrl = 0;
0285     unsigned int gpio_nr;
0286 
0287     for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
0288         if (gpio_nr < 3)
0289             assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
0290 
0291         if (gpio_nr == 3)
0292             assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
0293     }
0294 
0295     mutex_lock(&st->gpio_mutex);
0296     ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
0297     ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
0298     mutex_unlock(&st->gpio_mutex);
0299 }
0300 
0301 static int ltc2992_config_gpio(struct ltc2992_state *st)
0302 {
0303     const char *name = dev_name(&st->client->dev);
0304     char *gpio_name;
0305     int ret;
0306     int i;
0307 
0308     ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
0309     if (ret < 0)
0310         return ret;
0311 
0312     mutex_init(&st->gpio_mutex);
0313 
0314     for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
0315         gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
0316                        st->client->addr, ltc2992_gpio_names[i]);
0317         if (!gpio_name)
0318             return -ENOMEM;
0319 
0320         st->gpio_names[i] = gpio_name;
0321     }
0322 
0323     st->gc.label = name;
0324     st->gc.parent = &st->client->dev;
0325     st->gc.owner = THIS_MODULE;
0326     st->gc.base = -1;
0327     st->gc.names = st->gpio_names;
0328     st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
0329     st->gc.get = ltc2992_gpio_get;
0330     st->gc.get_multiple = ltc2992_gpio_get_multiple;
0331     st->gc.set = ltc2992_gpio_set;
0332     st->gc.set_multiple = ltc2992_gpio_set_multiple;
0333 
0334     ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
0335     if (ret)
0336         dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
0337 
0338     return ret;
0339 }
0340 
0341 static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
0342                   int channel)
0343 {
0344     const struct ltc2992_state *st = data;
0345 
0346     switch (type) {
0347     case hwmon_chip:
0348         switch (attr) {
0349         case hwmon_chip_in_reset_history:
0350             return 0200;
0351         }
0352         break;
0353     case hwmon_in:
0354         switch (attr) {
0355         case hwmon_in_input:
0356         case hwmon_in_lowest:
0357         case hwmon_in_highest:
0358         case hwmon_in_min_alarm:
0359         case hwmon_in_max_alarm:
0360             return 0444;
0361         case hwmon_in_min:
0362         case hwmon_in_max:
0363             return 0644;
0364         }
0365         break;
0366     case hwmon_curr:
0367         switch (attr) {
0368         case hwmon_curr_input:
0369         case hwmon_curr_lowest:
0370         case hwmon_curr_highest:
0371         case hwmon_curr_min_alarm:
0372         case hwmon_curr_max_alarm:
0373             if (st->r_sense_uohm[channel])
0374                 return 0444;
0375             break;
0376         case hwmon_curr_min:
0377         case hwmon_curr_max:
0378             if (st->r_sense_uohm[channel])
0379                 return 0644;
0380             break;
0381         }
0382         break;
0383     case hwmon_power:
0384         switch (attr) {
0385         case hwmon_power_input:
0386         case hwmon_power_input_lowest:
0387         case hwmon_power_input_highest:
0388         case hwmon_power_min_alarm:
0389         case hwmon_power_max_alarm:
0390             if (st->r_sense_uohm[channel])
0391                 return 0444;
0392             break;
0393         case hwmon_power_min:
0394         case hwmon_power_max:
0395             if (st->r_sense_uohm[channel])
0396                 return 0644;
0397             break;
0398         }
0399         break;
0400     default:
0401         break;
0402     }
0403 
0404     return 0;
0405 }
0406 
0407 static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
0408 {
0409     int reg_val;
0410 
0411     reg_val = ltc2992_read_reg(st, reg, 2);
0412     if (reg_val < 0)
0413         return reg_val;
0414 
0415     reg_val = reg_val >> 4;
0416     *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
0417 
0418     return 0;
0419 }
0420 
0421 static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
0422 {
0423     val = DIV_ROUND_CLOSEST(val * 1000, scale);
0424     val = val << 4;
0425 
0426     return ltc2992_write_reg(st, reg, 2, val);
0427 }
0428 
0429 static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
0430 {
0431     int reg_val;
0432     u32 mask;
0433 
0434     if (attr == hwmon_in_max_alarm)
0435         mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
0436     else
0437         mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
0438 
0439     reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
0440     if (reg_val < 0)
0441         return reg_val;
0442 
0443     *val = !!(reg_val & mask);
0444     reg_val &= ~mask;
0445 
0446     return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
0447 }
0448 
0449 static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
0450 {
0451     struct ltc2992_state *st = dev_get_drvdata(dev);
0452     u32 reg;
0453 
0454     switch (attr) {
0455     case hwmon_in_input:
0456         reg = ltc2992_gpio_addr_map[nr_gpio].data;
0457         break;
0458     case hwmon_in_lowest:
0459         reg = ltc2992_gpio_addr_map[nr_gpio].min;
0460         break;
0461     case hwmon_in_highest:
0462         reg = ltc2992_gpio_addr_map[nr_gpio].max;
0463         break;
0464     case hwmon_in_min:
0465         reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
0466         break;
0467     case hwmon_in_max:
0468         reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
0469         break;
0470     case hwmon_in_min_alarm:
0471     case hwmon_in_max_alarm:
0472         return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
0473     default:
0474         return -EOPNOTSUPP;
0475     }
0476 
0477     return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
0478 }
0479 
0480 static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
0481 {
0482     int reg_val;
0483     u32 mask;
0484 
0485     if (attr == hwmon_in_max_alarm)
0486         mask = LTC2992_SENSE_FAULT_MSK(1);
0487     else
0488         mask = LTC2992_SENSE_FAULT_MSK(0);
0489 
0490     reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
0491     if (reg_val < 0)
0492         return reg_val;
0493 
0494     *val = !!(reg_val & mask);
0495     reg_val &= ~mask;
0496 
0497     return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
0498 }
0499 
0500 static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
0501 {
0502     struct ltc2992_state *st = dev_get_drvdata(dev);
0503     u32 reg;
0504 
0505     if (channel > 1)
0506         return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
0507 
0508     switch (attr) {
0509     case hwmon_in_input:
0510         reg = LTC2992_SENSE(channel);
0511         break;
0512     case hwmon_in_lowest:
0513         reg = LTC2992_SENSE_MIN(channel);
0514         break;
0515     case hwmon_in_highest:
0516         reg = LTC2992_SENSE_MAX(channel);
0517         break;
0518     case hwmon_in_min:
0519         reg = LTC2992_SENSE_MIN_THRESH(channel);
0520         break;
0521     case hwmon_in_max:
0522         reg = LTC2992_SENSE_MAX_THRESH(channel);
0523         break;
0524     case hwmon_in_min_alarm:
0525     case hwmon_in_max_alarm:
0526         return ltc2992_read_in_alarm(st, channel, val, attr);
0527     default:
0528         return -EOPNOTSUPP;
0529     }
0530 
0531     return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
0532 }
0533 
0534 static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
0535 {
0536     int reg_val;
0537 
0538     reg_val = ltc2992_read_reg(st, reg, 2);
0539     if (reg_val < 0)
0540         return reg_val;
0541 
0542     reg_val = reg_val >> 4;
0543     *val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
0544 
0545     return 0;
0546 }
0547 
0548 static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
0549 {
0550     u32 reg_val;
0551 
0552     reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);
0553     reg_val = reg_val << 4;
0554 
0555     return ltc2992_write_reg(st, reg, 2, reg_val);
0556 }
0557 
0558 static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
0559 {
0560     int reg_val;
0561     u32 mask;
0562 
0563     if (attr == hwmon_curr_max_alarm)
0564         mask = LTC2992_DSENSE_FAULT_MSK(1);
0565     else
0566         mask = LTC2992_DSENSE_FAULT_MSK(0);
0567 
0568     reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
0569     if (reg_val < 0)
0570         return reg_val;
0571 
0572     *val = !!(reg_val & mask);
0573 
0574     reg_val &= ~mask;
0575     return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
0576 }
0577 
0578 static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
0579 {
0580     struct ltc2992_state *st = dev_get_drvdata(dev);
0581     u32 reg;
0582 
0583     switch (attr) {
0584     case hwmon_curr_input:
0585         reg = LTC2992_DSENSE(channel);
0586         break;
0587     case hwmon_curr_lowest:
0588         reg = LTC2992_DSENSE_MIN(channel);
0589         break;
0590     case hwmon_curr_highest:
0591         reg = LTC2992_DSENSE_MAX(channel);
0592         break;
0593     case hwmon_curr_min:
0594         reg = LTC2992_DSENSE_MIN_THRESH(channel);
0595         break;
0596     case hwmon_curr_max:
0597         reg = LTC2992_DSENSE_MAX_THRESH(channel);
0598         break;
0599     case hwmon_curr_min_alarm:
0600     case hwmon_curr_max_alarm:
0601         return ltc2992_read_curr_alarm(st, channel, val, attr);
0602     default:
0603         return -EOPNOTSUPP;
0604     }
0605 
0606     return ltc2992_get_current(st, reg, channel, val);
0607 }
0608 
0609 static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
0610 {
0611     int reg_val;
0612 
0613     reg_val = ltc2992_read_reg(st, reg, 3);
0614     if (reg_val < 0)
0615         return reg_val;
0616 
0617     *val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,
0618                    st->r_sense_uohm[channel] * 1000);
0619 
0620     return 0;
0621 }
0622 
0623 static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
0624 {
0625     u32 reg_val;
0626 
0627     reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,
0628                   LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB);
0629 
0630     return ltc2992_write_reg(st, reg, 3, reg_val);
0631 }
0632 
0633 static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
0634 {
0635     int reg_val;
0636     u32 mask;
0637 
0638     if (attr == hwmon_power_max_alarm)
0639         mask = LTC2992_POWER_FAULT_MSK(1);
0640     else
0641         mask = LTC2992_POWER_FAULT_MSK(0);
0642 
0643     reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
0644     if (reg_val < 0)
0645         return reg_val;
0646 
0647     *val = !!(reg_val & mask);
0648     reg_val &= ~mask;
0649 
0650     return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
0651 }
0652 
0653 static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
0654 {
0655     struct ltc2992_state *st = dev_get_drvdata(dev);
0656     u32 reg;
0657 
0658     switch (attr) {
0659     case hwmon_power_input:
0660         reg = LTC2992_POWER(channel);
0661         break;
0662     case hwmon_power_input_lowest:
0663         reg = LTC2992_POWER_MIN(channel);
0664         break;
0665     case hwmon_power_input_highest:
0666         reg = LTC2992_POWER_MAX(channel);
0667         break;
0668     case hwmon_power_min:
0669         reg = LTC2992_POWER_MIN_THRESH(channel);
0670         break;
0671     case hwmon_power_max:
0672         reg = LTC2992_POWER_MAX_THRESH(channel);
0673         break;
0674     case hwmon_power_min_alarm:
0675     case hwmon_power_max_alarm:
0676         return ltc2992_read_power_alarm(st, channel, val, attr);
0677     default:
0678         return -EOPNOTSUPP;
0679     }
0680 
0681     return ltc2992_get_power(st, reg, channel, val);
0682 }
0683 
0684 static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
0685             long *val)
0686 {
0687     switch (type) {
0688     case hwmon_in:
0689         return ltc2992_read_in(dev, attr, channel, val);
0690     case hwmon_curr:
0691         return ltc2992_read_curr(dev, attr, channel, val);
0692     case hwmon_power:
0693         return ltc2992_read_power(dev, attr, channel, val);
0694     default:
0695         return -EOPNOTSUPP;
0696     }
0697 }
0698 
0699 static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
0700 {
0701     struct ltc2992_state *st = dev_get_drvdata(dev);
0702     u32 reg;
0703 
0704     switch (attr) {
0705     case hwmon_curr_min:
0706         reg = LTC2992_DSENSE_MIN_THRESH(channel);
0707         break;
0708     case hwmon_curr_max:
0709         reg = LTC2992_DSENSE_MAX_THRESH(channel);
0710         break;
0711     default:
0712         return -EOPNOTSUPP;
0713     }
0714 
0715     return ltc2992_set_current(st, reg, channel, val);
0716 }
0717 
0718 static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
0719 {
0720     struct ltc2992_state *st = dev_get_drvdata(dev);
0721     u32 reg;
0722 
0723     switch (attr) {
0724     case hwmon_in_min:
0725         reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
0726         break;
0727     case hwmon_in_max:
0728         reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
0729         break;
0730     default:
0731         return -EOPNOTSUPP;
0732     }
0733 
0734     return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
0735 }
0736 
0737 static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
0738 {
0739     struct ltc2992_state *st = dev_get_drvdata(dev);
0740     u32 reg;
0741 
0742     if (channel > 1)
0743         return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
0744 
0745     switch (attr) {
0746     case hwmon_in_min:
0747         reg = LTC2992_SENSE_MIN_THRESH(channel);
0748         break;
0749     case hwmon_in_max:
0750         reg = LTC2992_SENSE_MAX_THRESH(channel);
0751         break;
0752     default:
0753         return -EOPNOTSUPP;
0754     }
0755 
0756     return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
0757 }
0758 
0759 static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
0760 {
0761     struct ltc2992_state *st = dev_get_drvdata(dev);
0762     u32 reg;
0763 
0764     switch (attr) {
0765     case hwmon_power_min:
0766         reg = LTC2992_POWER_MIN_THRESH(channel);
0767         break;
0768     case hwmon_power_max:
0769         reg = LTC2992_POWER_MAX_THRESH(channel);
0770         break;
0771     default:
0772         return -EOPNOTSUPP;
0773     }
0774 
0775     return ltc2992_set_power(st, reg, channel, val);
0776 }
0777 
0778 static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
0779 {
0780     struct ltc2992_state *st = dev_get_drvdata(dev);
0781 
0782     switch (attr) {
0783     case hwmon_chip_in_reset_history:
0784         return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
0785                       LTC2992_RESET_HISTORY);
0786     default:
0787         return -EOPNOTSUPP;
0788     }
0789 }
0790 
0791 static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
0792              long val)
0793 {
0794     switch (type) {
0795     case hwmon_chip:
0796         return ltc2992_write_chip(dev, attr, channel, val);
0797     case hwmon_in:
0798         return ltc2992_write_in(dev, attr, channel, val);
0799     case hwmon_curr:
0800         return ltc2992_write_curr(dev, attr, channel, val);
0801     case hwmon_power:
0802         return ltc2992_write_power(dev, attr, channel, val);
0803     default:
0804         return -EOPNOTSUPP;
0805     }
0806 }
0807 
0808 static const struct hwmon_ops ltc2992_hwmon_ops = {
0809     .is_visible = ltc2992_is_visible,
0810     .read = ltc2992_read,
0811     .write = ltc2992_write,
0812 };
0813 
0814 static const struct hwmon_channel_info *ltc2992_info[] = {
0815     HWMON_CHANNEL_INFO(chip,
0816                HWMON_C_IN_RESET_HISTORY),
0817     HWMON_CHANNEL_INFO(in,
0818                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0819                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
0820                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0821                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
0822                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0823                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
0824                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0825                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
0826                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0827                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
0828                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
0829                HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM),
0830     HWMON_CHANNEL_INFO(curr,
0831                HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
0832                HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
0833                HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
0834                HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM),
0835     HWMON_CHANNEL_INFO(power,
0836                HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
0837                HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
0838                HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
0839                HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM),
0840     NULL
0841 };
0842 
0843 static const struct hwmon_chip_info ltc2992_chip_info = {
0844     .ops = &ltc2992_hwmon_ops,
0845     .info = ltc2992_info,
0846 };
0847 
0848 static const struct regmap_config ltc2992_regmap_config = {
0849     .reg_bits = 8,
0850     .val_bits = 8,
0851     .max_register = 0xE8,
0852 };
0853 
0854 static int ltc2992_parse_dt(struct ltc2992_state *st)
0855 {
0856     struct fwnode_handle *fwnode;
0857     struct fwnode_handle *child;
0858     u32 addr;
0859     u32 val;
0860     int ret;
0861 
0862     fwnode = dev_fwnode(&st->client->dev);
0863 
0864     fwnode_for_each_available_child_node(fwnode, child) {
0865         ret = fwnode_property_read_u32(child, "reg", &addr);
0866         if (ret < 0) {
0867             fwnode_handle_put(child);
0868             return ret;
0869         }
0870 
0871         if (addr > 1) {
0872             fwnode_handle_put(child);
0873             return -EINVAL;
0874         }
0875 
0876         ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
0877         if (!ret)
0878             st->r_sense_uohm[addr] = val;
0879     }
0880 
0881     return 0;
0882 }
0883 
0884 static int ltc2992_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
0885 {
0886     struct device *hwmon_dev;
0887     struct ltc2992_state *st;
0888     int ret;
0889 
0890     st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
0891     if (!st)
0892         return -ENOMEM;
0893 
0894     st->client = client;
0895     st->regmap = devm_regmap_init_i2c(client, &ltc2992_regmap_config);
0896     if (IS_ERR(st->regmap))
0897         return PTR_ERR(st->regmap);
0898 
0899     ret = ltc2992_parse_dt(st);
0900     if (ret < 0)
0901         return ret;
0902 
0903     ret = ltc2992_config_gpio(st);
0904     if (ret < 0)
0905         return ret;
0906 
0907     hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
0908                              &ltc2992_chip_info, NULL);
0909 
0910     return PTR_ERR_OR_ZERO(hwmon_dev);
0911 }
0912 
0913 static const struct of_device_id ltc2992_of_match[] = {
0914     { .compatible = "adi,ltc2992" },
0915     { }
0916 };
0917 MODULE_DEVICE_TABLE(of, ltc2992_of_match);
0918 
0919 static const struct i2c_device_id ltc2992_i2c_id[] = {
0920     {"ltc2992", 0},
0921     {}
0922 };
0923 MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
0924 
0925 static struct i2c_driver ltc2992_i2c_driver = {
0926     .driver = {
0927         .name = "ltc2992",
0928         .of_match_table = ltc2992_of_match,
0929     },
0930     .probe    = ltc2992_i2c_probe,
0931     .id_table = ltc2992_i2c_id,
0932 };
0933 
0934 module_i2c_driver(ltc2992_i2c_driver);
0935 
0936 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
0937 MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
0938 MODULE_LICENSE("Dual BSD/GPL");
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