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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Analog Devices LTC2947 high precision power and energy monitor
0004  *
0005  * Copyright 2019 Analog Devices Inc.
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/bits.h>
0009 #include <linux/clk.h>
0010 #include <linux/device.h>
0011 #include <linux/hwmon.h>
0012 #include <linux/hwmon-sysfs.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/regmap.h>
0016 
0017 #include "ltc2947.h"
0018 
0019 /* register's */
0020 #define LTC2947_REG_PAGE_CTRL       0xFF
0021 #define LTC2947_REG_CTRL        0xF0
0022 #define LTC2947_REG_TBCTL       0xE9
0023 #define LTC2947_CONT_MODE_MASK      BIT(3)
0024 #define LTC2947_CONT_MODE(x)        FIELD_PREP(LTC2947_CONT_MODE_MASK, x)
0025 #define LTC2947_PRE_MASK        GENMASK(2, 0)
0026 #define LTC2947_PRE(x)          FIELD_PREP(LTC2947_PRE_MASK, x)
0027 #define LTC2947_DIV_MASK        GENMASK(7, 3)
0028 #define LTC2947_DIV(x)          FIELD_PREP(LTC2947_DIV_MASK, x)
0029 #define LTC2947_SHUTDOWN_MASK       BIT(0)
0030 #define LTC2947_REG_ACCUM_POL       0xE1
0031 #define LTC2947_ACCUM_POL_1_MASK    GENMASK(1, 0)
0032 #define LTC2947_ACCUM_POL_1(x)      FIELD_PREP(LTC2947_ACCUM_POL_1_MASK, x)
0033 #define LTC2947_ACCUM_POL_2_MASK    GENMASK(3, 2)
0034 #define LTC2947_ACCUM_POL_2(x)      FIELD_PREP(LTC2947_ACCUM_POL_2_MASK, x)
0035 #define LTC2947_REG_ACCUM_DEADBAND  0xE4
0036 #define LTC2947_REG_GPIOSTATCTL     0x67
0037 #define LTC2947_GPIO_EN_MASK        BIT(0)
0038 #define LTC2947_GPIO_EN(x)      FIELD_PREP(LTC2947_GPIO_EN_MASK, x)
0039 #define LTC2947_GPIO_FAN_EN_MASK    BIT(6)
0040 #define LTC2947_GPIO_FAN_EN(x)      FIELD_PREP(LTC2947_GPIO_FAN_EN_MASK, x)
0041 #define LTC2947_GPIO_FAN_POL_MASK   BIT(7)
0042 #define LTC2947_GPIO_FAN_POL(x)     FIELD_PREP(LTC2947_GPIO_FAN_POL_MASK, x)
0043 #define LTC2947_REG_GPIO_ACCUM      0xE3
0044 /* 200Khz */
0045 #define LTC2947_CLK_MIN         200000
0046 /* 25Mhz */
0047 #define LTC2947_CLK_MAX         25000000
0048 #define LTC2947_PAGE0           0
0049 #define LTC2947_PAGE1           1
0050 /* Voltage registers */
0051 #define LTC2947_REG_VOLTAGE     0xA0
0052 #define LTC2947_REG_VOLTAGE_MAX     0x50
0053 #define LTC2947_REG_VOLTAGE_MIN     0x52
0054 #define LTC2947_REG_VOLTAGE_THRE_H  0x90
0055 #define LTC2947_REG_VOLTAGE_THRE_L  0x92
0056 #define LTC2947_REG_DVCC        0xA4
0057 #define LTC2947_REG_DVCC_MAX        0x58
0058 #define LTC2947_REG_DVCC_MIN        0x5A
0059 #define LTC2947_REG_DVCC_THRE_H     0x98
0060 #define LTC2947_REG_DVCC_THRE_L     0x9A
0061 #define LTC2947_VOLTAGE_GEN_CHAN    0
0062 #define LTC2947_VOLTAGE_DVCC_CHAN   1
0063 /* in mV */
0064 #define VOLTAGE_MAX         15500
0065 #define VOLTAGE_MIN         -300
0066 #define VDVCC_MAX           15000
0067 #define VDVCC_MIN           4750
0068 /* Current registers */
0069 #define LTC2947_REG_CURRENT     0x90
0070 #define LTC2947_REG_CURRENT_MAX     0x40
0071 #define LTC2947_REG_CURRENT_MIN     0x42
0072 #define LTC2947_REG_CURRENT_THRE_H  0x80
0073 #define LTC2947_REG_CURRENT_THRE_L  0x82
0074 /* in mA */
0075 #define CURRENT_MAX         30000
0076 #define CURRENT_MIN         -30000
0077 /* Power registers */
0078 #define LTC2947_REG_POWER       0x93
0079 #define LTC2947_REG_POWER_MAX       0x44
0080 #define LTC2947_REG_POWER_MIN       0x46
0081 #define LTC2947_REG_POWER_THRE_H    0x84
0082 #define LTC2947_REG_POWER_THRE_L    0x86
0083 /* in uW */
0084 #define POWER_MAX           450000000
0085 #define POWER_MIN           -450000000
0086 /* Temperature registers */
0087 #define LTC2947_REG_TEMP        0xA2
0088 #define LTC2947_REG_TEMP_MAX        0x54
0089 #define LTC2947_REG_TEMP_MIN        0x56
0090 #define LTC2947_REG_TEMP_THRE_H     0x94
0091 #define LTC2947_REG_TEMP_THRE_L     0x96
0092 #define LTC2947_REG_TEMP_FAN_THRE_H 0x9C
0093 #define LTC2947_REG_TEMP_FAN_THRE_L 0x9E
0094 #define LTC2947_TEMP_FAN_CHAN       1
0095 /* in millidegress Celsius */
0096 #define TEMP_MAX            85000
0097 #define TEMP_MIN            -40000
0098 /* Energy registers */
0099 #define LTC2947_REG_ENERGY1     0x06
0100 #define LTC2947_REG_ENERGY2     0x16
0101 /* Status/Alarm/Overflow registers */
0102 #define LTC2947_REG_STATUS      0x80
0103 #define LTC2947_REG_STATVT      0x81
0104 #define LTC2947_REG_STATIP      0x82
0105 #define LTC2947_REG_STATVDVCC       0x87
0106 
0107 #define LTC2947_ALERTS_SIZE (LTC2947_REG_STATVDVCC - LTC2947_REG_STATUS)
0108 #define LTC2947_MAX_VOLTAGE_MASK    BIT(0)
0109 #define LTC2947_MIN_VOLTAGE_MASK    BIT(1)
0110 #define LTC2947_MAX_CURRENT_MASK    BIT(0)
0111 #define LTC2947_MIN_CURRENT_MASK    BIT(1)
0112 #define LTC2947_MAX_POWER_MASK      BIT(2)
0113 #define LTC2947_MIN_POWER_MASK      BIT(3)
0114 #define LTC2947_MAX_TEMP_MASK       BIT(2)
0115 #define LTC2947_MIN_TEMP_MASK       BIT(3)
0116 #define LTC2947_MAX_TEMP_FAN_MASK   BIT(4)
0117 #define LTC2947_MIN_TEMP_FAN_MASK   BIT(5)
0118 
0119 struct ltc2947_data {
0120     struct regmap *map;
0121     struct device *dev;
0122     /*
0123      * The mutex is needed because the device has 2 memory pages. When
0124      * reading/writing the correct page needs to be set so that, the
0125      * complete sequence select_page->read/write needs to be protected.
0126      */
0127     struct mutex lock;
0128     u32 lsb_energy;
0129     bool gpio_out;
0130 };
0131 
0132 static int __ltc2947_val_read16(const struct ltc2947_data *st, const u8 reg,
0133                 u64 *val)
0134 {
0135     __be16 __val = 0;
0136     int ret;
0137 
0138     ret = regmap_bulk_read(st->map, reg, &__val, 2);
0139     if (ret)
0140         return ret;
0141 
0142     *val = be16_to_cpu(__val);
0143 
0144     return 0;
0145 }
0146 
0147 static int __ltc2947_val_read24(const struct ltc2947_data *st, const u8 reg,
0148                 u64 *val)
0149 {
0150     __be32 __val = 0;
0151     int ret;
0152 
0153     ret = regmap_bulk_read(st->map, reg, &__val, 3);
0154     if (ret)
0155         return ret;
0156 
0157     *val = be32_to_cpu(__val) >> 8;
0158 
0159     return 0;
0160 }
0161 
0162 static int __ltc2947_val_read64(const struct ltc2947_data *st, const u8 reg,
0163                 u64 *val)
0164 {
0165     __be64 __val = 0;
0166     int ret;
0167 
0168     ret = regmap_bulk_read(st->map, reg, &__val, 6);
0169     if (ret)
0170         return ret;
0171 
0172     *val = be64_to_cpu(__val) >> 16;
0173 
0174     return 0;
0175 }
0176 
0177 static int ltc2947_val_read(struct ltc2947_data *st, const u8 reg,
0178                 const u8 page, const size_t size, s64 *val)
0179 {
0180     int ret;
0181     u64 __val = 0;
0182 
0183     mutex_lock(&st->lock);
0184 
0185     ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page);
0186     if (ret) {
0187         mutex_unlock(&st->lock);
0188         return ret;
0189     }
0190 
0191     dev_dbg(st->dev, "Read val, reg:%02X, p:%d sz:%zu\n", reg, page,
0192         size);
0193 
0194     switch (size) {
0195     case 2:
0196         ret = __ltc2947_val_read16(st, reg, &__val);
0197         break;
0198     case 3:
0199         ret = __ltc2947_val_read24(st, reg, &__val);
0200         break;
0201     case 6:
0202         ret = __ltc2947_val_read64(st, reg, &__val);
0203         break;
0204     default:
0205         ret = -EINVAL;
0206         break;
0207     }
0208 
0209     mutex_unlock(&st->lock);
0210 
0211     if (ret)
0212         return ret;
0213 
0214     *val = sign_extend64(__val, (8 * size) - 1);
0215 
0216     dev_dbg(st->dev, "Got s:%lld, u:%016llX\n", *val, __val);
0217 
0218     return 0;
0219 }
0220 
0221 static int __ltc2947_val_write64(const struct ltc2947_data *st, const u8 reg,
0222                  const u64 val)
0223 {
0224     __be64 __val;
0225 
0226     __val = cpu_to_be64(val << 16);
0227     return regmap_bulk_write(st->map, reg, &__val, 6);
0228 }
0229 
0230 static int __ltc2947_val_write16(const struct ltc2947_data *st, const u8 reg,
0231                  const u16 val)
0232 {
0233     __be16 __val;
0234 
0235     __val = cpu_to_be16(val);
0236     return regmap_bulk_write(st->map, reg, &__val, 2);
0237 }
0238 
0239 static int ltc2947_val_write(struct ltc2947_data *st, const u8 reg,
0240                  const u8 page, const size_t size, const u64 val)
0241 {
0242     int ret;
0243 
0244     mutex_lock(&st->lock);
0245     /* set device on correct page */
0246     ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page);
0247     if (ret) {
0248         mutex_unlock(&st->lock);
0249         return ret;
0250     }
0251 
0252     dev_dbg(st->dev, "Write val, r:%02X, p:%d, sz:%zu, val:%016llX\n",
0253         reg, page, size, val);
0254 
0255     switch (size) {
0256     case 2:
0257         ret = __ltc2947_val_write16(st, reg, val);
0258         break;
0259     case 6:
0260         ret = __ltc2947_val_write64(st, reg, val);
0261         break;
0262     default:
0263         ret = -EINVAL;
0264         break;
0265     }
0266 
0267     mutex_unlock(&st->lock);
0268 
0269     return ret;
0270 }
0271 
0272 static int ltc2947_reset_history(struct ltc2947_data *st, const u8 reg_h,
0273                  const u8 reg_l)
0274 {
0275     int ret;
0276     /*
0277      * let's reset the tracking register's. Tracking register's have all
0278      * 2 bytes size
0279      */
0280     ret = ltc2947_val_write(st, reg_h, LTC2947_PAGE0, 2, 0x8000U);
0281     if (ret)
0282         return ret;
0283 
0284     return ltc2947_val_write(st, reg_l, LTC2947_PAGE0, 2, 0x7FFFU);
0285 }
0286 
0287 static int ltc2947_alarm_read(struct ltc2947_data *st, const u8 reg,
0288                   const u32 mask, long *val)
0289 {
0290     u8 offset = reg - LTC2947_REG_STATUS;
0291     /* +1 to include status reg */
0292     char alarms[LTC2947_ALERTS_SIZE + 1];
0293     int ret = 0;
0294 
0295     memset(alarms, 0, sizeof(alarms));
0296 
0297     mutex_lock(&st->lock);
0298 
0299     ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, LTC2947_PAGE0);
0300     if (ret)
0301         goto unlock;
0302 
0303     dev_dbg(st->dev, "Read alarm, reg:%02X, mask:%02X\n", reg, mask);
0304     /*
0305      * As stated in the datasheet, when Threshold and Overflow registers
0306      * are used, the status and all alert registers must be read in one
0307      * multi-byte transaction.
0308      */
0309     ret = regmap_bulk_read(st->map, LTC2947_REG_STATUS, alarms,
0310                    sizeof(alarms));
0311     if (ret)
0312         goto unlock;
0313 
0314     /* get the alarm */
0315     *val = !!(alarms[offset] & mask);
0316 unlock:
0317     mutex_unlock(&st->lock);
0318     return ret;
0319 }
0320 
0321 static ssize_t ltc2947_show_value(struct device *dev,
0322                   struct device_attribute *da, char *buf)
0323 {
0324     struct ltc2947_data *st = dev_get_drvdata(dev);
0325     struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
0326     int ret;
0327     s64 val = 0;
0328 
0329     ret = ltc2947_val_read(st, attr->index, LTC2947_PAGE0, 6, &val);
0330     if (ret)
0331         return ret;
0332 
0333     /* value in microJoule. st->lsb_energy was multiplied by 10E9 */
0334     val = div_s64(val * st->lsb_energy, 1000);
0335 
0336     return sprintf(buf, "%lld\n", val);
0337 }
0338 
0339 static int ltc2947_read_temp(struct device *dev, const u32 attr, long *val,
0340                  const int channel)
0341 {
0342     int ret;
0343     struct ltc2947_data *st = dev_get_drvdata(dev);
0344     s64 __val = 0;
0345 
0346     switch (attr) {
0347     case hwmon_temp_input:
0348         ret = ltc2947_val_read(st, LTC2947_REG_TEMP, LTC2947_PAGE0,
0349                        2, &__val);
0350         break;
0351     case hwmon_temp_highest:
0352         ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MAX, LTC2947_PAGE0,
0353                        2, &__val);
0354         break;
0355     case hwmon_temp_lowest:
0356         ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MIN, LTC2947_PAGE0,
0357                        2, &__val);
0358         break;
0359     case hwmon_temp_max_alarm:
0360         if (channel == LTC2947_TEMP_FAN_CHAN)
0361             return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0362                           LTC2947_MAX_TEMP_FAN_MASK,
0363                           val);
0364 
0365         return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0366                       LTC2947_MAX_TEMP_MASK, val);
0367     case hwmon_temp_min_alarm:
0368         if (channel == LTC2947_TEMP_FAN_CHAN)
0369             return  ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0370                            LTC2947_MIN_TEMP_FAN_MASK,
0371                            val);
0372 
0373         return  ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0374                        LTC2947_MIN_TEMP_MASK, val);
0375     case hwmon_temp_max:
0376         if (channel == LTC2947_TEMP_FAN_CHAN)
0377             ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_H,
0378                            LTC2947_PAGE1, 2, &__val);
0379         else
0380             ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_H,
0381                            LTC2947_PAGE1, 2, &__val);
0382         break;
0383     case hwmon_temp_min:
0384         if (channel == LTC2947_TEMP_FAN_CHAN)
0385             ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_L,
0386                            LTC2947_PAGE1, 2, &__val);
0387         else
0388             ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_L,
0389                            LTC2947_PAGE1, 2, &__val);
0390         break;
0391     default:
0392         return -ENOTSUPP;
0393     }
0394 
0395     if (ret)
0396         return ret;
0397 
0398     /* in milidegrees celcius, temp is given by: */
0399     *val = (__val * 204) + 550;
0400 
0401     return 0;
0402 }
0403 
0404 static int ltc2947_read_power(struct device *dev, const u32 attr, long *val)
0405 {
0406     struct ltc2947_data *st = dev_get_drvdata(dev);
0407     int ret;
0408     u32 lsb = 200000; /* in uW */
0409     s64 __val = 0;
0410 
0411     switch (attr) {
0412     case hwmon_power_input:
0413         ret = ltc2947_val_read(st, LTC2947_REG_POWER, LTC2947_PAGE0,
0414                        3, &__val);
0415         lsb = 50000;
0416         break;
0417     case hwmon_power_input_highest:
0418         ret = ltc2947_val_read(st, LTC2947_REG_POWER_MAX, LTC2947_PAGE0,
0419                        2, &__val);
0420         break;
0421     case hwmon_power_input_lowest:
0422         ret = ltc2947_val_read(st, LTC2947_REG_POWER_MIN, LTC2947_PAGE0,
0423                        2, &__val);
0424         break;
0425     case hwmon_power_max_alarm:
0426         return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
0427                       LTC2947_MAX_POWER_MASK, val);
0428     case hwmon_power_min_alarm:
0429         return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
0430                       LTC2947_MIN_POWER_MASK, val);
0431     case hwmon_power_max:
0432         ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_H,
0433                        LTC2947_PAGE1, 2, &__val);
0434         break;
0435     case hwmon_power_min:
0436         ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_L,
0437                        LTC2947_PAGE1, 2, &__val);
0438         break;
0439     default:
0440         return -ENOTSUPP;
0441     }
0442 
0443     if (ret)
0444         return ret;
0445 
0446     *val = __val * lsb;
0447 
0448     return 0;
0449 }
0450 
0451 static int ltc2947_read_curr(struct device *dev, const u32 attr, long *val)
0452 {
0453     struct ltc2947_data *st = dev_get_drvdata(dev);
0454     int ret;
0455     u8 lsb = 12; /* in mA */
0456     s64 __val = 0;
0457 
0458     switch (attr) {
0459     case hwmon_curr_input:
0460         ret = ltc2947_val_read(st, LTC2947_REG_CURRENT,
0461                        LTC2947_PAGE0, 3, &__val);
0462         lsb = 3;
0463         break;
0464     case hwmon_curr_highest:
0465         ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MAX,
0466                        LTC2947_PAGE0, 2, &__val);
0467         break;
0468     case hwmon_curr_lowest:
0469         ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MIN,
0470                        LTC2947_PAGE0, 2, &__val);
0471         break;
0472     case hwmon_curr_max_alarm:
0473         return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
0474                       LTC2947_MAX_CURRENT_MASK, val);
0475     case hwmon_curr_min_alarm:
0476         return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
0477                       LTC2947_MIN_CURRENT_MASK, val);
0478     case hwmon_curr_max:
0479         ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_H,
0480                        LTC2947_PAGE1, 2, &__val);
0481         break;
0482     case hwmon_curr_min:
0483         ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_L,
0484                        LTC2947_PAGE1, 2, &__val);
0485         break;
0486     default:
0487         return -ENOTSUPP;
0488     }
0489 
0490     if (ret)
0491         return ret;
0492 
0493     *val = __val * lsb;
0494 
0495     return 0;
0496 }
0497 
0498 static int ltc2947_read_in(struct device *dev, const u32 attr, long *val,
0499                const int channel)
0500 {
0501     struct ltc2947_data *st = dev_get_drvdata(dev);
0502     int ret;
0503     u8 lsb = 2; /* in mV */
0504     s64 __val = 0;
0505 
0506     if (channel < 0 || channel > LTC2947_VOLTAGE_DVCC_CHAN) {
0507         dev_err(st->dev, "Invalid chan%d for voltage", channel);
0508         return -EINVAL;
0509     }
0510 
0511     switch (attr) {
0512     case hwmon_in_input:
0513         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0514             ret = ltc2947_val_read(st, LTC2947_REG_DVCC,
0515                            LTC2947_PAGE0, 2, &__val);
0516             lsb = 145;
0517         } else {
0518             ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE,
0519                            LTC2947_PAGE0, 2, &__val);
0520         }
0521         break;
0522     case hwmon_in_highest:
0523         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0524             ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MAX,
0525                            LTC2947_PAGE0, 2, &__val);
0526             lsb = 145;
0527         } else {
0528             ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MAX,
0529                            LTC2947_PAGE0, 2, &__val);
0530         }
0531         break;
0532     case hwmon_in_lowest:
0533         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0534             ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MIN,
0535                            LTC2947_PAGE0, 2, &__val);
0536             lsb = 145;
0537         } else {
0538             ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MIN,
0539                            LTC2947_PAGE0, 2, &__val);
0540         }
0541         break;
0542     case hwmon_in_max_alarm:
0543         if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
0544             return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC,
0545                           LTC2947_MAX_VOLTAGE_MASK,
0546                           val);
0547 
0548         return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0549                       LTC2947_MAX_VOLTAGE_MASK, val);
0550     case hwmon_in_min_alarm:
0551         if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
0552             return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC,
0553                           LTC2947_MIN_VOLTAGE_MASK,
0554                           val);
0555 
0556         return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
0557                       LTC2947_MIN_VOLTAGE_MASK, val);
0558     case hwmon_in_max:
0559         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0560             ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_H,
0561                            LTC2947_PAGE1, 2, &__val);
0562             lsb = 145;
0563         } else {
0564             ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_H,
0565                            LTC2947_PAGE1, 2, &__val);
0566         }
0567         break;
0568     case hwmon_in_min:
0569         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0570             ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_L,
0571                            LTC2947_PAGE1, 2, &__val);
0572             lsb = 145;
0573         } else {
0574             ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_L,
0575                            LTC2947_PAGE1, 2, &__val);
0576         }
0577         break;
0578     default:
0579         return -ENOTSUPP;
0580     }
0581 
0582     if (ret)
0583         return ret;
0584 
0585     *val = __val * lsb;
0586 
0587     return 0;
0588 }
0589 
0590 static int ltc2947_read(struct device *dev, enum hwmon_sensor_types type,
0591             u32 attr, int channel, long *val)
0592 {
0593     switch (type) {
0594     case hwmon_in:
0595         return ltc2947_read_in(dev, attr, val, channel);
0596     case hwmon_curr:
0597         return ltc2947_read_curr(dev, attr, val);
0598     case hwmon_power:
0599         return ltc2947_read_power(dev, attr, val);
0600     case hwmon_temp:
0601         return ltc2947_read_temp(dev, attr, val, channel);
0602     default:
0603         return -ENOTSUPP;
0604     }
0605 }
0606 
0607 static int ltc2947_write_temp(struct device *dev, const u32 attr,
0608                   long val, const int channel)
0609 {
0610     struct ltc2947_data *st = dev_get_drvdata(dev);
0611 
0612     if (channel < 0 || channel > LTC2947_TEMP_FAN_CHAN) {
0613         dev_err(st->dev, "Invalid chan%d for temperature", channel);
0614         return -EINVAL;
0615     }
0616 
0617     switch (attr) {
0618     case hwmon_temp_reset_history:
0619         if (val != 1)
0620             return -EINVAL;
0621         return ltc2947_reset_history(st, LTC2947_REG_TEMP_MAX,
0622                          LTC2947_REG_TEMP_MIN);
0623     case hwmon_temp_max:
0624         val = clamp_val(val, TEMP_MIN, TEMP_MAX);
0625         if (channel == LTC2947_TEMP_FAN_CHAN) {
0626             if (!st->gpio_out)
0627                 return -ENOTSUPP;
0628 
0629             return ltc2947_val_write(st,
0630                     LTC2947_REG_TEMP_FAN_THRE_H,
0631                     LTC2947_PAGE1, 2,
0632                     DIV_ROUND_CLOSEST(val - 550, 204));
0633         }
0634 
0635         return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_H,
0636                      LTC2947_PAGE1, 2,
0637                      DIV_ROUND_CLOSEST(val - 550, 204));
0638     case hwmon_temp_min:
0639         val = clamp_val(val, TEMP_MIN, TEMP_MAX);
0640         if (channel == LTC2947_TEMP_FAN_CHAN) {
0641             if (!st->gpio_out)
0642                 return -ENOTSUPP;
0643 
0644             return ltc2947_val_write(st,
0645                     LTC2947_REG_TEMP_FAN_THRE_L,
0646                     LTC2947_PAGE1, 2,
0647                     DIV_ROUND_CLOSEST(val - 550, 204));
0648         }
0649 
0650         return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_L,
0651                      LTC2947_PAGE1, 2,
0652                      DIV_ROUND_CLOSEST(val - 550, 204));
0653     default:
0654         return -ENOTSUPP;
0655     }
0656 }
0657 
0658 static int ltc2947_write_power(struct device *dev, const u32 attr,
0659                    long val)
0660 {
0661     struct ltc2947_data *st = dev_get_drvdata(dev);
0662 
0663     switch (attr) {
0664     case hwmon_power_reset_history:
0665         if (val != 1)
0666             return -EINVAL;
0667         return ltc2947_reset_history(st, LTC2947_REG_POWER_MAX,
0668                          LTC2947_REG_POWER_MIN);
0669     case hwmon_power_max:
0670         val = clamp_val(val, POWER_MIN, POWER_MAX);
0671         return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H,
0672                      LTC2947_PAGE1, 2,
0673                      DIV_ROUND_CLOSEST(val, 200000));
0674     case hwmon_power_min:
0675         val = clamp_val(val, POWER_MIN, POWER_MAX);
0676         return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L,
0677                      LTC2947_PAGE1, 2,
0678                      DIV_ROUND_CLOSEST(val, 200000));
0679     default:
0680         return -ENOTSUPP;
0681     }
0682 }
0683 
0684 static int ltc2947_write_curr(struct device *dev, const u32 attr,
0685                   long val)
0686 {
0687     struct ltc2947_data *st = dev_get_drvdata(dev);
0688 
0689     switch (attr) {
0690     case hwmon_curr_reset_history:
0691         if (val != 1)
0692             return -EINVAL;
0693         return ltc2947_reset_history(st, LTC2947_REG_CURRENT_MAX,
0694                          LTC2947_REG_CURRENT_MIN);
0695     case hwmon_curr_max:
0696         val = clamp_val(val, CURRENT_MIN, CURRENT_MAX);
0697         return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_H,
0698                      LTC2947_PAGE1, 2,
0699                      DIV_ROUND_CLOSEST(val, 12));
0700     case hwmon_curr_min:
0701         val = clamp_val(val, CURRENT_MIN, CURRENT_MAX);
0702         return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_L,
0703                      LTC2947_PAGE1, 2,
0704                      DIV_ROUND_CLOSEST(val, 12));
0705     default:
0706         return -ENOTSUPP;
0707     }
0708 }
0709 
0710 static int ltc2947_write_in(struct device *dev, const u32 attr, long val,
0711                 const int channel)
0712 {
0713     struct ltc2947_data *st = dev_get_drvdata(dev);
0714 
0715     if (channel > LTC2947_VOLTAGE_DVCC_CHAN) {
0716         dev_err(st->dev, "Invalid chan%d for voltage", channel);
0717         return -EINVAL;
0718     }
0719 
0720     switch (attr) {
0721     case hwmon_in_reset_history:
0722         if (val != 1)
0723             return -EINVAL;
0724 
0725         if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
0726             return ltc2947_reset_history(st, LTC2947_REG_DVCC_MAX,
0727                              LTC2947_REG_DVCC_MIN);
0728 
0729         return ltc2947_reset_history(st, LTC2947_REG_VOLTAGE_MAX,
0730                          LTC2947_REG_VOLTAGE_MIN);
0731     case hwmon_in_max:
0732         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0733             val = clamp_val(val, VDVCC_MIN, VDVCC_MAX);
0734             return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_H,
0735                          LTC2947_PAGE1, 2,
0736                          DIV_ROUND_CLOSEST(val, 145));
0737         }
0738 
0739         val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX);
0740         return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_H,
0741                      LTC2947_PAGE1, 2,
0742                      DIV_ROUND_CLOSEST(val, 2));
0743     case hwmon_in_min:
0744         if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
0745             val = clamp_val(val, VDVCC_MIN, VDVCC_MAX);
0746             return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_L,
0747                          LTC2947_PAGE1, 2,
0748                          DIV_ROUND_CLOSEST(val, 145));
0749         }
0750 
0751         val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX);
0752         return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_L,
0753                      LTC2947_PAGE1, 2,
0754                      DIV_ROUND_CLOSEST(val, 2));
0755     default:
0756         return -ENOTSUPP;
0757     }
0758 }
0759 
0760 static int ltc2947_write(struct device *dev,
0761              enum hwmon_sensor_types type,
0762              u32 attr, int channel, long val)
0763 {
0764     switch (type) {
0765     case hwmon_in:
0766         return ltc2947_write_in(dev, attr, val, channel);
0767     case hwmon_curr:
0768         return ltc2947_write_curr(dev, attr, val);
0769     case hwmon_power:
0770         return ltc2947_write_power(dev, attr, val);
0771     case hwmon_temp:
0772         return ltc2947_write_temp(dev, attr, val, channel);
0773     default:
0774         return -ENOTSUPP;
0775     }
0776 }
0777 
0778 static int ltc2947_read_labels(struct device *dev,
0779                    enum hwmon_sensor_types type,
0780                    u32 attr, int channel, const char **str)
0781 {
0782     switch (type) {
0783     case hwmon_in:
0784         if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
0785             *str = "DVCC";
0786         else
0787             *str = "VP-VM";
0788         return 0;
0789     case hwmon_curr:
0790         *str = "IP-IM";
0791         return 0;
0792     case hwmon_temp:
0793         if (channel == LTC2947_TEMP_FAN_CHAN)
0794             *str = "TEMPFAN";
0795         else
0796             *str = "Ambient";
0797         return 0;
0798     case hwmon_power:
0799         *str = "Power";
0800         return 0;
0801     default:
0802         return -ENOTSUPP;
0803     }
0804 }
0805 
0806 static int ltc2947_in_is_visible(const u32 attr)
0807 {
0808     switch (attr) {
0809     case hwmon_in_input:
0810     case hwmon_in_highest:
0811     case hwmon_in_lowest:
0812     case hwmon_in_max_alarm:
0813     case hwmon_in_min_alarm:
0814     case hwmon_in_label:
0815         return 0444;
0816     case hwmon_in_reset_history:
0817         return 0200;
0818     case hwmon_in_max:
0819     case hwmon_in_min:
0820         return 0644;
0821     default:
0822         return 0;
0823     }
0824 }
0825 
0826 static int ltc2947_curr_is_visible(const u32 attr)
0827 {
0828     switch (attr) {
0829     case hwmon_curr_input:
0830     case hwmon_curr_highest:
0831     case hwmon_curr_lowest:
0832     case hwmon_curr_max_alarm:
0833     case hwmon_curr_min_alarm:
0834     case hwmon_curr_label:
0835         return 0444;
0836     case hwmon_curr_reset_history:
0837         return 0200;
0838     case hwmon_curr_max:
0839     case hwmon_curr_min:
0840         return 0644;
0841     default:
0842         return 0;
0843     }
0844 }
0845 
0846 static int ltc2947_power_is_visible(const u32 attr)
0847 {
0848     switch (attr) {
0849     case hwmon_power_input:
0850     case hwmon_power_input_highest:
0851     case hwmon_power_input_lowest:
0852     case hwmon_power_label:
0853     case hwmon_power_max_alarm:
0854     case hwmon_power_min_alarm:
0855         return 0444;
0856     case hwmon_power_reset_history:
0857         return 0200;
0858     case hwmon_power_max:
0859     case hwmon_power_min:
0860         return 0644;
0861     default:
0862         return 0;
0863     }
0864 }
0865 
0866 static int ltc2947_temp_is_visible(const u32 attr)
0867 {
0868     switch (attr) {
0869     case hwmon_temp_input:
0870     case hwmon_temp_highest:
0871     case hwmon_temp_lowest:
0872     case hwmon_temp_max_alarm:
0873     case hwmon_temp_min_alarm:
0874     case hwmon_temp_label:
0875         return 0444;
0876     case hwmon_temp_reset_history:
0877         return 0200;
0878     case hwmon_temp_max:
0879     case hwmon_temp_min:
0880         return 0644;
0881     default:
0882         return 0;
0883     }
0884 }
0885 
0886 static umode_t ltc2947_is_visible(const void *data,
0887                   enum hwmon_sensor_types type,
0888                   u32 attr, int channel)
0889 {
0890     switch (type) {
0891     case hwmon_in:
0892         return ltc2947_in_is_visible(attr);
0893     case hwmon_curr:
0894         return ltc2947_curr_is_visible(attr);
0895     case hwmon_power:
0896         return ltc2947_power_is_visible(attr);
0897     case hwmon_temp:
0898         return ltc2947_temp_is_visible(attr);
0899     default:
0900         return 0;
0901     }
0902 }
0903 
0904 static const struct hwmon_channel_info *ltc2947_info[] = {
0905     HWMON_CHANNEL_INFO(in,
0906                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
0907                HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY |
0908                HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM |
0909                HWMON_I_LABEL,
0910                HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
0911                HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY |
0912                HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM |
0913                HWMON_I_LABEL),
0914     HWMON_CHANNEL_INFO(curr,
0915                HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST |
0916                HWMON_C_MAX | HWMON_C_MIN | HWMON_C_RESET_HISTORY |
0917                HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM |
0918                HWMON_C_LABEL),
0919     HWMON_CHANNEL_INFO(power,
0920                HWMON_P_INPUT | HWMON_P_INPUT_LOWEST |
0921                HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN |
0922                HWMON_P_RESET_HISTORY | HWMON_P_MAX_ALARM |
0923                HWMON_P_MIN_ALARM | HWMON_P_LABEL),
0924     HWMON_CHANNEL_INFO(temp,
0925                HWMON_T_INPUT | HWMON_T_LOWEST | HWMON_T_HIGHEST |
0926                HWMON_T_MAX | HWMON_T_MIN | HWMON_T_RESET_HISTORY |
0927                HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
0928                HWMON_T_LABEL,
0929                HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM | HWMON_T_MAX |
0930                HWMON_T_MIN | HWMON_T_LABEL),
0931     NULL
0932 };
0933 
0934 static const struct hwmon_ops ltc2947_hwmon_ops = {
0935     .is_visible = ltc2947_is_visible,
0936     .read = ltc2947_read,
0937     .write = ltc2947_write,
0938     .read_string = ltc2947_read_labels,
0939 };
0940 
0941 static const struct hwmon_chip_info ltc2947_chip_info = {
0942     .ops = &ltc2947_hwmon_ops,
0943     .info = ltc2947_info,
0944 };
0945 
0946 /* energy attributes are 6bytes wide so we need u64 */
0947 static SENSOR_DEVICE_ATTR(energy1_input, 0444, ltc2947_show_value, NULL,
0948               LTC2947_REG_ENERGY1);
0949 static SENSOR_DEVICE_ATTR(energy2_input, 0444, ltc2947_show_value, NULL,
0950               LTC2947_REG_ENERGY2);
0951 
0952 static struct attribute *ltc2947_attrs[] = {
0953     &sensor_dev_attr_energy1_input.dev_attr.attr,
0954     &sensor_dev_attr_energy2_input.dev_attr.attr,
0955     NULL,
0956 };
0957 ATTRIBUTE_GROUPS(ltc2947);
0958 
0959 static void ltc2947_clk_disable(void *data)
0960 {
0961     struct clk *extclk = data;
0962 
0963     clk_disable_unprepare(extclk);
0964 }
0965 
0966 static int ltc2947_setup(struct ltc2947_data *st)
0967 {
0968     int ret;
0969     struct clk *extclk;
0970     u32 dummy, deadband, pol;
0971     u32 accum[2];
0972 
0973     /* clear status register by reading it */
0974     ret = regmap_read(st->map, LTC2947_REG_STATUS, &dummy);
0975     if (ret)
0976         return ret;
0977     /*
0978      * Set max/min for power here since the default values x scale
0979      * would overflow on 32bit arch
0980      */
0981     ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H, LTC2947_PAGE1, 2,
0982                 POWER_MAX / 200000);
0983     if (ret)
0984         return ret;
0985 
0986     ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L, LTC2947_PAGE1, 2,
0987                 POWER_MIN / 200000);
0988     if (ret)
0989         return ret;
0990 
0991     /* check external clock presence */
0992     extclk = devm_clk_get_optional(st->dev, NULL);
0993     if (IS_ERR(extclk))
0994         return dev_err_probe(st->dev, PTR_ERR(extclk),
0995                      "Failed to get external clock\n");
0996 
0997     if (extclk) {
0998         unsigned long rate_hz;
0999         u8 pre = 0, div, tbctl;
1000         u64 aux;
1001 
1002         /* let's calculate and set the right valus in TBCTL */
1003         rate_hz = clk_get_rate(extclk);
1004         if (rate_hz < LTC2947_CLK_MIN || rate_hz > LTC2947_CLK_MAX) {
1005             dev_err(st->dev, "Invalid rate:%lu for external clock",
1006                 rate_hz);
1007             return -EINVAL;
1008         }
1009 
1010         ret = clk_prepare_enable(extclk);
1011         if (ret)
1012             return ret;
1013 
1014         ret = devm_add_action_or_reset(st->dev, ltc2947_clk_disable,
1015                            extclk);
1016         if (ret)
1017             return ret;
1018         /* as in table 1 of the datasheet */
1019         if (rate_hz >= LTC2947_CLK_MIN && rate_hz <= 1000000)
1020             pre = 0;
1021         else if (rate_hz > 1000000 && rate_hz <= 2000000)
1022             pre = 1;
1023         else if (rate_hz > 2000000 && rate_hz <= 4000000)
1024             pre = 2;
1025         else if (rate_hz > 4000000 && rate_hz <= 8000000)
1026             pre = 3;
1027         else if (rate_hz > 8000000 && rate_hz <= 16000000)
1028             pre = 4;
1029         else if (rate_hz > 16000000 && rate_hz <= LTC2947_CLK_MAX)
1030             pre = 5;
1031         /*
1032          * Div is given by:
1033          *  floor(fref / (2^PRE * 32768))
1034          */
1035         div = rate_hz / ((1 << pre) * 32768);
1036         tbctl = LTC2947_PRE(pre) | LTC2947_DIV(div);
1037 
1038         ret = regmap_write(st->map, LTC2947_REG_TBCTL, tbctl);
1039         if (ret)
1040             return ret;
1041         /*
1042          * The energy lsb is given by (in W*s):
1043          *      06416 * (1/fref) * 2^PRE * (DIV + 1)
1044          * The value is multiplied by 10E9
1045          */
1046         aux = (div + 1) * ((1 << pre) * 641600000ULL);
1047         st->lsb_energy = DIV_ROUND_CLOSEST_ULL(aux, rate_hz);
1048     } else {
1049         /* 19.89E-6 * 10E9 */
1050         st->lsb_energy = 19890;
1051     }
1052     ret = of_property_read_u32_array(st->dev->of_node,
1053                      "adi,accumulator-ctl-pol", accum,
1054                       ARRAY_SIZE(accum));
1055     if (!ret) {
1056         u32 accum_reg = LTC2947_ACCUM_POL_1(accum[0]) |
1057                 LTC2947_ACCUM_POL_2(accum[1]);
1058 
1059         ret = regmap_write(st->map, LTC2947_REG_ACCUM_POL, accum_reg);
1060         if (ret)
1061             return ret;
1062     }
1063     ret = of_property_read_u32(st->dev->of_node,
1064                    "adi,accumulation-deadband-microamp",
1065                    &deadband);
1066     if (!ret) {
1067         /* the LSB is the same as the current, so 3mA */
1068         ret = regmap_write(st->map, LTC2947_REG_ACCUM_DEADBAND,
1069                    deadband / (1000 * 3));
1070         if (ret)
1071             return ret;
1072     }
1073     /* check gpio cfg */
1074     ret = of_property_read_u32(st->dev->of_node, "adi,gpio-out-pol", &pol);
1075     if (!ret) {
1076         /* setup GPIO as output */
1077         u32 gpio_ctl = LTC2947_GPIO_EN(1) | LTC2947_GPIO_FAN_EN(1) |
1078             LTC2947_GPIO_FAN_POL(pol);
1079 
1080         st->gpio_out = true;
1081         ret = regmap_write(st->map, LTC2947_REG_GPIOSTATCTL, gpio_ctl);
1082         if (ret)
1083             return ret;
1084     }
1085     ret = of_property_read_u32_array(st->dev->of_node, "adi,gpio-in-accum",
1086                      accum, ARRAY_SIZE(accum));
1087     if (!ret) {
1088         /*
1089          * Setup the accum options. The gpioctl is already defined as
1090          * input by default.
1091          */
1092         u32 accum_val = LTC2947_ACCUM_POL_1(accum[0]) |
1093                 LTC2947_ACCUM_POL_2(accum[1]);
1094 
1095         if (st->gpio_out) {
1096             dev_err(st->dev,
1097                 "Cannot have input gpio config if already configured as output");
1098             return -EINVAL;
1099         }
1100 
1101         ret = regmap_write(st->map, LTC2947_REG_GPIO_ACCUM, accum_val);
1102         if (ret)
1103             return ret;
1104     }
1105 
1106     /* set continuos mode */
1107     return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1108                   LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1));
1109 }
1110 
1111 int ltc2947_core_probe(struct regmap *map, const char *name)
1112 {
1113     struct ltc2947_data *st;
1114     struct device *dev = regmap_get_device(map);
1115     struct device *hwmon;
1116     int ret;
1117 
1118     st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
1119     if (!st)
1120         return -ENOMEM;
1121 
1122     st->map = map;
1123     st->dev = dev;
1124     dev_set_drvdata(dev, st);
1125     mutex_init(&st->lock);
1126 
1127     ret = ltc2947_setup(st);
1128     if (ret)
1129         return ret;
1130 
1131     hwmon = devm_hwmon_device_register_with_info(dev, name, st,
1132                              &ltc2947_chip_info,
1133                              ltc2947_groups);
1134     return PTR_ERR_OR_ZERO(hwmon);
1135 }
1136 EXPORT_SYMBOL_GPL(ltc2947_core_probe);
1137 
1138 static int __maybe_unused ltc2947_resume(struct device *dev)
1139 {
1140     struct ltc2947_data *st = dev_get_drvdata(dev);
1141     u32 ctrl = 0;
1142     int ret;
1143 
1144     /* dummy read to wake the device */
1145     ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl);
1146     if (ret)
1147         return ret;
1148     /*
1149      * Wait for the device. It takes 100ms to wake up so, 10ms extra
1150      * should be enough.
1151      */
1152     msleep(110);
1153     ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl);
1154     if (ret)
1155         return ret;
1156     /* ctrl should be 0 */
1157     if (ctrl != 0) {
1158         dev_err(st->dev, "Device failed to wake up, ctl:%02X\n", ctrl);
1159         return -ETIMEDOUT;
1160     }
1161 
1162     /* set continuous mode */
1163     return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1164                   LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1));
1165 }
1166 
1167 static int __maybe_unused ltc2947_suspend(struct device *dev)
1168 {
1169     struct ltc2947_data *st = dev_get_drvdata(dev);
1170 
1171     return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1172                   LTC2947_SHUTDOWN_MASK, 1);
1173 }
1174 
1175 SIMPLE_DEV_PM_OPS(ltc2947_pm_ops, ltc2947_suspend, ltc2947_resume);
1176 EXPORT_SYMBOL_GPL(ltc2947_pm_ops);
1177 
1178 const struct of_device_id ltc2947_of_match[] = {
1179     { .compatible = "adi,ltc2947" },
1180     {}
1181 };
1182 EXPORT_SYMBOL_GPL(ltc2947_of_match);
1183 MODULE_DEVICE_TABLE(of, ltc2947_of_match);
1184 
1185 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1186 MODULE_DESCRIPTION("LTC2947 power and energy monitor core driver");
1187 MODULE_LICENSE("GPL");
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