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0011 #include <linux/err.h>
0012 #include <linux/init.h>
0013 #include <linux/hwmon.h>
0014 #include <linux/i2c.h>
0015 #include <linux/module.h>
0016 #include <linux/mutex.h>
0017 #include <linux/regmap.h>
0018 #include <linux/slab.h>
0019
0020 static const unsigned short normal_i2c[] = {
0021 0x18, 0x19, 0x29, 0x4c, 0x4d, I2C_CLIENT_END };
0022
0023
0024
0025 #define LM95245_REG_RW_CONFIG1 0x03
0026 #define LM95245_REG_RW_CONVERS_RATE 0x04
0027 #define LM95245_REG_W_ONE_SHOT 0x0F
0028
0029
0030 #define LM95245_REG_RW_CONFIG2 0xBF
0031 #define LM95245_REG_RW_REMOTE_OFFH 0x11
0032 #define LM95245_REG_RW_REMOTE_OFFL 0x12
0033
0034
0035 #define LM95245_REG_R_STATUS1 0x02
0036 #define LM95245_REG_R_STATUS2 0x33
0037
0038
0039 #define LM95245_REG_RW_REMOTE_OS_LIMIT 0x07
0040 #define LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT 0x20
0041 #define LM95245_REG_RW_REMOTE_TCRIT_LIMIT 0x19
0042 #define LM95245_REG_RW_COMMON_HYSTERESIS 0x21
0043
0044
0045 #define LM95245_REG_R_LOCAL_TEMPH_S 0x00
0046 #define LM95245_REG_R_LOCAL_TEMPL_S 0x30
0047 #define LM95245_REG_R_REMOTE_TEMPH_S 0x01
0048 #define LM95245_REG_R_REMOTE_TEMPL_S 0x10
0049
0050 #define LM95245_REG_R_REMOTE_TEMPH_U 0x31
0051 #define LM95245_REG_R_REMOTE_TEMPL_U 0x32
0052
0053
0054 #define LM95245_REG_R_MAN_ID 0xFE
0055 #define LM95245_REG_R_CHIP_ID 0xFF
0056
0057
0058 #define CFG_STOP 0x40
0059 #define CFG_REMOTE_TCRIT_MASK 0x10
0060 #define CFG_REMOTE_OS_MASK 0x08
0061 #define CFG_LOCAL_TCRIT_MASK 0x04
0062 #define CFG_LOCAL_OS_MASK 0x02
0063
0064 #define CFG2_OS_A0 0x40
0065 #define CFG2_DIODE_FAULT_OS 0x20
0066 #define CFG2_DIODE_FAULT_TCRIT 0x10
0067 #define CFG2_REMOTE_TT 0x08
0068 #define CFG2_REMOTE_FILTER_DIS 0x00
0069 #define CFG2_REMOTE_FILTER_EN 0x06
0070
0071
0072 #define RATE_CR0063 0x00
0073 #define RATE_CR0364 0x01
0074 #define RATE_CR1000 0x02
0075 #define RATE_CR2500 0x03
0076
0077 #define STATUS1_ROS 0x10
0078 #define STATUS1_DIODE_FAULT 0x04
0079 #define STATUS1_RTCRIT 0x02
0080 #define STATUS1_LOC 0x01
0081
0082 #define MANUFACTURER_ID 0x01
0083 #define LM95235_REVISION 0xB1
0084 #define LM95245_REVISION 0xB3
0085
0086
0087 struct lm95245_data {
0088 struct regmap *regmap;
0089 struct mutex update_lock;
0090 int interval;
0091 };
0092
0093
0094 static int temp_from_reg_unsigned(u8 val_h, u8 val_l)
0095 {
0096 return val_h * 1000 + val_l * 1000 / 256;
0097 }
0098
0099 static int temp_from_reg_signed(u8 val_h, u8 val_l)
0100 {
0101 if (val_h & 0x80)
0102 return (val_h - 0x100) * 1000;
0103 return temp_from_reg_unsigned(val_h, val_l);
0104 }
0105
0106 static int lm95245_read_conversion_rate(struct lm95245_data *data)
0107 {
0108 unsigned int rate;
0109 int ret;
0110
0111 ret = regmap_read(data->regmap, LM95245_REG_RW_CONVERS_RATE, &rate);
0112 if (ret < 0)
0113 return ret;
0114
0115 switch (rate) {
0116 case RATE_CR0063:
0117 data->interval = 63;
0118 break;
0119 case RATE_CR0364:
0120 data->interval = 364;
0121 break;
0122 case RATE_CR1000:
0123 data->interval = 1000;
0124 break;
0125 case RATE_CR2500:
0126 default:
0127 data->interval = 2500;
0128 break;
0129 }
0130 return 0;
0131 }
0132
0133 static int lm95245_set_conversion_rate(struct lm95245_data *data, long interval)
0134 {
0135 int ret, rate;
0136
0137 if (interval <= 63) {
0138 interval = 63;
0139 rate = RATE_CR0063;
0140 } else if (interval <= 364) {
0141 interval = 364;
0142 rate = RATE_CR0364;
0143 } else if (interval <= 1000) {
0144 interval = 1000;
0145 rate = RATE_CR1000;
0146 } else {
0147 interval = 2500;
0148 rate = RATE_CR2500;
0149 }
0150
0151 ret = regmap_write(data->regmap, LM95245_REG_RW_CONVERS_RATE, rate);
0152 if (ret < 0)
0153 return ret;
0154
0155 data->interval = interval;
0156 return 0;
0157 }
0158
0159 static int lm95245_read_temp(struct device *dev, u32 attr, int channel,
0160 long *val)
0161 {
0162 struct lm95245_data *data = dev_get_drvdata(dev);
0163 struct regmap *regmap = data->regmap;
0164 int ret, regl, regh, regvall, regvalh;
0165
0166 switch (attr) {
0167 case hwmon_temp_input:
0168 regl = channel ? LM95245_REG_R_REMOTE_TEMPL_S :
0169 LM95245_REG_R_LOCAL_TEMPL_S;
0170 regh = channel ? LM95245_REG_R_REMOTE_TEMPH_S :
0171 LM95245_REG_R_LOCAL_TEMPH_S;
0172 ret = regmap_read(regmap, regl, ®vall);
0173 if (ret < 0)
0174 return ret;
0175 ret = regmap_read(regmap, regh, ®valh);
0176 if (ret < 0)
0177 return ret;
0178
0179
0180
0181
0182
0183
0184 if (!channel || (regvalh & 0x80) || regvalh < 0x7f) {
0185 *val = temp_from_reg_signed(regvalh, regvall);
0186 return 0;
0187 }
0188 ret = regmap_read(regmap, LM95245_REG_R_REMOTE_TEMPL_U,
0189 ®vall);
0190 if (ret < 0)
0191 return ret;
0192 ret = regmap_read(regmap, LM95245_REG_R_REMOTE_TEMPH_U,
0193 ®valh);
0194 if (ret < 0)
0195 return ret;
0196 *val = temp_from_reg_unsigned(regvalh, regvall);
0197 return 0;
0198 case hwmon_temp_max:
0199 ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT,
0200 ®valh);
0201 if (ret < 0)
0202 return ret;
0203 *val = regvalh * 1000;
0204 return 0;
0205 case hwmon_temp_crit:
0206 regh = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
0207 LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
0208 ret = regmap_read(regmap, regh, ®valh);
0209 if (ret < 0)
0210 return ret;
0211 *val = regvalh * 1000;
0212 return 0;
0213 case hwmon_temp_max_hyst:
0214 ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT,
0215 ®valh);
0216 if (ret < 0)
0217 return ret;
0218 ret = regmap_read(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
0219 ®vall);
0220 if (ret < 0)
0221 return ret;
0222 *val = (regvalh - regvall) * 1000;
0223 return 0;
0224 case hwmon_temp_crit_hyst:
0225 regh = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
0226 LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
0227 ret = regmap_read(regmap, regh, ®valh);
0228 if (ret < 0)
0229 return ret;
0230 ret = regmap_read(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
0231 ®vall);
0232 if (ret < 0)
0233 return ret;
0234 *val = (regvalh - regvall) * 1000;
0235 return 0;
0236 case hwmon_temp_type:
0237 ret = regmap_read(regmap, LM95245_REG_RW_CONFIG2, ®valh);
0238 if (ret < 0)
0239 return ret;
0240 *val = (regvalh & CFG2_REMOTE_TT) ? 1 : 2;
0241 return 0;
0242 case hwmon_temp_offset:
0243 ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OFFL,
0244 ®vall);
0245 if (ret < 0)
0246 return ret;
0247 ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OFFH,
0248 ®valh);
0249 if (ret < 0)
0250 return ret;
0251 *val = temp_from_reg_signed(regvalh, regvall);
0252 return 0;
0253 case hwmon_temp_max_alarm:
0254 ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
0255 if (ret < 0)
0256 return ret;
0257 *val = !!(regvalh & STATUS1_ROS);
0258 return 0;
0259 case hwmon_temp_crit_alarm:
0260 ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
0261 if (ret < 0)
0262 return ret;
0263 *val = !!(regvalh & (channel ? STATUS1_RTCRIT : STATUS1_LOC));
0264 return 0;
0265 case hwmon_temp_fault:
0266 ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
0267 if (ret < 0)
0268 return ret;
0269 *val = !!(regvalh & STATUS1_DIODE_FAULT);
0270 return 0;
0271 default:
0272 return -EOPNOTSUPP;
0273 }
0274 }
0275
0276 static int lm95245_write_temp(struct device *dev, u32 attr, int channel,
0277 long val)
0278 {
0279 struct lm95245_data *data = dev_get_drvdata(dev);
0280 struct regmap *regmap = data->regmap;
0281 unsigned int regval;
0282 int ret, reg;
0283
0284 switch (attr) {
0285 case hwmon_temp_max:
0286 val = clamp_val(val / 1000, 0, 255);
0287 ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT, val);
0288 return ret;
0289 case hwmon_temp_crit:
0290 reg = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
0291 LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
0292 val = clamp_val(val / 1000, 0, channel ? 255 : 127);
0293 ret = regmap_write(regmap, reg, val);
0294 return ret;
0295 case hwmon_temp_crit_hyst:
0296 mutex_lock(&data->update_lock);
0297 ret = regmap_read(regmap, LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT,
0298 ®val);
0299 if (ret < 0) {
0300 mutex_unlock(&data->update_lock);
0301 return ret;
0302 }
0303
0304 val = clamp_val(val, -1000000, 1000000);
0305 val = regval - val / 1000;
0306 val = clamp_val(val, 0, 31);
0307 ret = regmap_write(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
0308 val);
0309 mutex_unlock(&data->update_lock);
0310 return ret;
0311 case hwmon_temp_offset:
0312 val = clamp_val(val, -128000, 127875);
0313 val = val * 256 / 1000;
0314 mutex_lock(&data->update_lock);
0315 ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OFFL,
0316 val & 0xe0);
0317 if (ret < 0) {
0318 mutex_unlock(&data->update_lock);
0319 return ret;
0320 }
0321 ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OFFH,
0322 (val >> 8) & 0xff);
0323 mutex_unlock(&data->update_lock);
0324 return ret;
0325 case hwmon_temp_type:
0326 if (val != 1 && val != 2)
0327 return -EINVAL;
0328 ret = regmap_update_bits(regmap, LM95245_REG_RW_CONFIG2,
0329 CFG2_REMOTE_TT,
0330 val == 1 ? CFG2_REMOTE_TT : 0);
0331 return ret;
0332 default:
0333 return -EOPNOTSUPP;
0334 }
0335 }
0336
0337 static int lm95245_read_chip(struct device *dev, u32 attr, int channel,
0338 long *val)
0339 {
0340 struct lm95245_data *data = dev_get_drvdata(dev);
0341
0342 switch (attr) {
0343 case hwmon_chip_update_interval:
0344 *val = data->interval;
0345 return 0;
0346 default:
0347 return -EOPNOTSUPP;
0348 }
0349 }
0350
0351 static int lm95245_write_chip(struct device *dev, u32 attr, int channel,
0352 long val)
0353 {
0354 struct lm95245_data *data = dev_get_drvdata(dev);
0355 int ret;
0356
0357 switch (attr) {
0358 case hwmon_chip_update_interval:
0359 mutex_lock(&data->update_lock);
0360 ret = lm95245_set_conversion_rate(data, val);
0361 mutex_unlock(&data->update_lock);
0362 return ret;
0363 default:
0364 return -EOPNOTSUPP;
0365 }
0366 }
0367
0368 static int lm95245_read(struct device *dev, enum hwmon_sensor_types type,
0369 u32 attr, int channel, long *val)
0370 {
0371 switch (type) {
0372 case hwmon_chip:
0373 return lm95245_read_chip(dev, attr, channel, val);
0374 case hwmon_temp:
0375 return lm95245_read_temp(dev, attr, channel, val);
0376 default:
0377 return -EOPNOTSUPP;
0378 }
0379 }
0380
0381 static int lm95245_write(struct device *dev, enum hwmon_sensor_types type,
0382 u32 attr, int channel, long val)
0383 {
0384 switch (type) {
0385 case hwmon_chip:
0386 return lm95245_write_chip(dev, attr, channel, val);
0387 case hwmon_temp:
0388 return lm95245_write_temp(dev, attr, channel, val);
0389 default:
0390 return -EOPNOTSUPP;
0391 }
0392 }
0393
0394 static umode_t lm95245_temp_is_visible(const void *data, u32 attr, int channel)
0395 {
0396 switch (attr) {
0397 case hwmon_temp_input:
0398 case hwmon_temp_max_alarm:
0399 case hwmon_temp_max_hyst:
0400 case hwmon_temp_crit_alarm:
0401 case hwmon_temp_fault:
0402 return 0444;
0403 case hwmon_temp_type:
0404 case hwmon_temp_max:
0405 case hwmon_temp_crit:
0406 case hwmon_temp_offset:
0407 return 0644;
0408 case hwmon_temp_crit_hyst:
0409 return (channel == 0) ? 0644 : 0444;
0410 default:
0411 return 0;
0412 }
0413 }
0414
0415 static umode_t lm95245_is_visible(const void *data,
0416 enum hwmon_sensor_types type,
0417 u32 attr, int channel)
0418 {
0419 switch (type) {
0420 case hwmon_chip:
0421 switch (attr) {
0422 case hwmon_chip_update_interval:
0423 return 0644;
0424 default:
0425 return 0;
0426 }
0427 case hwmon_temp:
0428 return lm95245_temp_is_visible(data, attr, channel);
0429 default:
0430 return 0;
0431 }
0432 }
0433
0434
0435 static int lm95245_detect(struct i2c_client *new_client,
0436 struct i2c_board_info *info)
0437 {
0438 struct i2c_adapter *adapter = new_client->adapter;
0439 int address = new_client->addr;
0440 const char *name;
0441 int rev, id;
0442
0443 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0444 return -ENODEV;
0445
0446 id = i2c_smbus_read_byte_data(new_client, LM95245_REG_R_MAN_ID);
0447 if (id != MANUFACTURER_ID)
0448 return -ENODEV;
0449
0450 rev = i2c_smbus_read_byte_data(new_client, LM95245_REG_R_CHIP_ID);
0451 switch (rev) {
0452 case LM95235_REVISION:
0453 if (address != 0x18 && address != 0x29 && address != 0x4c)
0454 return -ENODEV;
0455 name = "lm95235";
0456 break;
0457 case LM95245_REVISION:
0458 name = "lm95245";
0459 break;
0460 default:
0461 return -ENODEV;
0462 }
0463
0464 strlcpy(info->type, name, I2C_NAME_SIZE);
0465 return 0;
0466 }
0467
0468 static int lm95245_init_client(struct lm95245_data *data)
0469 {
0470 int ret;
0471
0472 ret = lm95245_read_conversion_rate(data);
0473 if (ret < 0)
0474 return ret;
0475
0476 return regmap_update_bits(data->regmap, LM95245_REG_RW_CONFIG1,
0477 CFG_STOP, 0);
0478 }
0479
0480 static bool lm95245_is_writeable_reg(struct device *dev, unsigned int reg)
0481 {
0482 switch (reg) {
0483 case LM95245_REG_RW_CONFIG1:
0484 case LM95245_REG_RW_CONVERS_RATE:
0485 case LM95245_REG_W_ONE_SHOT:
0486 case LM95245_REG_RW_CONFIG2:
0487 case LM95245_REG_RW_REMOTE_OFFH:
0488 case LM95245_REG_RW_REMOTE_OFFL:
0489 case LM95245_REG_RW_REMOTE_OS_LIMIT:
0490 case LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT:
0491 case LM95245_REG_RW_REMOTE_TCRIT_LIMIT:
0492 case LM95245_REG_RW_COMMON_HYSTERESIS:
0493 return true;
0494 default:
0495 return false;
0496 }
0497 }
0498
0499 static bool lm95245_is_volatile_reg(struct device *dev, unsigned int reg)
0500 {
0501 switch (reg) {
0502 case LM95245_REG_R_STATUS1:
0503 case LM95245_REG_R_STATUS2:
0504 case LM95245_REG_R_LOCAL_TEMPH_S:
0505 case LM95245_REG_R_LOCAL_TEMPL_S:
0506 case LM95245_REG_R_REMOTE_TEMPH_S:
0507 case LM95245_REG_R_REMOTE_TEMPL_S:
0508 case LM95245_REG_R_REMOTE_TEMPH_U:
0509 case LM95245_REG_R_REMOTE_TEMPL_U:
0510 return true;
0511 default:
0512 return false;
0513 }
0514 }
0515
0516 static const struct regmap_config lm95245_regmap_config = {
0517 .reg_bits = 8,
0518 .val_bits = 8,
0519 .writeable_reg = lm95245_is_writeable_reg,
0520 .volatile_reg = lm95245_is_volatile_reg,
0521 .cache_type = REGCACHE_RBTREE,
0522 .use_single_read = true,
0523 .use_single_write = true,
0524 };
0525
0526 static const struct hwmon_channel_info *lm95245_info[] = {
0527 HWMON_CHANNEL_INFO(chip,
0528 HWMON_C_UPDATE_INTERVAL),
0529 HWMON_CHANNEL_INFO(temp,
0530 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_HYST |
0531 HWMON_T_CRIT_ALARM,
0532 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
0533 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_FAULT |
0534 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM |
0535 HWMON_T_TYPE | HWMON_T_OFFSET),
0536 NULL
0537 };
0538
0539 static const struct hwmon_ops lm95245_hwmon_ops = {
0540 .is_visible = lm95245_is_visible,
0541 .read = lm95245_read,
0542 .write = lm95245_write,
0543 };
0544
0545 static const struct hwmon_chip_info lm95245_chip_info = {
0546 .ops = &lm95245_hwmon_ops,
0547 .info = lm95245_info,
0548 };
0549
0550 static int lm95245_probe(struct i2c_client *client)
0551 {
0552 struct device *dev = &client->dev;
0553 struct lm95245_data *data;
0554 struct device *hwmon_dev;
0555 int ret;
0556
0557 data = devm_kzalloc(dev, sizeof(struct lm95245_data), GFP_KERNEL);
0558 if (!data)
0559 return -ENOMEM;
0560
0561 data->regmap = devm_regmap_init_i2c(client, &lm95245_regmap_config);
0562 if (IS_ERR(data->regmap))
0563 return PTR_ERR(data->regmap);
0564
0565 mutex_init(&data->update_lock);
0566
0567
0568 ret = lm95245_init_client(data);
0569 if (ret < 0)
0570 return ret;
0571
0572 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
0573 data,
0574 &lm95245_chip_info,
0575 NULL);
0576 return PTR_ERR_OR_ZERO(hwmon_dev);
0577 }
0578
0579
0580 static const struct i2c_device_id lm95245_id[] = {
0581 { "lm95235", 0 },
0582 { "lm95245", 0 },
0583 { }
0584 };
0585 MODULE_DEVICE_TABLE(i2c, lm95245_id);
0586
0587 static const struct of_device_id __maybe_unused lm95245_of_match[] = {
0588 { .compatible = "national,lm95235" },
0589 { .compatible = "national,lm95245" },
0590 { },
0591 };
0592 MODULE_DEVICE_TABLE(of, lm95245_of_match);
0593
0594 static struct i2c_driver lm95245_driver = {
0595 .class = I2C_CLASS_HWMON,
0596 .driver = {
0597 .name = "lm95245",
0598 .of_match_table = of_match_ptr(lm95245_of_match),
0599 },
0600 .probe_new = lm95245_probe,
0601 .id_table = lm95245_id,
0602 .detect = lm95245_detect,
0603 .address_list = normal_i2c,
0604 };
0605
0606 module_i2c_driver(lm95245_driver);
0607
0608 MODULE_AUTHOR("Alexander Stein <alexander.stein@systec-electronic.com>");
0609 MODULE_DESCRIPTION("LM95235/LM95245 sensor driver");
0610 MODULE_LICENSE("GPL");