drivers/hwmon/jc42.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
0004  *
0005  * Copyright (c) 2010  Ericsson AB.
0006  *
0007  * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
0008  *
0009  * JC42.4 compliant temperature sensors are typically used on memory modules.
0010  */
0011
0012 #include <linux/bitops.h>
0013 #include <linux/module.h>
0014 #include <linux/init.h>
0015 #include <linux/slab.h>
0016 #include <linux/jiffies.h>
0017 #include <linux/i2c.h>
0018 #include <linux/hwmon.h>
0019 #include <linux/err.h>
0020 #include <linux/mutex.h>
0021 #include <linux/of.h>
0022
0023 /* Addresses to scan */
0024 static const unsigned short normal_i2c[] = {
0025     0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
0026
0027 /* JC42 registers. All registers are 16 bit. */
0028 #define JC42_REG_CAP        0x00
0029 #define JC42_REG_CONFIG     0x01
0030 #define JC42_REG_TEMP_UPPER 0x02
0031 #define JC42_REG_TEMP_LOWER 0x03
0032 #define JC42_REG_TEMP_CRITICAL  0x04
0033 #define JC42_REG_TEMP       0x05
0034 #define JC42_REG_MANID      0x06
0035 #define JC42_REG_DEVICEID   0x07
0036 #define JC42_REG_SMBUS      0x22 /* NXP and Atmel, possibly others? */
0037
0038 /* Status bits in temperature register */
0039 #define JC42_ALARM_CRIT_BIT 15
0040 #define JC42_ALARM_MAX_BIT  14
0041 #define JC42_ALARM_MIN_BIT  13
0042
0043 /* Configuration register defines */
0044 #define JC42_CFG_CRIT_ONLY  (1 << 2)
0045 #define JC42_CFG_TCRIT_LOCK (1 << 6)
0046 #define JC42_CFG_EVENT_LOCK (1 << 7)
0047 #define JC42_CFG_SHUTDOWN   (1 << 8)
0048 #define JC42_CFG_HYST_SHIFT 9
0049 #define JC42_CFG_HYST_MASK  (0x03 << 9)
0050
0051 /* Capabilities */
0052 #define JC42_CAP_RANGE      (1 << 2)
0053
0054 /* Manufacturer IDs */
0055 #define ADT_MANID       0x11d4  /* Analog Devices */
0056 #define ATMEL_MANID     0x001f  /* Atmel */
0057 #define ATMEL_MANID2        0x1114  /* Atmel */
0058 #define MAX_MANID       0x004d  /* Maxim */
0059 #define IDT_MANID       0x00b3  /* IDT */
0060 #define MCP_MANID       0x0054  /* Microchip */
0061 #define NXP_MANID       0x1131  /* NXP Semiconductors */
0062 #define ONS_MANID       0x1b09  /* ON Semiconductor */
0063 #define STM_MANID       0x104a  /* ST Microelectronics */
0064 #define GT_MANID        0x1c68  /* Giantec */
0065 #define GT_MANID2       0x132d  /* Giantec, 2nd mfg ID */
0066 #define SI_MANID        0x1c85  /* Seiko Instruments */
0067
0068 /* SMBUS register */
0069 #define SMBUS_STMOUT        BIT(7)  /* SMBus time-out, active low */
0070
0071 /* Supported chips */
0072
0073 /* Analog Devices */
0074 #define ADT7408_DEVID       0x0801
0075 #define ADT7408_DEVID_MASK  0xffff
0076
0077 /* Atmel */
0078 #define AT30TS00_DEVID      0x8201
0079 #define AT30TS00_DEVID_MASK 0xffff
0080
0081 #define AT30TSE004_DEVID    0x2200
0082 #define AT30TSE004_DEVID_MASK   0xffff
0083
0084 /* Giantec */
0085 #define GT30TS00_DEVID      0x2200
0086 #define GT30TS00_DEVID_MASK 0xff00
0087
0088 #define GT34TS02_DEVID      0x3300
0089 #define GT34TS02_DEVID_MASK 0xff00
0090
0091 /* IDT */
0092 #define TSE2004_DEVID       0x2200
0093 #define TSE2004_DEVID_MASK  0xff00
0094
0095 #define TS3000_DEVID        0x2900  /* Also matches TSE2002 */
0096 #define TS3000_DEVID_MASK   0xff00
0097
0098 #define TS3001_DEVID        0x3000
0099 #define TS3001_DEVID_MASK   0xff00
0100
0101 /* Maxim */
0102 #define MAX6604_DEVID       0x3e00
0103 #define MAX6604_DEVID_MASK  0xffff
0104
0105 /* Microchip */
0106 #define MCP9804_DEVID       0x0200
0107 #define MCP9804_DEVID_MASK  0xfffc
0108
0109 #define MCP9808_DEVID       0x0400
0110 #define MCP9808_DEVID_MASK  0xfffc
0111
0112 #define MCP98242_DEVID      0x2000
0113 #define MCP98242_DEVID_MASK 0xfffc
0114
0115 #define MCP98243_DEVID      0x2100
0116 #define MCP98243_DEVID_MASK 0xfffc
0117
0118 #define MCP98244_DEVID      0x2200
0119 #define MCP98244_DEVID_MASK 0xfffc
0120
0121 #define MCP9843_DEVID       0x0000  /* Also matches mcp9805 */
0122 #define MCP9843_DEVID_MASK  0xfffe
0123
0124 /* NXP */
0125 #define SE97_DEVID      0xa200
0126 #define SE97_DEVID_MASK     0xfffc
0127
0128 #define SE98_DEVID      0xa100
0129 #define SE98_DEVID_MASK     0xfffc
0130
0131 /* ON Semiconductor */
0132 #define CAT6095_DEVID       0x0800  /* Also matches CAT34TS02 */
0133 #define CAT6095_DEVID_MASK  0xffe0
0134
0135 #define CAT34TS02C_DEVID    0x0a00
0136 #define CAT34TS02C_DEVID_MASK   0xfff0
0137
0138 #define CAT34TS04_DEVID     0x2200
0139 #define CAT34TS04_DEVID_MASK    0xfff0
0140
0141 #define N34TS04_DEVID       0x2230
0142 #define N34TS04_DEVID_MASK  0xfff0
0143
0144 /* ST Microelectronics */
0145 #define STTS424_DEVID       0x0101
0146 #define STTS424_DEVID_MASK  0xffff
0147
0148 #define STTS424E_DEVID      0x0000
0149 #define STTS424E_DEVID_MASK 0xfffe
0150
0151 #define STTS2002_DEVID      0x0300
0152 #define STTS2002_DEVID_MASK 0xffff
0153
0154 #define STTS2004_DEVID      0x2201
0155 #define STTS2004_DEVID_MASK 0xffff
0156
0157 #define STTS3000_DEVID      0x0200
0158 #define STTS3000_DEVID_MASK 0xffff
0159
0160 /* Seiko Instruments */
0161 #define S34TS04A_DEVID      0x2221
0162 #define S34TS04A_DEVID_MASK 0xffff
0163
0164 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
0165
0166 struct jc42_chips {
0167     u16 manid;
0168     u16 devid;
0169     u16 devid_mask;
0170 };
0171
0172 static struct jc42_chips jc42_chips[] = {
0173     { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
0174     { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
0175     { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
0176     { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
0177     { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
0178     { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
0179     { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
0180     { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
0181     { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
0182     { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
0183     { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
0184     { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
0185     { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
0186     { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
0187     { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
0188     { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
0189     { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
0190     { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
0191     { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
0192     { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
0193     { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
0194     { SI_MANID,  S34TS04A_DEVID, S34TS04A_DEVID_MASK },
0195     { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
0196     { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
0197     { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
0198     { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
0199     { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
0200 };
0201
0202 enum temp_index {
0203     t_input = 0,
0204     t_crit,
0205     t_min,
0206     t_max,
0207     t_num_temp
0208 };
0209
0210 static const u8 temp_regs[t_num_temp] = {
0211     [t_input] = JC42_REG_TEMP,
0212     [t_crit] = JC42_REG_TEMP_CRITICAL,
0213     [t_min] = JC42_REG_TEMP_LOWER,
0214     [t_max] = JC42_REG_TEMP_UPPER,
0215 };
0216
0217 /* Each client has this additional data */
0218 struct jc42_data {
0219     struct i2c_client *client;
0220     struct mutex    update_lock;    /* protect register access */
0221     bool        extended;   /* true if extended range supported */
0222     bool        valid;
0223     unsigned long   last_updated;   /* In jiffies */
0224     u16     orig_config;    /* original configuration */
0225     u16     config;     /* current configuration */
0226     u16     temp[t_num_temp];/* Temperatures */
0227 };
0228
0229 #define JC42_TEMP_MIN_EXTENDED  (-40000)
0230 #define JC42_TEMP_MIN       0
0231 #define JC42_TEMP_MAX       125000
0232
0233 static u16 jc42_temp_to_reg(long temp, bool extended)
0234 {
0235     int ntemp = clamp_val(temp,
0236                   extended ? JC42_TEMP_MIN_EXTENDED :
0237                   JC42_TEMP_MIN, JC42_TEMP_MAX);
0238
0239     /* convert from 0.001 to 0.0625 resolution */
0240     return (ntemp * 2 / 125) & 0x1fff;
0241 }
0242
0243 static int jc42_temp_from_reg(s16 reg)
0244 {
0245     reg = sign_extend32(reg, 12);
0246
0247     /* convert from 0.0625 to 0.001 resolution */
0248     return reg * 125 / 2;
0249 }
0250
0251 static struct jc42_data *jc42_update_device(struct device *dev)
0252 {
0253     struct jc42_data *data = dev_get_drvdata(dev);
0254     struct i2c_client *client = data->client;
0255     struct jc42_data *ret = data;
0256     int i, val;
0257
0258     mutex_lock(&data->update_lock);
0259
0260     if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
0261         for (i = 0; i < t_num_temp; i++) {
0262             val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
0263             if (val < 0) {
0264                 ret = ERR_PTR(val);
0265                 goto abort;
0266             }
0267             data->temp[i] = val;
0268         }
0269         data->last_updated = jiffies;
0270         data->valid = true;
0271     }
0272 abort:
0273     mutex_unlock(&data->update_lock);
0274     return ret;
0275 }
0276
0277 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
0278              u32 attr, int channel, long *val)
0279 {
0280     struct jc42_data *data = jc42_update_device(dev);
0281     int temp, hyst;
0282
0283     if (IS_ERR(data))
0284         return PTR_ERR(data);
0285
0286     switch (attr) {
0287     case hwmon_temp_input:
0288         *val = jc42_temp_from_reg(data->temp[t_input]);
0289         return 0;
0290     case hwmon_temp_min:
0291         *val = jc42_temp_from_reg(data->temp[t_min]);
0292         return 0;
0293     case hwmon_temp_max:
0294         *val = jc42_temp_from_reg(data->temp[t_max]);
0295         return 0;
0296     case hwmon_temp_crit:
0297         *val = jc42_temp_from_reg(data->temp[t_crit]);
0298         return 0;
0299     case hwmon_temp_max_hyst:
0300         temp = jc42_temp_from_reg(data->temp[t_max]);
0301         hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
0302                         >> JC42_CFG_HYST_SHIFT];
0303         *val = temp - hyst;
0304         return 0;
0305     case hwmon_temp_crit_hyst:
0306         temp = jc42_temp_from_reg(data->temp[t_crit]);
0307         hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
0308                         >> JC42_CFG_HYST_SHIFT];
0309         *val = temp - hyst;
0310         return 0;
0311     case hwmon_temp_min_alarm:
0312         *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
0313         return 0;
0314     case hwmon_temp_max_alarm:
0315         *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
0316         return 0;
0317     case hwmon_temp_crit_alarm:
0318         *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
0319         return 0;
0320     default:
0321         return -EOPNOTSUPP;
0322     }
0323 }
0324
0325 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
0326               u32 attr, int channel, long val)
0327 {
0328     struct jc42_data *data = dev_get_drvdata(dev);
0329     struct i2c_client *client = data->client;
0330     int diff, hyst;
0331     int ret;
0332
0333     mutex_lock(&data->update_lock);
0334
0335     switch (attr) {
0336     case hwmon_temp_min:
0337         data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
0338         ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
0339                            data->temp[t_min]);
0340         break;
0341     case hwmon_temp_max:
0342         data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
0343         ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
0344                            data->temp[t_max]);
0345         break;
0346     case hwmon_temp_crit:
0347         data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
0348         ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
0349                            data->temp[t_crit]);
0350         break;
0351     case hwmon_temp_crit_hyst:
0352         /*
0353          * JC42.4 compliant chips only support four hysteresis values.
0354          * Pick best choice and go from there.
0355          */
0356         val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
0357                              : JC42_TEMP_MIN) - 6000,
0358                 JC42_TEMP_MAX);
0359         diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
0360         hyst = 0;
0361         if (diff > 0) {
0362             if (diff < 2250)
0363                 hyst = 1;   /* 1.5 degrees C */
0364             else if (diff < 4500)
0365                 hyst = 2;   /* 3.0 degrees C */
0366             else
0367                 hyst = 3;   /* 6.0 degrees C */
0368         }
0369         data->config = (data->config & ~JC42_CFG_HYST_MASK) |
0370                 (hyst << JC42_CFG_HYST_SHIFT);
0371         ret = i2c_smbus_write_word_swapped(data->client,
0372                            JC42_REG_CONFIG,
0373                            data->config);
0374         break;
0375     default:
0376         ret = -EOPNOTSUPP;
0377         break;
0378     }
0379
0380     mutex_unlock(&data->update_lock);
0381
0382     return ret;
0383 }
0384
0385 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
0386                    u32 attr, int channel)
0387 {
0388     const struct jc42_data *data = _data;
0389     unsigned int config = data->config;
0390     umode_t mode = 0444;
0391
0392     switch (attr) {
0393     case hwmon_temp_min:
0394     case hwmon_temp_max:
0395         if (!(config & JC42_CFG_EVENT_LOCK))
0396             mode |= 0200;
0397         break;
0398     case hwmon_temp_crit:
0399         if (!(config & JC42_CFG_TCRIT_LOCK))
0400             mode |= 0200;
0401         break;
0402     case hwmon_temp_crit_hyst:
0403         if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
0404             mode |= 0200;
0405         break;
0406     case hwmon_temp_input:
0407     case hwmon_temp_max_hyst:
0408     case hwmon_temp_min_alarm:
0409     case hwmon_temp_max_alarm:
0410     case hwmon_temp_crit_alarm:
0411         break;
0412     default:
0413         mode = 0;
0414         break;
0415     }
0416     return mode;
0417 }
0418
0419 /* Return 0 if detection is successful, -ENODEV otherwise */
0420 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
0421 {
0422     struct i2c_adapter *adapter = client->adapter;
0423     int i, config, cap, manid, devid;
0424
0425     if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
0426                      I2C_FUNC_SMBUS_WORD_DATA))
0427         return -ENODEV;
0428
0429     cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
0430     config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
0431     manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
0432     devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
0433
0434     if (cap < 0 || config < 0 || manid < 0 || devid < 0)
0435         return -ENODEV;
0436
0437     if ((cap & 0xff00) || (config & 0xf800))
0438         return -ENODEV;
0439
0440     for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
0441         struct jc42_chips *chip = &jc42_chips[i];
0442         if (manid == chip->manid &&
0443             (devid & chip->devid_mask) == chip->devid) {
0444             strlcpy(info->type, "jc42", I2C_NAME_SIZE);
0445             return 0;
0446         }
0447     }
0448     return -ENODEV;
0449 }
0450
0451 static const struct hwmon_channel_info *jc42_info[] = {
0452     HWMON_CHANNEL_INFO(chip,
0453                HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
0454     HWMON_CHANNEL_INFO(temp,
0455                HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
0456                HWMON_T_CRIT | HWMON_T_MAX_HYST |
0457                HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
0458                HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
0459     NULL
0460 };
0461
0462 static const struct hwmon_ops jc42_hwmon_ops = {
0463     .is_visible = jc42_is_visible,
0464     .read = jc42_read,
0465     .write = jc42_write,
0466 };
0467
0468 static const struct hwmon_chip_info jc42_chip_info = {
0469     .ops = &jc42_hwmon_ops,
0470     .info = jc42_info,
0471 };
0472
0473 static int jc42_probe(struct i2c_client *client)
0474 {
0475     struct device *dev = &client->dev;
0476     struct device *hwmon_dev;
0477     struct jc42_data *data;
0478     int config, cap;
0479
0480     data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
0481     if (!data)
0482         return -ENOMEM;
0483
0484     data->client = client;
0485     i2c_set_clientdata(client, data);
0486     mutex_init(&data->update_lock);
0487
0488     cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
0489     if (cap < 0)
0490         return cap;
0491
0492     data->extended = !!(cap & JC42_CAP_RANGE);
0493
0494     if (device_property_read_bool(dev, "smbus-timeout-disable")) {
0495         int smbus;
0496
0497         /*
0498          * Not all chips support this register, but from a
0499          * quick read of various datasheets no chip appears
0500          * incompatible with the below attempt to disable
0501          * the timeout. And the whole thing is opt-in...
0502          */
0503         smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
0504         if (smbus < 0)
0505             return smbus;
0506         i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
0507                          smbus | SMBUS_STMOUT);
0508     }
0509
0510     config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
0511     if (config < 0)
0512         return config;
0513
0514     data->orig_config = config;
0515     if (config & JC42_CFG_SHUTDOWN) {
0516         config &= ~JC42_CFG_SHUTDOWN;
0517         i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
0518     }
0519     data->config = config;
0520
0521     hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
0522                              data, &jc42_chip_info,
0523                              NULL);
0524     return PTR_ERR_OR_ZERO(hwmon_dev);
0525 }
0526
0527 static int jc42_remove(struct i2c_client *client)
0528 {
0529     struct jc42_data *data = i2c_get_clientdata(client);
0530
0531     /* Restore original configuration except hysteresis */
0532     if ((data->config & ~JC42_CFG_HYST_MASK) !=
0533         (data->orig_config & ~JC42_CFG_HYST_MASK)) {
0534         int config;
0535
0536         config = (data->orig_config & ~JC42_CFG_HYST_MASK)
0537           | (data->config & JC42_CFG_HYST_MASK);
0538         i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
0539     }
0540     return 0;
0541 }
0542
0543 #ifdef CONFIG_PM
0544
0545 static int jc42_suspend(struct device *dev)
0546 {
0547     struct jc42_data *data = dev_get_drvdata(dev);
0548
0549     data->config |= JC42_CFG_SHUTDOWN;
0550     i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
0551                      data->config);
0552     return 0;
0553 }
0554
0555 static int jc42_resume(struct device *dev)
0556 {
0557     struct jc42_data *data = dev_get_drvdata(dev);
0558
0559     data->config &= ~JC42_CFG_SHUTDOWN;
0560     i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
0561                      data->config);
0562     return 0;
0563 }
0564
0565 static const struct dev_pm_ops jc42_dev_pm_ops = {
0566     .suspend = jc42_suspend,
0567     .resume = jc42_resume,
0568 };
0569
0570 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
0571 #else
0572 #define JC42_DEV_PM_OPS NULL
0573 #endif /* CONFIG_PM */
0574
0575 static const struct i2c_device_id jc42_id[] = {
0576     { "jc42", 0 },
0577     { }
0578 };
0579 MODULE_DEVICE_TABLE(i2c, jc42_id);
0580
0581 #ifdef CONFIG_OF
0582 static const struct of_device_id jc42_of_ids[] = {
0583     { .compatible = "jedec,jc-42.4-temp", },
0584     { }
0585 };
0586 MODULE_DEVICE_TABLE(of, jc42_of_ids);
0587 #endif
0588
0589 static struct i2c_driver jc42_driver = {
0590     .class      = I2C_CLASS_SPD | I2C_CLASS_HWMON,
0591     .driver = {
0592         .name   = "jc42",
0593         .pm = JC42_DEV_PM_OPS,
0594         .of_match_table = of_match_ptr(jc42_of_ids),
0595     },
0596     .probe_new  = jc42_probe,
0597     .remove     = jc42_remove,
0598     .id_table   = jc42_id,
0599     .detect     = jc42_detect,
0600     .address_list   = normal_i2c,
0601 };
0602
0603 module_i2c_driver(jc42_driver);
0604
0605 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
0606 MODULE_DESCRIPTION("JC42 driver");
0607 MODULE_LICENSE("GPL");