drivers/hwmon/fam15h_power.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * fam15h_power.c - AMD Family 15h processor power monitoring
0004  *
0005  * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
0006  * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
0007  */
0008
0009 #include <linux/err.h>
0010 #include <linux/hwmon.h>
0011 #include <linux/hwmon-sysfs.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/pci.h>
0015 #include <linux/bitops.h>
0016 #include <linux/cpu.h>
0017 #include <linux/cpumask.h>
0018 #include <linux/time.h>
0019 #include <linux/sched.h>
0020 #include <asm/processor.h>
0021 #include <asm/msr.h>
0022
0023 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
0024 MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
0025 MODULE_LICENSE("GPL");
0026
0027 /* D18F3 */
0028 #define REG_NORTHBRIDGE_CAP     0xe8
0029
0030 /* D18F4 */
0031 #define REG_PROCESSOR_TDP       0x1b8
0032
0033 /* D18F5 */
0034 #define REG_TDP_RUNNING_AVERAGE     0xe0
0035 #define REG_TDP_LIMIT3          0xe8
0036
0037 #define FAM15H_MIN_NUM_ATTRS        2
0038 #define FAM15H_NUM_GROUPS       2
0039 #define MAX_CUS             8
0040
0041 /* set maximum interval as 1 second */
0042 #define MAX_INTERVAL            1000
0043
0044 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
0045
0046 struct fam15h_power_data {
0047     struct pci_dev *pdev;
0048     unsigned int tdp_to_watts;
0049     unsigned int base_tdp;
0050     unsigned int processor_pwr_watts;
0051     unsigned int cpu_pwr_sample_ratio;
0052     const struct attribute_group *groups[FAM15H_NUM_GROUPS];
0053     struct attribute_group group;
0054     /* maximum accumulated power of a compute unit */
0055     u64 max_cu_acc_power;
0056     /* accumulated power of the compute units */
0057     u64 cu_acc_power[MAX_CUS];
0058     /* performance timestamp counter */
0059     u64 cpu_sw_pwr_ptsc[MAX_CUS];
0060     /* online/offline status of current compute unit */
0061     int cu_on[MAX_CUS];
0062     unsigned long power_period;
0063 };
0064
0065 static bool is_carrizo_or_later(void)
0066 {
0067     return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
0068 }
0069
0070 static ssize_t power1_input_show(struct device *dev,
0071                  struct device_attribute *attr, char *buf)
0072 {
0073     u32 val, tdp_limit, running_avg_range;
0074     s32 running_avg_capture;
0075     u64 curr_pwr_watts;
0076     struct fam15h_power_data *data = dev_get_drvdata(dev);
0077     struct pci_dev *f4 = data->pdev;
0078
0079     pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
0080                   REG_TDP_RUNNING_AVERAGE, &val);
0081
0082     /*
0083      * On Carrizo and later platforms, TdpRunAvgAccCap bit field
0084      * is extended to 4:31 from 4:25.
0085      */
0086     if (is_carrizo_or_later()) {
0087         running_avg_capture = val >> 4;
0088         running_avg_capture = sign_extend32(running_avg_capture, 27);
0089     } else {
0090         running_avg_capture = (val >> 4) & 0x3fffff;
0091         running_avg_capture = sign_extend32(running_avg_capture, 21);
0092     }
0093
0094     running_avg_range = (val & 0xf) + 1;
0095
0096     pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
0097                   REG_TDP_LIMIT3, &val);
0098
0099     /*
0100      * On Carrizo and later platforms, ApmTdpLimit bit field
0101      * is extended to 16:31 from 16:28.
0102      */
0103     if (is_carrizo_or_later())
0104         tdp_limit = val >> 16;
0105     else
0106         tdp_limit = (val >> 16) & 0x1fff;
0107
0108     curr_pwr_watts = ((u64)(tdp_limit +
0109                 data->base_tdp)) << running_avg_range;
0110     curr_pwr_watts -= running_avg_capture;
0111     curr_pwr_watts *= data->tdp_to_watts;
0112
0113     /*
0114      * Convert to microWatt
0115      *
0116      * power is in Watt provided as fixed point integer with
0117      * scaling factor 1/(2^16).  For conversion we use
0118      * (10^6)/(2^16) = 15625/(2^10)
0119      */
0120     curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
0121     return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
0122 }
0123 static DEVICE_ATTR_RO(power1_input);
0124
0125 static ssize_t power1_crit_show(struct device *dev,
0126                 struct device_attribute *attr, char *buf)
0127 {
0128     struct fam15h_power_data *data = dev_get_drvdata(dev);
0129
0130     return sprintf(buf, "%u\n", data->processor_pwr_watts);
0131 }
0132 static DEVICE_ATTR_RO(power1_crit);
0133
0134 static void do_read_registers_on_cu(void *_data)
0135 {
0136     struct fam15h_power_data *data = _data;
0137     int cpu, cu;
0138
0139     cpu = smp_processor_id();
0140
0141     /*
0142      * With the new x86 topology modelling, cpu core id actually
0143      * is compute unit id.
0144      */
0145     cu = cpu_data(cpu).cpu_core_id;
0146
0147     rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
0148     rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
0149
0150     data->cu_on[cu] = 1;
0151 }
0152
0153 /*
0154  * This function is only able to be called when CPUID
0155  * Fn8000_0007:EDX[12] is set.
0156  */
0157 static int read_registers(struct fam15h_power_data *data)
0158 {
0159     int core, this_core;
0160     cpumask_var_t mask;
0161     int ret, cpu;
0162
0163     ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
0164     if (!ret)
0165         return -ENOMEM;
0166
0167     memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
0168
0169     cpus_read_lock();
0170
0171     /*
0172      * Choose the first online core of each compute unit, and then
0173      * read their MSR value of power and ptsc in a single IPI,
0174      * because the MSR value of CPU core represent the compute
0175      * unit's.
0176      */
0177     core = -1;
0178
0179     for_each_online_cpu(cpu) {
0180         this_core = topology_core_id(cpu);
0181
0182         if (this_core == core)
0183             continue;
0184
0185         core = this_core;
0186
0187         /* get any CPU on this compute unit */
0188         cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
0189     }
0190
0191     on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
0192
0193     cpus_read_unlock();
0194     free_cpumask_var(mask);
0195
0196     return 0;
0197 }
0198
0199 static ssize_t power1_average_show(struct device *dev,
0200                    struct device_attribute *attr, char *buf)
0201 {
0202     struct fam15h_power_data *data = dev_get_drvdata(dev);
0203     u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
0204         jdelta[MAX_CUS];
0205     u64 tdelta, avg_acc;
0206     int cu, cu_num, ret;
0207     signed long leftover;
0208
0209     /*
0210      * With the new x86 topology modelling, x86_max_cores is the
0211      * compute unit number.
0212      */
0213     cu_num = boot_cpu_data.x86_max_cores;
0214
0215     ret = read_registers(data);
0216     if (ret)
0217         return 0;
0218
0219     for (cu = 0; cu < cu_num; cu++) {
0220         prev_cu_acc_power[cu] = data->cu_acc_power[cu];
0221         prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
0222     }
0223
0224     leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
0225     if (leftover)
0226         return 0;
0227
0228     ret = read_registers(data);
0229     if (ret)
0230         return 0;
0231
0232     for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
0233         /* check if current compute unit is online */
0234         if (data->cu_on[cu] == 0)
0235             continue;
0236
0237         if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
0238             jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
0239             jdelta[cu] -= prev_cu_acc_power[cu];
0240         } else {
0241             jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
0242         }
0243         tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
0244         jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
0245         do_div(jdelta[cu], tdelta);
0246
0247         /* the unit is microWatt */
0248         avg_acc += jdelta[cu];
0249     }
0250
0251     return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
0252 }
0253 static DEVICE_ATTR_RO(power1_average);
0254
0255 static ssize_t power1_average_interval_show(struct device *dev,
0256                         struct device_attribute *attr,
0257                         char *buf)
0258 {
0259     struct fam15h_power_data *data = dev_get_drvdata(dev);
0260
0261     return sprintf(buf, "%lu\n", data->power_period);
0262 }
0263
0264 static ssize_t power1_average_interval_store(struct device *dev,
0265                          struct device_attribute *attr,
0266                          const char *buf, size_t count)
0267 {
0268     struct fam15h_power_data *data = dev_get_drvdata(dev);
0269     unsigned long temp;
0270     int ret;
0271
0272     ret = kstrtoul(buf, 10, &temp);
0273     if (ret)
0274         return ret;
0275
0276     if (temp > MAX_INTERVAL)
0277         return -EINVAL;
0278
0279     /* the interval value should be greater than 0 */
0280     if (temp <= 0)
0281         return -EINVAL;
0282
0283     data->power_period = temp;
0284
0285     return count;
0286 }
0287 static DEVICE_ATTR_RW(power1_average_interval);
0288
0289 static int fam15h_power_init_attrs(struct pci_dev *pdev,
0290                    struct fam15h_power_data *data)
0291 {
0292     int n = FAM15H_MIN_NUM_ATTRS;
0293     struct attribute **fam15h_power_attrs;
0294     struct cpuinfo_x86 *c = &boot_cpu_data;
0295
0296     if (c->x86 == 0x15 &&
0297         (c->x86_model <= 0xf ||
0298          (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
0299         n += 1;
0300
0301     /* check if processor supports accumulated power */
0302     if (boot_cpu_has(X86_FEATURE_ACC_POWER))
0303         n += 2;
0304
0305     fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
0306                       sizeof(*fam15h_power_attrs),
0307                       GFP_KERNEL);
0308
0309     if (!fam15h_power_attrs)
0310         return -ENOMEM;
0311
0312     n = 0;
0313     fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
0314     if (c->x86 == 0x15 &&
0315         (c->x86_model <= 0xf ||
0316          (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
0317         fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
0318
0319     if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
0320         fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
0321         fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
0322     }
0323
0324     data->group.attrs = fam15h_power_attrs;
0325
0326     return 0;
0327 }
0328
0329 static bool should_load_on_this_node(struct pci_dev *f4)
0330 {
0331     u32 val;
0332
0333     pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
0334                   REG_NORTHBRIDGE_CAP, &val);
0335     if ((val & BIT(29)) && ((val >> 30) & 3))
0336         return false;
0337
0338     return true;
0339 }
0340
0341 /*
0342  * Newer BKDG versions have an updated recommendation on how to properly
0343  * initialize the running average range (was: 0xE, now: 0x9). This avoids
0344  * counter saturations resulting in bogus power readings.
0345  * We correct this value ourselves to cope with older BIOSes.
0346  */
0347 static const struct pci_device_id affected_device[] = {
0348     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
0349     { 0 }
0350 };
0351
0352 static void tweak_runavg_range(struct pci_dev *pdev)
0353 {
0354     u32 val;
0355
0356     /*
0357      * let this quirk apply only to the current version of the
0358      * northbridge, since future versions may change the behavior
0359      */
0360     if (!pci_match_id(affected_device, pdev))
0361         return;
0362
0363     pci_bus_read_config_dword(pdev->bus,
0364         PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
0365         REG_TDP_RUNNING_AVERAGE, &val);
0366     if ((val & 0xf) != 0xe)
0367         return;
0368
0369     val &= ~0xf;
0370     val |=  0x9;
0371     pci_bus_write_config_dword(pdev->bus,
0372         PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
0373         REG_TDP_RUNNING_AVERAGE, val);
0374 }
0375
0376 #ifdef CONFIG_PM
0377 static int fam15h_power_resume(struct pci_dev *pdev)
0378 {
0379     tweak_runavg_range(pdev);
0380     return 0;
0381 }
0382 #else
0383 #define fam15h_power_resume NULL
0384 #endif
0385
0386 static int fam15h_power_init_data(struct pci_dev *f4,
0387                   struct fam15h_power_data *data)
0388 {
0389     u32 val;
0390     u64 tmp;
0391     int ret;
0392
0393     pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
0394     data->base_tdp = val >> 16;
0395     tmp = val & 0xffff;
0396
0397     pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
0398                   REG_TDP_LIMIT3, &val);
0399
0400     data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
0401     tmp *= data->tdp_to_watts;
0402
0403     /* result not allowed to be >= 256W */
0404     if ((tmp >> 16) >= 256)
0405         dev_warn(&f4->dev,
0406              "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
0407              (unsigned int) (tmp >> 16));
0408
0409     /* convert to microWatt */
0410     data->processor_pwr_watts = (tmp * 15625) >> 10;
0411
0412     ret = fam15h_power_init_attrs(f4, data);
0413     if (ret)
0414         return ret;
0415
0416
0417     /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
0418     if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
0419         return 0;
0420
0421     /*
0422      * determine the ratio of the compute unit power accumulator
0423      * sample period to the PTSC counter period by executing CPUID
0424      * Fn8000_0007:ECX
0425      */
0426     data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
0427
0428     if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
0429         pr_err("Failed to read max compute unit power accumulator MSR\n");
0430         return -ENODEV;
0431     }
0432
0433     data->max_cu_acc_power = tmp;
0434
0435     /*
0436      * Milliseconds are a reasonable interval for the measurement.
0437      * But it shouldn't set too long here, because several seconds
0438      * would cause the read function to hang. So set default
0439      * interval as 10 ms.
0440      */
0441     data->power_period = 10;
0442
0443     return read_registers(data);
0444 }
0445
0446 static int fam15h_power_probe(struct pci_dev *pdev,
0447                   const struct pci_device_id *id)
0448 {
0449     struct fam15h_power_data *data;
0450     struct device *dev = &pdev->dev;
0451     struct device *hwmon_dev;
0452     int ret;
0453
0454     /*
0455      * though we ignore every other northbridge, we still have to
0456      * do the tweaking on _each_ node in MCM processors as the counters
0457      * are working hand-in-hand
0458      */
0459     tweak_runavg_range(pdev);
0460
0461     if (!should_load_on_this_node(pdev))
0462         return -ENODEV;
0463
0464     data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
0465     if (!data)
0466         return -ENOMEM;
0467
0468     ret = fam15h_power_init_data(pdev, data);
0469     if (ret)
0470         return ret;
0471
0472     data->pdev = pdev;
0473
0474     data->groups[0] = &data->group;
0475
0476     hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
0477                                data,
0478                                &data->groups[0]);
0479     return PTR_ERR_OR_ZERO(hwmon_dev);
0480 }
0481
0482 static const struct pci_device_id fam15h_power_id_table[] = {
0483     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
0484     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
0485     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
0486     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
0487     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
0488     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
0489     {}
0490 };
0491 MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
0492
0493 static struct pci_driver fam15h_power_driver = {
0494     .name = "fam15h_power",
0495     .id_table = fam15h_power_id_table,
0496     .probe = fam15h_power_probe,
0497     .resume = fam15h_power_resume,
0498 };
0499
0500 module_pci_driver(fam15h_power_driver);