Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * coretemp.c - Linux kernel module for hardware monitoring
0004  *
0005  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
0006  *
0007  * Inspired from many hwmon drivers
0008  */
0009 
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011 
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/slab.h>
0015 #include <linux/jiffies.h>
0016 #include <linux/hwmon.h>
0017 #include <linux/sysfs.h>
0018 #include <linux/hwmon-sysfs.h>
0019 #include <linux/err.h>
0020 #include <linux/mutex.h>
0021 #include <linux/list.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/cpu.h>
0024 #include <linux/smp.h>
0025 #include <linux/moduleparam.h>
0026 #include <linux/pci.h>
0027 #include <asm/msr.h>
0028 #include <asm/processor.h>
0029 #include <asm/cpu_device_id.h>
0030 
0031 #define DRVNAME "coretemp"
0032 
0033 /*
0034  * force_tjmax only matters when TjMax can't be read from the CPU itself.
0035  * When set, it replaces the driver's suboptimal heuristic.
0036  */
0037 static int force_tjmax;
0038 module_param_named(tjmax, force_tjmax, int, 0444);
0039 MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
0040 
0041 #define PKG_SYSFS_ATTR_NO   1   /* Sysfs attribute for package temp */
0042 #define BASE_SYSFS_ATTR_NO  2   /* Sysfs Base attr no for coretemp */
0043 #define NUM_REAL_CORES      128 /* Number of Real cores per cpu */
0044 #define CORETEMP_NAME_LENGTH    19  /* String Length of attrs */
0045 #define MAX_CORE_ATTRS      4   /* Maximum no of basic attrs */
0046 #define TOTAL_ATTRS     (MAX_CORE_ATTRS + 1)
0047 #define MAX_CORE_DATA       (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)
0048 
0049 #define TO_CORE_ID(cpu)     (cpu_data(cpu).cpu_core_id)
0050 #define TO_ATTR_NO(cpu)     (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO)
0051 
0052 #ifdef CONFIG_SMP
0053 #define for_each_sibling(i, cpu) \
0054     for_each_cpu(i, topology_sibling_cpumask(cpu))
0055 #else
0056 #define for_each_sibling(i, cpu)    for (i = 0; false; )
0057 #endif
0058 
0059 /*
0060  * Per-Core Temperature Data
0061  * @last_updated: The time when the current temperature value was updated
0062  *      earlier (in jiffies).
0063  * @cpu_core_id: The CPU Core from which temperature values should be read
0064  *      This value is passed as "id" field to rdmsr/wrmsr functions.
0065  * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
0066  *      from where the temperature values should be read.
0067  * @attr_size:  Total number of pre-core attrs displayed in the sysfs.
0068  * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data.
0069  *      Otherwise, temp_data holds coretemp data.
0070  * @valid: If this is 1, the current temperature is valid.
0071  */
0072 struct temp_data {
0073     int temp;
0074     int ttarget;
0075     int tjmax;
0076     unsigned long last_updated;
0077     unsigned int cpu;
0078     u32 cpu_core_id;
0079     u32 status_reg;
0080     int attr_size;
0081     bool is_pkg_data;
0082     bool valid;
0083     struct sensor_device_attribute sd_attrs[TOTAL_ATTRS];
0084     char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH];
0085     struct attribute *attrs[TOTAL_ATTRS + 1];
0086     struct attribute_group attr_group;
0087     struct mutex update_lock;
0088 };
0089 
0090 /* Platform Data per Physical CPU */
0091 struct platform_data {
0092     struct device       *hwmon_dev;
0093     u16         pkg_id;
0094     struct cpumask      cpumask;
0095     struct temp_data    *core_data[MAX_CORE_DATA];
0096     struct device_attribute name_attr;
0097 };
0098 
0099 /* Keep track of how many zone pointers we allocated in init() */
0100 static int max_zones __read_mostly;
0101 /* Array of zone pointers. Serialized by cpu hotplug lock */
0102 static struct platform_device **zone_devices;
0103 
0104 static ssize_t show_label(struct device *dev,
0105                 struct device_attribute *devattr, char *buf)
0106 {
0107     struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
0108     struct platform_data *pdata = dev_get_drvdata(dev);
0109     struct temp_data *tdata = pdata->core_data[attr->index];
0110 
0111     if (tdata->is_pkg_data)
0112         return sprintf(buf, "Package id %u\n", pdata->pkg_id);
0113 
0114     return sprintf(buf, "Core %u\n", tdata->cpu_core_id);
0115 }
0116 
0117 static ssize_t show_crit_alarm(struct device *dev,
0118                 struct device_attribute *devattr, char *buf)
0119 {
0120     u32 eax, edx;
0121     struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
0122     struct platform_data *pdata = dev_get_drvdata(dev);
0123     struct temp_data *tdata = pdata->core_data[attr->index];
0124 
0125     mutex_lock(&tdata->update_lock);
0126     rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
0127     mutex_unlock(&tdata->update_lock);
0128 
0129     return sprintf(buf, "%d\n", (eax >> 5) & 1);
0130 }
0131 
0132 static ssize_t show_tjmax(struct device *dev,
0133             struct device_attribute *devattr, char *buf)
0134 {
0135     struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
0136     struct platform_data *pdata = dev_get_drvdata(dev);
0137 
0138     return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax);
0139 }
0140 
0141 static ssize_t show_ttarget(struct device *dev,
0142                 struct device_attribute *devattr, char *buf)
0143 {
0144     struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
0145     struct platform_data *pdata = dev_get_drvdata(dev);
0146 
0147     return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget);
0148 }
0149 
0150 static ssize_t show_temp(struct device *dev,
0151             struct device_attribute *devattr, char *buf)
0152 {
0153     u32 eax, edx;
0154     struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
0155     struct platform_data *pdata = dev_get_drvdata(dev);
0156     struct temp_data *tdata = pdata->core_data[attr->index];
0157 
0158     mutex_lock(&tdata->update_lock);
0159 
0160     /* Check whether the time interval has elapsed */
0161     if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) {
0162         rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
0163         /*
0164          * Ignore the valid bit. In all observed cases the register
0165          * value is either low or zero if the valid bit is 0.
0166          * Return it instead of reporting an error which doesn't
0167          * really help at all.
0168          */
0169         tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000;
0170         tdata->valid = true;
0171         tdata->last_updated = jiffies;
0172     }
0173 
0174     mutex_unlock(&tdata->update_lock);
0175     return sprintf(buf, "%d\n", tdata->temp);
0176 }
0177 
0178 struct tjmax_pci {
0179     unsigned int device;
0180     int tjmax;
0181 };
0182 
0183 static const struct tjmax_pci tjmax_pci_table[] = {
0184     { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */
0185     { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */
0186     { 0x0c73, 95000 },  /* Atom S1220 (Centerton) */
0187     { 0x0c75, 95000 },  /* Atom S1260 (Centerton) */
0188 };
0189 
0190 struct tjmax {
0191     char const *id;
0192     int tjmax;
0193 };
0194 
0195 static const struct tjmax tjmax_table[] = {
0196     { "CPU  230", 100000 },     /* Model 0x1c, stepping 2   */
0197     { "CPU  330", 125000 },     /* Model 0x1c, stepping 2   */
0198 };
0199 
0200 struct tjmax_model {
0201     u8 model;
0202     u8 mask;
0203     int tjmax;
0204 };
0205 
0206 #define ANY 0xff
0207 
0208 static const struct tjmax_model tjmax_model_table[] = {
0209     { 0x1c, 10, 100000 },   /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */
0210     { 0x1c, ANY, 90000 },   /* Z5xx, N2xx, possibly others
0211                  * Note: Also matches 230 and 330,
0212                  * which are covered by tjmax_table
0213                  */
0214     { 0x26, ANY, 90000 },   /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
0215                  * Note: TjMax for E6xxT is 110C, but CPU type
0216                  * is undetectable by software
0217                  */
0218     { 0x27, ANY, 90000 },   /* Atom Medfield (Z2460) */
0219     { 0x35, ANY, 90000 },   /* Atom Clover Trail/Cloverview (Z27x0) */
0220     { 0x36, ANY, 100000 },  /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx)
0221                  * Also matches S12x0 (stepping 9), covered by
0222                  * PCI table
0223                  */
0224 };
0225 
0226 static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
0227 {
0228     /* The 100C is default for both mobile and non mobile CPUs */
0229 
0230     int tjmax = 100000;
0231     int tjmax_ee = 85000;
0232     int usemsr_ee = 1;
0233     int err;
0234     u32 eax, edx;
0235     int i;
0236     u16 devfn = PCI_DEVFN(0, 0);
0237     struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn);
0238 
0239     /*
0240      * Explicit tjmax table entries override heuristics.
0241      * First try PCI host bridge IDs, followed by model ID strings
0242      * and model/stepping information.
0243      */
0244     if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) {
0245         for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) {
0246             if (host_bridge->device == tjmax_pci_table[i].device)
0247                 return tjmax_pci_table[i].tjmax;
0248         }
0249     }
0250 
0251     for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
0252         if (strstr(c->x86_model_id, tjmax_table[i].id))
0253             return tjmax_table[i].tjmax;
0254     }
0255 
0256     for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
0257         const struct tjmax_model *tm = &tjmax_model_table[i];
0258         if (c->x86_model == tm->model &&
0259             (tm->mask == ANY || c->x86_stepping == tm->mask))
0260             return tm->tjmax;
0261     }
0262 
0263     /* Early chips have no MSR for TjMax */
0264 
0265     if (c->x86_model == 0xf && c->x86_stepping < 4)
0266         usemsr_ee = 0;
0267 
0268     if (c->x86_model > 0xe && usemsr_ee) {
0269         u8 platform_id;
0270 
0271         /*
0272          * Now we can detect the mobile CPU using Intel provided table
0273          * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
0274          * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
0275          */
0276         err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
0277         if (err) {
0278             dev_warn(dev,
0279                  "Unable to access MSR 0x17, assuming desktop"
0280                  " CPU\n");
0281             usemsr_ee = 0;
0282         } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
0283             /*
0284              * Trust bit 28 up to Penryn, I could not find any
0285              * documentation on that; if you happen to know
0286              * someone at Intel please ask
0287              */
0288             usemsr_ee = 0;
0289         } else {
0290             /* Platform ID bits 52:50 (EDX starts at bit 32) */
0291             platform_id = (edx >> 18) & 0x7;
0292 
0293             /*
0294              * Mobile Penryn CPU seems to be platform ID 7 or 5
0295              * (guesswork)
0296              */
0297             if (c->x86_model == 0x17 &&
0298                 (platform_id == 5 || platform_id == 7)) {
0299                 /*
0300                  * If MSR EE bit is set, set it to 90 degrees C,
0301                  * otherwise 105 degrees C
0302                  */
0303                 tjmax_ee = 90000;
0304                 tjmax = 105000;
0305             }
0306         }
0307     }
0308 
0309     if (usemsr_ee) {
0310         err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
0311         if (err) {
0312             dev_warn(dev,
0313                  "Unable to access MSR 0xEE, for Tjmax, left"
0314                  " at default\n");
0315         } else if (eax & 0x40000000) {
0316             tjmax = tjmax_ee;
0317         }
0318     } else if (tjmax == 100000) {
0319         /*
0320          * If we don't use msr EE it means we are desktop CPU
0321          * (with exeception of Atom)
0322          */
0323         dev_warn(dev, "Using relative temperature scale!\n");
0324     }
0325 
0326     return tjmax;
0327 }
0328 
0329 static bool cpu_has_tjmax(struct cpuinfo_x86 *c)
0330 {
0331     u8 model = c->x86_model;
0332 
0333     return model > 0xe &&
0334            model != 0x1c &&
0335            model != 0x26 &&
0336            model != 0x27 &&
0337            model != 0x35 &&
0338            model != 0x36;
0339 }
0340 
0341 static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
0342 {
0343     int err;
0344     u32 eax, edx;
0345     u32 val;
0346 
0347     /*
0348      * A new feature of current Intel(R) processors, the
0349      * IA32_TEMPERATURE_TARGET contains the TjMax value
0350      */
0351     err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
0352     if (err) {
0353         if (cpu_has_tjmax(c))
0354             dev_warn(dev, "Unable to read TjMax from CPU %u\n", id);
0355     } else {
0356         val = (eax >> 16) & 0xff;
0357         /*
0358          * If the TjMax is not plausible, an assumption
0359          * will be used
0360          */
0361         if (val) {
0362             dev_dbg(dev, "TjMax is %d degrees C\n", val);
0363             return val * 1000;
0364         }
0365     }
0366 
0367     if (force_tjmax) {
0368         dev_notice(dev, "TjMax forced to %d degrees C by user\n",
0369                force_tjmax);
0370         return force_tjmax * 1000;
0371     }
0372 
0373     /*
0374      * An assumption is made for early CPUs and unreadable MSR.
0375      * NOTE: the calculated value may not be correct.
0376      */
0377     return adjust_tjmax(c, id, dev);
0378 }
0379 
0380 static int create_core_attrs(struct temp_data *tdata, struct device *dev,
0381                  int attr_no)
0382 {
0383     int i;
0384     static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
0385             struct device_attribute *devattr, char *buf) = {
0386             show_label, show_crit_alarm, show_temp, show_tjmax,
0387             show_ttarget };
0388     static const char *const suffixes[TOTAL_ATTRS] = {
0389         "label", "crit_alarm", "input", "crit", "max"
0390     };
0391 
0392     for (i = 0; i < tdata->attr_size; i++) {
0393         snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH,
0394              "temp%d_%s", attr_no, suffixes[i]);
0395         sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr);
0396         tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i];
0397         tdata->sd_attrs[i].dev_attr.attr.mode = 0444;
0398         tdata->sd_attrs[i].dev_attr.show = rd_ptr[i];
0399         tdata->sd_attrs[i].index = attr_no;
0400         tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr;
0401     }
0402     tdata->attr_group.attrs = tdata->attrs;
0403     return sysfs_create_group(&dev->kobj, &tdata->attr_group);
0404 }
0405 
0406 
0407 static int chk_ucode_version(unsigned int cpu)
0408 {
0409     struct cpuinfo_x86 *c = &cpu_data(cpu);
0410 
0411     /*
0412      * Check if we have problem with errata AE18 of Core processors:
0413      * Readings might stop update when processor visited too deep sleep,
0414      * fixed for stepping D0 (6EC).
0415      */
0416     if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
0417         pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
0418         return -ENODEV;
0419     }
0420     return 0;
0421 }
0422 
0423 static struct platform_device *coretemp_get_pdev(unsigned int cpu)
0424 {
0425     int id = topology_logical_die_id(cpu);
0426 
0427     if (id >= 0 && id < max_zones)
0428         return zone_devices[id];
0429     return NULL;
0430 }
0431 
0432 static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag)
0433 {
0434     struct temp_data *tdata;
0435 
0436     tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL);
0437     if (!tdata)
0438         return NULL;
0439 
0440     tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
0441                             MSR_IA32_THERM_STATUS;
0442     tdata->is_pkg_data = pkg_flag;
0443     tdata->cpu = cpu;
0444     tdata->cpu_core_id = TO_CORE_ID(cpu);
0445     tdata->attr_size = MAX_CORE_ATTRS;
0446     mutex_init(&tdata->update_lock);
0447     return tdata;
0448 }
0449 
0450 static int create_core_data(struct platform_device *pdev, unsigned int cpu,
0451                 int pkg_flag)
0452 {
0453     struct temp_data *tdata;
0454     struct platform_data *pdata = platform_get_drvdata(pdev);
0455     struct cpuinfo_x86 *c = &cpu_data(cpu);
0456     u32 eax, edx;
0457     int err, attr_no;
0458 
0459     /*
0460      * Find attr number for sysfs:
0461      * We map the attr number to core id of the CPU
0462      * The attr number is always core id + 2
0463      * The Pkgtemp will always show up as temp1_*, if available
0464      */
0465     attr_no = pkg_flag ? PKG_SYSFS_ATTR_NO : TO_ATTR_NO(cpu);
0466 
0467     if (attr_no > MAX_CORE_DATA - 1)
0468         return -ERANGE;
0469 
0470     tdata = init_temp_data(cpu, pkg_flag);
0471     if (!tdata)
0472         return -ENOMEM;
0473 
0474     /* Test if we can access the status register */
0475     err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx);
0476     if (err)
0477         goto exit_free;
0478 
0479     /* We can access status register. Get Critical Temperature */
0480     tdata->tjmax = get_tjmax(c, cpu, &pdev->dev);
0481 
0482     /*
0483      * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET.
0484      * The target temperature is available on older CPUs but not in this
0485      * register. Atoms don't have the register at all.
0486      */
0487     if (c->x86_model > 0xe && c->x86_model != 0x1c) {
0488         err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET,
0489                     &eax, &edx);
0490         if (!err) {
0491             tdata->ttarget
0492               = tdata->tjmax - ((eax >> 8) & 0xff) * 1000;
0493             tdata->attr_size++;
0494         }
0495     }
0496 
0497     pdata->core_data[attr_no] = tdata;
0498 
0499     /* Create sysfs interfaces */
0500     err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no);
0501     if (err)
0502         goto exit_free;
0503 
0504     return 0;
0505 exit_free:
0506     pdata->core_data[attr_no] = NULL;
0507     kfree(tdata);
0508     return err;
0509 }
0510 
0511 static void
0512 coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag)
0513 {
0514     if (create_core_data(pdev, cpu, pkg_flag))
0515         dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
0516 }
0517 
0518 static void coretemp_remove_core(struct platform_data *pdata, int indx)
0519 {
0520     struct temp_data *tdata = pdata->core_data[indx];
0521 
0522     /* Remove the sysfs attributes */
0523     sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group);
0524 
0525     kfree(pdata->core_data[indx]);
0526     pdata->core_data[indx] = NULL;
0527 }
0528 
0529 static int coretemp_probe(struct platform_device *pdev)
0530 {
0531     struct device *dev = &pdev->dev;
0532     struct platform_data *pdata;
0533 
0534     /* Initialize the per-zone data structures */
0535     pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL);
0536     if (!pdata)
0537         return -ENOMEM;
0538 
0539     pdata->pkg_id = pdev->id;
0540     platform_set_drvdata(pdev, pdata);
0541 
0542     pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME,
0543                                   pdata, NULL);
0544     return PTR_ERR_OR_ZERO(pdata->hwmon_dev);
0545 }
0546 
0547 static int coretemp_remove(struct platform_device *pdev)
0548 {
0549     struct platform_data *pdata = platform_get_drvdata(pdev);
0550     int i;
0551 
0552     for (i = MAX_CORE_DATA - 1; i >= 0; --i)
0553         if (pdata->core_data[i])
0554             coretemp_remove_core(pdata, i);
0555 
0556     return 0;
0557 }
0558 
0559 static struct platform_driver coretemp_driver = {
0560     .driver = {
0561         .name = DRVNAME,
0562     },
0563     .probe = coretemp_probe,
0564     .remove = coretemp_remove,
0565 };
0566 
0567 static struct platform_device *coretemp_device_add(unsigned int cpu)
0568 {
0569     int err, zoneid = topology_logical_die_id(cpu);
0570     struct platform_device *pdev;
0571 
0572     if (zoneid < 0)
0573         return ERR_PTR(-ENOMEM);
0574 
0575     pdev = platform_device_alloc(DRVNAME, zoneid);
0576     if (!pdev)
0577         return ERR_PTR(-ENOMEM);
0578 
0579     err = platform_device_add(pdev);
0580     if (err) {
0581         platform_device_put(pdev);
0582         return ERR_PTR(err);
0583     }
0584 
0585     zone_devices[zoneid] = pdev;
0586     return pdev;
0587 }
0588 
0589 static int coretemp_cpu_online(unsigned int cpu)
0590 {
0591     struct platform_device *pdev = coretemp_get_pdev(cpu);
0592     struct cpuinfo_x86 *c = &cpu_data(cpu);
0593     struct platform_data *pdata;
0594 
0595     /*
0596      * Don't execute this on resume as the offline callback did
0597      * not get executed on suspend.
0598      */
0599     if (cpuhp_tasks_frozen)
0600         return 0;
0601 
0602     /*
0603      * CPUID.06H.EAX[0] indicates whether the CPU has thermal
0604      * sensors. We check this bit only, all the early CPUs
0605      * without thermal sensors will be filtered out.
0606      */
0607     if (!cpu_has(c, X86_FEATURE_DTHERM))
0608         return -ENODEV;
0609 
0610     if (!pdev) {
0611         /* Check the microcode version of the CPU */
0612         if (chk_ucode_version(cpu))
0613             return -EINVAL;
0614 
0615         /*
0616          * Alright, we have DTS support.
0617          * We are bringing the _first_ core in this pkg
0618          * online. So, initialize per-pkg data structures and
0619          * then bring this core online.
0620          */
0621         pdev = coretemp_device_add(cpu);
0622         if (IS_ERR(pdev))
0623             return PTR_ERR(pdev);
0624 
0625         /*
0626          * Check whether pkgtemp support is available.
0627          * If so, add interfaces for pkgtemp.
0628          */
0629         if (cpu_has(c, X86_FEATURE_PTS))
0630             coretemp_add_core(pdev, cpu, 1);
0631     }
0632 
0633     pdata = platform_get_drvdata(pdev);
0634     /*
0635      * Check whether a thread sibling is already online. If not add the
0636      * interface for this CPU core.
0637      */
0638     if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu)))
0639         coretemp_add_core(pdev, cpu, 0);
0640 
0641     cpumask_set_cpu(cpu, &pdata->cpumask);
0642     return 0;
0643 }
0644 
0645 static int coretemp_cpu_offline(unsigned int cpu)
0646 {
0647     struct platform_device *pdev = coretemp_get_pdev(cpu);
0648     struct platform_data *pd;
0649     struct temp_data *tdata;
0650     int indx, target;
0651 
0652     /*
0653      * Don't execute this on suspend as the device remove locks
0654      * up the machine.
0655      */
0656     if (cpuhp_tasks_frozen)
0657         return 0;
0658 
0659     /* If the physical CPU device does not exist, just return */
0660     if (!pdev)
0661         return 0;
0662 
0663     /* The core id is too big, just return */
0664     indx = TO_ATTR_NO(cpu);
0665     if (indx > MAX_CORE_DATA - 1)
0666         return 0;
0667 
0668     pd = platform_get_drvdata(pdev);
0669     tdata = pd->core_data[indx];
0670 
0671     cpumask_clear_cpu(cpu, &pd->cpumask);
0672 
0673     /*
0674      * If this is the last thread sibling, remove the CPU core
0675      * interface, If there is still a sibling online, transfer the
0676      * target cpu of that core interface to it.
0677      */
0678     target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu));
0679     if (target >= nr_cpu_ids) {
0680         coretemp_remove_core(pd, indx);
0681     } else if (tdata && tdata->cpu == cpu) {
0682         mutex_lock(&tdata->update_lock);
0683         tdata->cpu = target;
0684         mutex_unlock(&tdata->update_lock);
0685     }
0686 
0687     /*
0688      * If all cores in this pkg are offline, remove the device. This
0689      * will invoke the platform driver remove function, which cleans up
0690      * the rest.
0691      */
0692     if (cpumask_empty(&pd->cpumask)) {
0693         zone_devices[topology_logical_die_id(cpu)] = NULL;
0694         platform_device_unregister(pdev);
0695         return 0;
0696     }
0697 
0698     /*
0699      * Check whether this core is the target for the package
0700      * interface. We need to assign it to some other cpu.
0701      */
0702     tdata = pd->core_data[PKG_SYSFS_ATTR_NO];
0703     if (tdata && tdata->cpu == cpu) {
0704         target = cpumask_first(&pd->cpumask);
0705         mutex_lock(&tdata->update_lock);
0706         tdata->cpu = target;
0707         mutex_unlock(&tdata->update_lock);
0708     }
0709     return 0;
0710 }
0711 static const struct x86_cpu_id __initconst coretemp_ids[] = {
0712     X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL),
0713     {}
0714 };
0715 MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);
0716 
0717 static enum cpuhp_state coretemp_hp_online;
0718 
0719 static int __init coretemp_init(void)
0720 {
0721     int err;
0722 
0723     /*
0724      * CPUID.06H.EAX[0] indicates whether the CPU has thermal
0725      * sensors. We check this bit only, all the early CPUs
0726      * without thermal sensors will be filtered out.
0727      */
0728     if (!x86_match_cpu(coretemp_ids))
0729         return -ENODEV;
0730 
0731     max_zones = topology_max_packages() * topology_max_die_per_package();
0732     zone_devices = kcalloc(max_zones, sizeof(struct platform_device *),
0733                   GFP_KERNEL);
0734     if (!zone_devices)
0735         return -ENOMEM;
0736 
0737     err = platform_driver_register(&coretemp_driver);
0738     if (err)
0739         goto outzone;
0740 
0741     err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online",
0742                 coretemp_cpu_online, coretemp_cpu_offline);
0743     if (err < 0)
0744         goto outdrv;
0745     coretemp_hp_online = err;
0746     return 0;
0747 
0748 outdrv:
0749     platform_driver_unregister(&coretemp_driver);
0750 outzone:
0751     kfree(zone_devices);
0752     return err;
0753 }
0754 module_init(coretemp_init)
0755 
0756 static void __exit coretemp_exit(void)
0757 {
0758     cpuhp_remove_state(coretemp_hp_online);
0759     platform_driver_unregister(&coretemp_driver);
0760     kfree(zone_devices);
0761 }
0762 module_exit(coretemp_exit)
0763 
0764 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
0765 MODULE_DESCRIPTION("Intel Core temperature monitor");
0766 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!