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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Fan Control HDL CORE driver
0004  *
0005  * Copyright 2019 Analog Devices Inc.
0006  */
0007 #include <linux/bits.h>
0008 #include <linux/clk.h>
0009 #include <linux/fpga/adi-axi-common.h>
0010 #include <linux/hwmon.h>
0011 #include <linux/hwmon-sysfs.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 
0019 /* register map */
0020 #define ADI_REG_RSTN        0x0080
0021 #define ADI_REG_PWM_WIDTH   0x0084
0022 #define ADI_REG_TACH_PERIOD 0x0088
0023 #define ADI_REG_TACH_TOLERANCE  0x008c
0024 #define ADI_REG_PWM_PERIOD  0x00c0
0025 #define ADI_REG_TACH_MEASUR 0x00c4
0026 #define ADI_REG_TEMPERATURE 0x00c8
0027 #define ADI_REG_TEMP_00_H   0x0100
0028 #define ADI_REG_TEMP_25_L   0x0104
0029 #define ADI_REG_TEMP_25_H   0x0108
0030 #define ADI_REG_TEMP_50_L   0x010c
0031 #define ADI_REG_TEMP_50_H   0x0110
0032 #define ADI_REG_TEMP_75_L   0x0114
0033 #define ADI_REG_TEMP_75_H   0x0118
0034 #define ADI_REG_TEMP_100_L  0x011c
0035 
0036 #define ADI_REG_IRQ_MASK    0x0040
0037 #define ADI_REG_IRQ_PENDING 0x0044
0038 #define ADI_REG_IRQ_SRC     0x0048
0039 
0040 /* IRQ sources */
0041 #define ADI_IRQ_SRC_PWM_CHANGED     BIT(0)
0042 #define ADI_IRQ_SRC_TACH_ERR        BIT(1)
0043 #define ADI_IRQ_SRC_TEMP_INCREASE   BIT(2)
0044 #define ADI_IRQ_SRC_NEW_MEASUR      BIT(3)
0045 #define ADI_IRQ_SRC_MASK        GENMASK(3, 0)
0046 #define ADI_IRQ_MASK_OUT_ALL        0xFFFFFFFFU
0047 
0048 #define SYSFS_PWM_MAX           255
0049 
0050 struct axi_fan_control_data {
0051     void __iomem *base;
0052     struct device *hdev;
0053     unsigned long clk_rate;
0054     int irq;
0055     /* pulses per revolution */
0056     u32 ppr;
0057     bool hw_pwm_req;
0058     bool update_tacho_params;
0059     u8 fan_fault;
0060 };
0061 
0062 static inline void axi_iowrite(const u32 val, const u32 reg,
0063                    const struct axi_fan_control_data *ctl)
0064 {
0065     iowrite32(val, ctl->base + reg);
0066 }
0067 
0068 static inline u32 axi_ioread(const u32 reg,
0069                  const struct axi_fan_control_data *ctl)
0070 {
0071     return ioread32(ctl->base + reg);
0072 }
0073 
0074 /*
0075  * The core calculates the temperature as:
0076  *  T = /raw * 509.3140064 / 65535) - 280.2308787
0077  */
0078 static ssize_t axi_fan_control_show(struct device *dev, struct device_attribute *da, char *buf)
0079 {
0080     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0081     struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
0082     u32 temp = axi_ioread(attr->index, ctl);
0083 
0084     temp = DIV_ROUND_CLOSEST_ULL(temp * 509314ULL, 65535) - 280230;
0085 
0086     return sprintf(buf, "%u\n", temp);
0087 }
0088 
0089 static ssize_t axi_fan_control_store(struct device *dev, struct device_attribute *da,
0090                      const char *buf, size_t count)
0091 {
0092     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0093     struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
0094     u32 temp;
0095     int ret;
0096 
0097     ret = kstrtou32(buf, 10, &temp);
0098     if (ret)
0099         return ret;
0100 
0101     temp = DIV_ROUND_CLOSEST_ULL((temp + 280230) * 65535ULL, 509314);
0102     axi_iowrite(temp, attr->index, ctl);
0103 
0104     return count;
0105 }
0106 
0107 static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl)
0108 {
0109     u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl);
0110     u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
0111     /*
0112      * PWM_PERIOD is a RO register set by the core. It should never be 0.
0113      * For now we are trusting the HW...
0114      */
0115     return DIV_ROUND_CLOSEST(pwm_width * SYSFS_PWM_MAX, pwm_period);
0116 }
0117 
0118 static int axi_fan_control_set_pwm_duty(const long val,
0119                     struct axi_fan_control_data *ctl)
0120 {
0121     u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
0122     u32 new_width;
0123     long __val = clamp_val(val, 0, SYSFS_PWM_MAX);
0124 
0125     new_width = DIV_ROUND_CLOSEST(__val * pwm_period, SYSFS_PWM_MAX);
0126 
0127     axi_iowrite(new_width, ADI_REG_PWM_WIDTH, ctl);
0128 
0129     return 0;
0130 }
0131 
0132 static long axi_fan_control_get_fan_rpm(const struct axi_fan_control_data *ctl)
0133 {
0134     const u32 tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
0135 
0136     if (tach == 0)
0137         /* should we return error, EAGAIN maybe? */
0138         return 0;
0139     /*
0140      * The tacho period should be:
0141      *      TACH = 60/(ppr * rpm), where rpm is revolutions per second
0142      *      and ppr is pulses per revolution.
0143      * Given the tacho period, we can multiply it by the input clock
0144      * so that we know how many clocks we need to have this period.
0145      * From this, we can derive the RPM value.
0146      */
0147     return DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * tach);
0148 }
0149 
0150 static int axi_fan_control_read_temp(struct device *dev, u32 attr, long *val)
0151 {
0152     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0153     long raw_temp;
0154 
0155     switch (attr) {
0156     case hwmon_temp_input:
0157         raw_temp = axi_ioread(ADI_REG_TEMPERATURE, ctl);
0158         /*
0159          * The formula for the temperature is:
0160          *      T = (ADC * 501.3743 / 2^bits) - 273.6777
0161          * It's multiplied by 1000 to have millidegrees as
0162          * specified by the hwmon sysfs interface.
0163          */
0164         *val = ((raw_temp * 501374) >> 16) - 273677;
0165         return 0;
0166     default:
0167         return -ENOTSUPP;
0168     }
0169 }
0170 
0171 static int axi_fan_control_read_fan(struct device *dev, u32 attr, long *val)
0172 {
0173     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0174 
0175     switch (attr) {
0176     case hwmon_fan_fault:
0177         *val = ctl->fan_fault;
0178         /* clear it now */
0179         ctl->fan_fault = 0;
0180         return 0;
0181     case hwmon_fan_input:
0182         *val = axi_fan_control_get_fan_rpm(ctl);
0183         return 0;
0184     default:
0185         return -ENOTSUPP;
0186     }
0187 }
0188 
0189 static int axi_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
0190 {
0191     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0192 
0193     switch (attr) {
0194     case hwmon_pwm_input:
0195         *val = axi_fan_control_get_pwm_duty(ctl);
0196         return 0;
0197     default:
0198         return -ENOTSUPP;
0199     }
0200 }
0201 
0202 static int axi_fan_control_write_pwm(struct device *dev, u32 attr, long val)
0203 {
0204     struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
0205 
0206     switch (attr) {
0207     case hwmon_pwm_input:
0208         return axi_fan_control_set_pwm_duty(val, ctl);
0209     default:
0210         return -ENOTSUPP;
0211     }
0212 }
0213 
0214 static int axi_fan_control_read_labels(struct device *dev,
0215                        enum hwmon_sensor_types type,
0216                        u32 attr, int channel, const char **str)
0217 {
0218     switch (type) {
0219     case hwmon_fan:
0220         *str = "FAN";
0221         return 0;
0222     case hwmon_temp:
0223         *str = "SYSMON4";
0224         return 0;
0225     default:
0226         return -ENOTSUPP;
0227     }
0228 }
0229 
0230 static int axi_fan_control_read(struct device *dev,
0231                 enum hwmon_sensor_types type,
0232                 u32 attr, int channel, long *val)
0233 {
0234     switch (type) {
0235     case hwmon_fan:
0236         return axi_fan_control_read_fan(dev, attr, val);
0237     case hwmon_pwm:
0238         return axi_fan_control_read_pwm(dev, attr, val);
0239     case hwmon_temp:
0240         return axi_fan_control_read_temp(dev, attr, val);
0241     default:
0242         return -ENOTSUPP;
0243     }
0244 }
0245 
0246 static int axi_fan_control_write(struct device *dev,
0247                  enum hwmon_sensor_types type,
0248                  u32 attr, int channel, long val)
0249 {
0250     switch (type) {
0251     case hwmon_pwm:
0252         return axi_fan_control_write_pwm(dev, attr, val);
0253     default:
0254         return -ENOTSUPP;
0255     }
0256 }
0257 
0258 static umode_t axi_fan_control_fan_is_visible(const u32 attr)
0259 {
0260     switch (attr) {
0261     case hwmon_fan_input:
0262     case hwmon_fan_fault:
0263     case hwmon_fan_label:
0264         return 0444;
0265     default:
0266         return 0;
0267     }
0268 }
0269 
0270 static umode_t axi_fan_control_pwm_is_visible(const u32 attr)
0271 {
0272     switch (attr) {
0273     case hwmon_pwm_input:
0274         return 0644;
0275     default:
0276         return 0;
0277     }
0278 }
0279 
0280 static umode_t axi_fan_control_temp_is_visible(const u32 attr)
0281 {
0282     switch (attr) {
0283     case hwmon_temp_input:
0284     case hwmon_temp_label:
0285         return 0444;
0286     default:
0287         return 0;
0288     }
0289 }
0290 
0291 static umode_t axi_fan_control_is_visible(const void *data,
0292                       enum hwmon_sensor_types type,
0293                       u32 attr, int channel)
0294 {
0295     switch (type) {
0296     case hwmon_fan:
0297         return axi_fan_control_fan_is_visible(attr);
0298     case hwmon_pwm:
0299         return axi_fan_control_pwm_is_visible(attr);
0300     case hwmon_temp:
0301         return axi_fan_control_temp_is_visible(attr);
0302     default:
0303         return 0;
0304     }
0305 }
0306 
0307 /*
0308  * This core has two main ways of changing the PWM duty cycle. It is done,
0309  * either by a request from userspace (writing on pwm1_input) or by the
0310  * core itself. When the change is done by the core, it will use predefined
0311  * parameters to evaluate the tach signal and, on that case we cannot set them.
0312  * On the other hand, when the request is done by the user, with some arbitrary
0313  * value that the core does not now about, we have to provide the tach
0314  * parameters so that, the core can evaluate the signal. On the IRQ handler we
0315  * distinguish this by using the ADI_IRQ_SRC_TEMP_INCREASE interrupt. This tell
0316  * us that the CORE requested a new duty cycle. After this, there is 5s delay
0317  * on which the core waits for the fan rotation speed to stabilize. After this
0318  * we get ADI_IRQ_SRC_PWM_CHANGED irq where we will decide if we need to set
0319  * the tach parameters or not on the next tach measurement cycle (corresponding
0320  * already to the ney duty cycle) based on the %ctl->hw_pwm_req flag.
0321  */
0322 static irqreturn_t axi_fan_control_irq_handler(int irq, void *data)
0323 {
0324     struct axi_fan_control_data *ctl = (struct axi_fan_control_data *)data;
0325     u32 irq_pending = axi_ioread(ADI_REG_IRQ_PENDING, ctl);
0326     u32 clear_mask;
0327 
0328     if (irq_pending & ADI_IRQ_SRC_TEMP_INCREASE)
0329         /* hardware requested a new pwm */
0330         ctl->hw_pwm_req = true;
0331 
0332     if (irq_pending & ADI_IRQ_SRC_PWM_CHANGED) {
0333         /*
0334          * if the pwm changes on behalf of software,
0335          * we need to provide new tacho parameters to the core.
0336          * Wait for the next measurement for that...
0337          */
0338         if (!ctl->hw_pwm_req) {
0339             ctl->update_tacho_params = true;
0340         } else {
0341             ctl->hw_pwm_req = false;
0342             hwmon_notify_event(ctl->hdev, hwmon_pwm,
0343                        hwmon_pwm_input, 0);
0344         }
0345     }
0346 
0347     if (irq_pending & ADI_IRQ_SRC_NEW_MEASUR) {
0348         if (ctl->update_tacho_params) {
0349             u32 new_tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
0350             /* get 25% tolerance */
0351             u32 tach_tol = DIV_ROUND_CLOSEST(new_tach * 25, 100);
0352 
0353             /* set new tacho parameters */
0354             axi_iowrite(new_tach, ADI_REG_TACH_PERIOD, ctl);
0355             axi_iowrite(tach_tol, ADI_REG_TACH_TOLERANCE, ctl);
0356             ctl->update_tacho_params = false;
0357         }
0358     }
0359 
0360     if (irq_pending & ADI_IRQ_SRC_TACH_ERR)
0361         ctl->fan_fault = 1;
0362 
0363     /* clear all interrupts */
0364     clear_mask = irq_pending & ADI_IRQ_SRC_MASK;
0365     axi_iowrite(clear_mask, ADI_REG_IRQ_PENDING, ctl);
0366 
0367     return IRQ_HANDLED;
0368 }
0369 
0370 static int axi_fan_control_init(struct axi_fan_control_data *ctl,
0371                 const struct device_node *np)
0372 {
0373     int ret;
0374 
0375     /* get fan pulses per revolution */
0376     ret = of_property_read_u32(np, "pulses-per-revolution", &ctl->ppr);
0377     if (ret)
0378         return ret;
0379 
0380     /* 1, 2 and 4 are the typical and accepted values */
0381     if (ctl->ppr != 1 && ctl->ppr != 2 && ctl->ppr != 4)
0382         return -EINVAL;
0383     /*
0384      * Enable all IRQs
0385      */
0386     axi_iowrite(ADI_IRQ_MASK_OUT_ALL &
0387             ~(ADI_IRQ_SRC_NEW_MEASUR | ADI_IRQ_SRC_TACH_ERR |
0388               ADI_IRQ_SRC_PWM_CHANGED | ADI_IRQ_SRC_TEMP_INCREASE),
0389             ADI_REG_IRQ_MASK, ctl);
0390 
0391     /* bring the device out of reset */
0392     axi_iowrite(0x01, ADI_REG_RSTN, ctl);
0393 
0394     return ret;
0395 }
0396 
0397 static void axi_fan_control_clk_disable(void *clk)
0398 {
0399     clk_disable_unprepare(clk);
0400 }
0401 
0402 static const struct hwmon_channel_info *axi_fan_control_info[] = {
0403     HWMON_CHANNEL_INFO(pwm, HWMON_PWM_INPUT),
0404     HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_LABEL),
0405     HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_LABEL),
0406     NULL
0407 };
0408 
0409 static const struct hwmon_ops axi_fan_control_hwmon_ops = {
0410     .is_visible = axi_fan_control_is_visible,
0411     .read = axi_fan_control_read,
0412     .write = axi_fan_control_write,
0413     .read_string = axi_fan_control_read_labels,
0414 };
0415 
0416 static const struct hwmon_chip_info axi_chip_info = {
0417     .ops = &axi_fan_control_hwmon_ops,
0418     .info = axi_fan_control_info,
0419 };
0420 
0421 /* temperature threshold below which PWM should be 0% */
0422 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp_hyst, axi_fan_control, ADI_REG_TEMP_00_H);
0423 /* temperature threshold above which PWM should be 25% */
0424 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp, axi_fan_control, ADI_REG_TEMP_25_L);
0425 /* temperature threshold below which PWM should be 25% */
0426 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp_hyst, axi_fan_control, ADI_REG_TEMP_25_H);
0427 /* temperature threshold above which PWM should be 50% */
0428 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp, axi_fan_control, ADI_REG_TEMP_50_L);
0429 /* temperature threshold below which PWM should be 50% */
0430 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp_hyst, axi_fan_control, ADI_REG_TEMP_50_H);
0431 /* temperature threshold above which PWM should be 75% */
0432 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp, axi_fan_control, ADI_REG_TEMP_75_L);
0433 /* temperature threshold below which PWM should be 75% */
0434 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp_hyst, axi_fan_control, ADI_REG_TEMP_75_H);
0435 /* temperature threshold above which PWM should be 100% */
0436 static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp, axi_fan_control, ADI_REG_TEMP_100_L);
0437 
0438 static struct attribute *axi_fan_control_attrs[] = {
0439     &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
0440     &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
0441     &sensor_dev_attr_pwm1_auto_point2_temp_hyst.dev_attr.attr,
0442     &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
0443     &sensor_dev_attr_pwm1_auto_point3_temp_hyst.dev_attr.attr,
0444     &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
0445     &sensor_dev_attr_pwm1_auto_point4_temp_hyst.dev_attr.attr,
0446     &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
0447     NULL,
0448 };
0449 ATTRIBUTE_GROUPS(axi_fan_control);
0450 
0451 static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a');
0452 
0453 static const struct of_device_id axi_fan_control_of_match[] = {
0454     { .compatible = "adi,axi-fan-control-1.00.a",
0455         .data = (void *)&version_1_0_0},
0456     {},
0457 };
0458 MODULE_DEVICE_TABLE(of, axi_fan_control_of_match);
0459 
0460 static int axi_fan_control_probe(struct platform_device *pdev)
0461 {
0462     struct axi_fan_control_data *ctl;
0463     struct clk *clk;
0464     const struct of_device_id *id;
0465     const char *name = "axi_fan_control";
0466     u32 version;
0467     int ret;
0468 
0469     id = of_match_node(axi_fan_control_of_match, pdev->dev.of_node);
0470     if (!id)
0471         return -EINVAL;
0472 
0473     ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
0474     if (!ctl)
0475         return -ENOMEM;
0476 
0477     ctl->base = devm_platform_ioremap_resource(pdev, 0);
0478     if (IS_ERR(ctl->base))
0479         return PTR_ERR(ctl->base);
0480 
0481     clk = devm_clk_get(&pdev->dev, NULL);
0482     if (IS_ERR(clk)) {
0483         dev_err(&pdev->dev, "clk_get failed with %ld\n", PTR_ERR(clk));
0484         return PTR_ERR(clk);
0485     }
0486 
0487     ret = clk_prepare_enable(clk);
0488     if (ret)
0489         return ret;
0490 
0491     ret = devm_add_action_or_reset(&pdev->dev, axi_fan_control_clk_disable, clk);
0492     if (ret)
0493         return ret;
0494 
0495     ctl->clk_rate = clk_get_rate(clk);
0496     if (!ctl->clk_rate)
0497         return -EINVAL;
0498 
0499     version = axi_ioread(ADI_AXI_REG_VERSION, ctl);
0500     if (ADI_AXI_PCORE_VER_MAJOR(version) !=
0501         ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data))) {
0502         dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
0503             ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data)),
0504             ADI_AXI_PCORE_VER_MINOR((*(u32 *)id->data)),
0505             ADI_AXI_PCORE_VER_PATCH((*(u32 *)id->data)),
0506             ADI_AXI_PCORE_VER_MAJOR(version),
0507             ADI_AXI_PCORE_VER_MINOR(version),
0508             ADI_AXI_PCORE_VER_PATCH(version));
0509         return -ENODEV;
0510     }
0511 
0512     ctl->irq = platform_get_irq(pdev, 0);
0513     if (ctl->irq < 0)
0514         return ctl->irq;
0515 
0516     ret = devm_request_threaded_irq(&pdev->dev, ctl->irq, NULL,
0517                     axi_fan_control_irq_handler,
0518                     IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
0519                     pdev->driver_override, ctl);
0520     if (ret) {
0521         dev_err(&pdev->dev, "failed to request an irq, %d", ret);
0522         return ret;
0523     }
0524 
0525     ret = axi_fan_control_init(ctl, pdev->dev.of_node);
0526     if (ret) {
0527         dev_err(&pdev->dev, "Failed to initialize device\n");
0528         return ret;
0529     }
0530 
0531     ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
0532                              name,
0533                              ctl,
0534                              &axi_chip_info,
0535                              axi_fan_control_groups);
0536 
0537     return PTR_ERR_OR_ZERO(ctl->hdev);
0538 }
0539 
0540 static struct platform_driver axi_fan_control_driver = {
0541     .driver = {
0542         .name = "axi_fan_control_driver",
0543         .of_match_table = axi_fan_control_of_match,
0544     },
0545     .probe = axi_fan_control_probe,
0546 };
0547 module_platform_driver(axi_fan_control_driver);
0548 
0549 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
0550 MODULE_DESCRIPTION("Analog Devices Fan Control HDL CORE driver");
0551 MODULE_LICENSE("GPL");
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