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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2016 Google, Inc
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/errno.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/hwmon.h>
0011 #include <linux/hwmon-sysfs.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/reset.h>
0020 #include <linux/sysfs.h>
0021 #include <linux/thermal.h>
0022 
0023 /* ASPEED PWM & FAN Tach Register Definition */
0024 #define ASPEED_PTCR_CTRL        0x00
0025 #define ASPEED_PTCR_CLK_CTRL        0x04
0026 #define ASPEED_PTCR_DUTY0_CTRL      0x08
0027 #define ASPEED_PTCR_DUTY1_CTRL      0x0c
0028 #define ASPEED_PTCR_TYPEM_CTRL      0x10
0029 #define ASPEED_PTCR_TYPEM_CTRL1     0x14
0030 #define ASPEED_PTCR_TYPEN_CTRL      0x18
0031 #define ASPEED_PTCR_TYPEN_CTRL1     0x1c
0032 #define ASPEED_PTCR_TACH_SOURCE     0x20
0033 #define ASPEED_PTCR_TRIGGER     0x28
0034 #define ASPEED_PTCR_RESULT      0x2c
0035 #define ASPEED_PTCR_INTR_CTRL       0x30
0036 #define ASPEED_PTCR_INTR_STS        0x34
0037 #define ASPEED_PTCR_TYPEM_LIMIT     0x38
0038 #define ASPEED_PTCR_TYPEN_LIMIT     0x3C
0039 #define ASPEED_PTCR_CTRL_EXT        0x40
0040 #define ASPEED_PTCR_CLK_CTRL_EXT    0x44
0041 #define ASPEED_PTCR_DUTY2_CTRL      0x48
0042 #define ASPEED_PTCR_DUTY3_CTRL      0x4c
0043 #define ASPEED_PTCR_TYPEO_CTRL      0x50
0044 #define ASPEED_PTCR_TYPEO_CTRL1     0x54
0045 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60
0046 #define ASPEED_PTCR_TYPEO_LIMIT     0x78
0047 
0048 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
0049 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1    15
0050 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2    6
0051 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15))
0052 
0053 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1    14
0054 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2    5
0055 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14))
0056 
0057 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1    13
0058 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2    4
0059 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13))
0060 
0061 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1    12
0062 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2    3
0063 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12))
0064 
0065 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x)  BIT(16 + (x))
0066 
0067 #define ASPEED_PTCR_CTRL_PWMD_EN    BIT(11)
0068 #define ASPEED_PTCR_CTRL_PWMC_EN    BIT(10)
0069 #define ASPEED_PTCR_CTRL_PWMB_EN    BIT(9)
0070 #define ASPEED_PTCR_CTRL_PWMA_EN    BIT(8)
0071 
0072 #define ASPEED_PTCR_CTRL_CLK_SRC    BIT(1)
0073 #define ASPEED_PTCR_CTRL_CLK_EN     BIT(0)
0074 
0075 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
0076 /* TYPE N */
0077 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK     GENMASK(31, 16)
0078 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT     24
0079 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H        20
0080 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L        16
0081 /* TYPE M */
0082 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
0083 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT     8
0084 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H        4
0085 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L        0
0086 
0087 /*
0088  * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
0089  * 0/1/2/3 register
0090  */
0091 #define DUTY_CTRL_PWM2_FALL_POINT   24
0092 #define DUTY_CTRL_PWM2_RISE_POINT   16
0093 #define DUTY_CTRL_PWM2_RISE_FALL_MASK   GENMASK(31, 16)
0094 #define DUTY_CTRL_PWM1_FALL_POINT   8
0095 #define DUTY_CTRL_PWM1_RISE_POINT   0
0096 #define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
0097 
0098 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
0099 #define TYPE_CTRL_FAN_MASK      (GENMASK(5, 1) | GENMASK(31, 16))
0100 #define TYPE_CTRL_FAN1_MASK     GENMASK(31, 0)
0101 #define TYPE_CTRL_FAN_PERIOD        16
0102 #define TYPE_CTRL_FAN_MODE      4
0103 #define TYPE_CTRL_FAN_DIVISION      1
0104 #define TYPE_CTRL_FAN_TYPE_EN       1
0105 
0106 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
0107 /* bit [0,1] at 0x20, bit [2] at 0x60 */
0108 #define TACH_PWM_SOURCE_BIT01(x)    ((x) * 2)
0109 #define TACH_PWM_SOURCE_BIT2(x)     ((x) * 2)
0110 #define TACH_PWM_SOURCE_MASK_BIT01(x)   (0x3 << ((x) * 2))
0111 #define TACH_PWM_SOURCE_MASK_BIT2(x)    BIT((x) * 2)
0112 
0113 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
0114 #define RESULT_STATUS_MASK      BIT(31)
0115 #define RESULT_VALUE_MASK       0xfffff
0116 
0117 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
0118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1    15
0119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2    6
0120 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15))
0121 
0122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1    14
0123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2    5
0124 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14))
0125 
0126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1    13
0127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2    4
0128 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13))
0129 
0130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1    12
0131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2    3
0132 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12))
0133 
0134 #define ASPEED_PTCR_CTRL_PWMH_EN    BIT(11)
0135 #define ASPEED_PTCR_CTRL_PWMG_EN    BIT(10)
0136 #define ASPEED_PTCR_CTRL_PWMF_EN    BIT(9)
0137 #define ASPEED_PTCR_CTRL_PWME_EN    BIT(8)
0138 
0139 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
0140 /* TYPE O */
0141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
0142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT     8
0143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H        4
0144 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L        0
0145 
0146 #define PWM_MAX 255
0147 
0148 #define BOTH_EDGES 0x02 /* 10b */
0149 
0150 #define M_PWM_DIV_H 0x00
0151 #define M_PWM_DIV_L 0x05
0152 #define M_PWM_PERIOD 0x5F
0153 #define M_TACH_CLK_DIV 0x00
0154 /*
0155  * 5:4 Type N fan tach mode selection bit:
0156  * 00: falling
0157  * 01: rising
0158  * 10: both
0159  * 11: reserved.
0160  */
0161 #define M_TACH_MODE 0x02 /* 10b */
0162 #define M_TACH_UNIT 0x0420
0163 #define INIT_FAN_CTRL 0xFF
0164 
0165 /* How long we sleep in us while waiting for an RPM result. */
0166 #define ASPEED_RPM_STATUS_SLEEP_USEC    500
0167 
0168 #define MAX_CDEV_NAME_LEN 16
0169 
0170 struct aspeed_cooling_device {
0171     char name[16];
0172     struct aspeed_pwm_tacho_data *priv;
0173     struct thermal_cooling_device *tcdev;
0174     int pwm_port;
0175     u8 *cooling_levels;
0176     u8 max_state;
0177     u8 cur_state;
0178 };
0179 
0180 struct aspeed_pwm_tacho_data {
0181     struct regmap *regmap;
0182     struct reset_control *rst;
0183     unsigned long clk_freq;
0184     bool pwm_present[8];
0185     bool fan_tach_present[16];
0186     u8 type_pwm_clock_unit[3];
0187     u8 type_pwm_clock_division_h[3];
0188     u8 type_pwm_clock_division_l[3];
0189     u8 type_fan_tach_clock_division[3];
0190     u8 type_fan_tach_mode[3];
0191     u16 type_fan_tach_unit[3];
0192     u8 pwm_port_type[8];
0193     u8 pwm_port_fan_ctrl[8];
0194     u8 fan_tach_ch_source[16];
0195     struct aspeed_cooling_device *cdev[8];
0196     const struct attribute_group *groups[3];
0197 };
0198 
0199 enum type { TYPEM, TYPEN, TYPEO };
0200 
0201 struct type_params {
0202     u32 l_value;
0203     u32 h_value;
0204     u32 unit_value;
0205     u32 clk_ctrl_mask;
0206     u32 clk_ctrl_reg;
0207     u32 ctrl_reg;
0208     u32 ctrl_reg1;
0209 };
0210 
0211 static const struct type_params type_params[] = {
0212     [TYPEM] = {
0213         .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
0214         .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
0215         .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
0216         .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
0217         .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
0218         .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
0219         .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
0220     },
0221     [TYPEN] = {
0222         .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
0223         .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
0224         .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
0225         .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
0226         .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
0227         .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
0228         .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
0229     },
0230     [TYPEO] = {
0231         .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
0232         .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
0233         .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
0234         .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
0235         .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
0236         .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
0237         .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
0238     }
0239 };
0240 
0241 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
0242 
0243 struct pwm_port_params {
0244     u32 pwm_en;
0245     u32 ctrl_reg;
0246     u32 type_part1;
0247     u32 type_part2;
0248     u32 type_mask;
0249     u32 duty_ctrl_rise_point;
0250     u32 duty_ctrl_fall_point;
0251     u32 duty_ctrl_reg;
0252     u32 duty_ctrl_rise_fall_mask;
0253 };
0254 
0255 static const struct pwm_port_params pwm_port_params[] = {
0256     [PWMA] = {
0257         .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
0258         .ctrl_reg = ASPEED_PTCR_CTRL,
0259         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
0260         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
0261         .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
0262         .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
0263         .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
0264         .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
0265         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
0266     },
0267     [PWMB] = {
0268         .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
0269         .ctrl_reg = ASPEED_PTCR_CTRL,
0270         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
0271         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
0272         .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
0273         .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
0274         .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
0275         .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
0276         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
0277     },
0278     [PWMC] = {
0279         .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
0280         .ctrl_reg = ASPEED_PTCR_CTRL,
0281         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
0282         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
0283         .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
0284         .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
0285         .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
0286         .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
0287         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
0288     },
0289     [PWMD] = {
0290         .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
0291         .ctrl_reg = ASPEED_PTCR_CTRL,
0292         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
0293         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
0294         .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
0295         .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
0296         .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
0297         .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
0298         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
0299     },
0300     [PWME] = {
0301         .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
0302         .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
0303         .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
0304         .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
0305         .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
0306         .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
0307         .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
0308         .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
0309         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
0310     },
0311     [PWMF] = {
0312         .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
0313         .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
0314         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
0315         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
0316         .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
0317         .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
0318         .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
0319         .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
0320         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
0321     },
0322     [PWMG] = {
0323         .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
0324         .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
0325         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
0326         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
0327         .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
0328         .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
0329         .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
0330         .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
0331         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
0332     },
0333     [PWMH] = {
0334         .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
0335         .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
0336         .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
0337         .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
0338         .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
0339         .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
0340         .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
0341         .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
0342         .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
0343     }
0344 };
0345 
0346 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
0347                          unsigned int val)
0348 {
0349     void __iomem *regs = (void __iomem *)context;
0350 
0351     writel(val, regs + reg);
0352     return 0;
0353 }
0354 
0355 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
0356                         unsigned int *val)
0357 {
0358     void __iomem *regs = (void __iomem *)context;
0359 
0360     *val = readl(regs + reg);
0361     return 0;
0362 }
0363 
0364 static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
0365     .reg_bits = 32,
0366     .val_bits = 32,
0367     .reg_stride = 4,
0368     .max_register = ASPEED_PTCR_TYPEO_LIMIT,
0369     .reg_write = regmap_aspeed_pwm_tacho_reg_write,
0370     .reg_read = regmap_aspeed_pwm_tacho_reg_read,
0371     .fast_io = true,
0372 };
0373 
0374 static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
0375 {
0376     regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
0377                ASPEED_PTCR_CTRL_CLK_EN,
0378                val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
0379 }
0380 
0381 static void aspeed_set_clock_source(struct regmap *regmap, int val)
0382 {
0383     regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
0384                ASPEED_PTCR_CTRL_CLK_SRC,
0385                val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
0386 }
0387 
0388 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
0389                     u8 div_high, u8 div_low, u8 unit)
0390 {
0391     u32 reg_value = ((div_high << type_params[type].h_value) |
0392              (div_low << type_params[type].l_value) |
0393              (unit << type_params[type].unit_value));
0394 
0395     regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
0396                type_params[type].clk_ctrl_mask, reg_value);
0397 }
0398 
0399 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
0400                        bool enable)
0401 {
0402     regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
0403                pwm_port_params[pwm_port].pwm_en,
0404                enable ? pwm_port_params[pwm_port].pwm_en : 0);
0405 }
0406 
0407 static void aspeed_set_pwm_port_type(struct regmap *regmap,
0408                      u8 pwm_port, u8 type)
0409 {
0410     u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
0411 
0412     reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
0413 
0414     regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
0415                pwm_port_params[pwm_port].type_mask, reg_value);
0416 }
0417 
0418 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
0419                             u8 pwm_port, u8 rising,
0420                             u8 falling)
0421 {
0422     u32 reg_value = (rising <<
0423              pwm_port_params[pwm_port].duty_ctrl_rise_point);
0424     reg_value |= (falling <<
0425               pwm_port_params[pwm_port].duty_ctrl_fall_point);
0426 
0427     regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
0428                pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
0429                reg_value);
0430 }
0431 
0432 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
0433                      bool enable)
0434 {
0435     regmap_update_bits(regmap, type_params[type].ctrl_reg,
0436                TYPE_CTRL_FAN_TYPE_EN,
0437                enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
0438 }
0439 
0440 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
0441                      u8 mode, u16 unit, u8 division)
0442 {
0443     u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
0444              (unit << TYPE_CTRL_FAN_PERIOD) |
0445              (division << TYPE_CTRL_FAN_DIVISION));
0446 
0447     regmap_update_bits(regmap, type_params[type].ctrl_reg,
0448                TYPE_CTRL_FAN_MASK, reg_value);
0449     regmap_update_bits(regmap, type_params[type].ctrl_reg1,
0450                TYPE_CTRL_FAN1_MASK, unit << 16);
0451 }
0452 
0453 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
0454                       bool enable)
0455 {
0456     regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
0457                ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
0458                enable ?
0459                ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
0460 }
0461 
0462 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
0463                       u8 fan_tach_ch_source)
0464 {
0465     u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
0466               TACH_PWM_SOURCE_BIT01(fan_tach_ch));
0467     u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
0468               TACH_PWM_SOURCE_BIT2(fan_tach_ch));
0469 
0470     regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
0471                TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
0472                reg_value1);
0473 
0474     regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
0475                TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
0476                reg_value2);
0477 }
0478 
0479 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
0480                      u8 index, u8 fan_ctrl)
0481 {
0482     u16 period, dc_time_on;
0483 
0484     period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
0485     period += 1;
0486     dc_time_on = (fan_ctrl * period) / PWM_MAX;
0487 
0488     if (dc_time_on == 0) {
0489         aspeed_set_pwm_port_enable(priv->regmap, index, false);
0490     } else {
0491         if (dc_time_on == period)
0492             dc_time_on = 0;
0493 
0494         aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
0495                             dc_time_on);
0496         aspeed_set_pwm_port_enable(priv->regmap, index, true);
0497     }
0498 }
0499 
0500 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
0501                          *priv, u8 type)
0502 {
0503     u32 clk;
0504     u16 tacho_unit;
0505     u8 clk_unit, div_h, div_l, tacho_div;
0506 
0507     clk = priv->clk_freq;
0508     clk_unit = priv->type_pwm_clock_unit[type];
0509     div_h = priv->type_pwm_clock_division_h[type];
0510     div_h = 0x1 << div_h;
0511     div_l = priv->type_pwm_clock_division_l[type];
0512     if (div_l == 0)
0513         div_l = 1;
0514     else
0515         div_l = div_l * 2;
0516 
0517     tacho_unit = priv->type_fan_tach_unit[type];
0518     tacho_div = priv->type_fan_tach_clock_division[type];
0519 
0520     tacho_div = 0x4 << (tacho_div * 2);
0521     return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
0522 }
0523 
0524 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
0525                       u8 fan_tach_ch)
0526 {
0527     u32 raw_data, tach_div, clk_source, msec, usec, val;
0528     u8 fan_tach_ch_source, type, mode, both;
0529     int ret;
0530 
0531     regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
0532     regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
0533 
0534     fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
0535     type = priv->pwm_port_type[fan_tach_ch_source];
0536 
0537     msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
0538     usec = msec * 1000;
0539 
0540     ret = regmap_read_poll_timeout(
0541         priv->regmap,
0542         ASPEED_PTCR_RESULT,
0543         val,
0544         (val & RESULT_STATUS_MASK),
0545         ASPEED_RPM_STATUS_SLEEP_USEC,
0546         usec);
0547 
0548     /* return -ETIMEDOUT if we didn't get an answer. */
0549     if (ret)
0550         return ret;
0551 
0552     raw_data = val & RESULT_VALUE_MASK;
0553     tach_div = priv->type_fan_tach_clock_division[type];
0554     /*
0555      * We need the mode to determine if the raw_data is double (from
0556      * counting both edges).
0557      */
0558     mode = priv->type_fan_tach_mode[type];
0559     both = (mode & BOTH_EDGES) ? 1 : 0;
0560 
0561     tach_div = (0x4 << both) << (tach_div * 2);
0562     clk_source = priv->clk_freq;
0563 
0564     if (raw_data == 0)
0565         return 0;
0566 
0567     return (clk_source * 60) / (2 * raw_data * tach_div);
0568 }
0569 
0570 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
0571              const char *buf, size_t count)
0572 {
0573     struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
0574     int index = sensor_attr->index;
0575     int ret;
0576     struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
0577     long fan_ctrl;
0578 
0579     ret = kstrtol(buf, 10, &fan_ctrl);
0580     if (ret != 0)
0581         return ret;
0582 
0583     if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
0584         return -EINVAL;
0585 
0586     if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
0587         return count;
0588 
0589     priv->pwm_port_fan_ctrl[index] = fan_ctrl;
0590     aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
0591 
0592     return count;
0593 }
0594 
0595 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
0596             char *buf)
0597 {
0598     struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
0599     int index = sensor_attr->index;
0600     struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
0601 
0602     return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
0603 }
0604 
0605 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr,
0606             char *buf)
0607 {
0608     struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
0609     int index = sensor_attr->index;
0610     int rpm;
0611     struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
0612 
0613     rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
0614     if (rpm < 0)
0615         return rpm;
0616 
0617     return sprintf(buf, "%d\n", rpm);
0618 }
0619 
0620 static umode_t pwm_is_visible(struct kobject *kobj,
0621                   struct attribute *a, int index)
0622 {
0623     struct device *dev = kobj_to_dev(kobj);
0624     struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
0625 
0626     if (!priv->pwm_present[index])
0627         return 0;
0628     return a->mode;
0629 }
0630 
0631 static umode_t fan_dev_is_visible(struct kobject *kobj,
0632                   struct attribute *a, int index)
0633 {
0634     struct device *dev = kobj_to_dev(kobj);
0635     struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
0636 
0637     if (!priv->fan_tach_present[index])
0638         return 0;
0639     return a->mode;
0640 }
0641 
0642 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
0643 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
0644 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
0645 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
0646 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4);
0647 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5);
0648 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6);
0649 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7);
0650 static struct attribute *pwm_dev_attrs[] = {
0651     &sensor_dev_attr_pwm1.dev_attr.attr,
0652     &sensor_dev_attr_pwm2.dev_attr.attr,
0653     &sensor_dev_attr_pwm3.dev_attr.attr,
0654     &sensor_dev_attr_pwm4.dev_attr.attr,
0655     &sensor_dev_attr_pwm5.dev_attr.attr,
0656     &sensor_dev_attr_pwm6.dev_attr.attr,
0657     &sensor_dev_attr_pwm7.dev_attr.attr,
0658     &sensor_dev_attr_pwm8.dev_attr.attr,
0659     NULL,
0660 };
0661 
0662 static const struct attribute_group pwm_dev_group = {
0663     .attrs = pwm_dev_attrs,
0664     .is_visible = pwm_is_visible,
0665 };
0666 
0667 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
0668 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1);
0669 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2);
0670 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3);
0671 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4);
0672 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5);
0673 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6);
0674 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7);
0675 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8);
0676 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9);
0677 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10);
0678 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11);
0679 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12);
0680 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13);
0681 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14);
0682 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15);
0683 static struct attribute *fan_dev_attrs[] = {
0684     &sensor_dev_attr_fan1_input.dev_attr.attr,
0685     &sensor_dev_attr_fan2_input.dev_attr.attr,
0686     &sensor_dev_attr_fan3_input.dev_attr.attr,
0687     &sensor_dev_attr_fan4_input.dev_attr.attr,
0688     &sensor_dev_attr_fan5_input.dev_attr.attr,
0689     &sensor_dev_attr_fan6_input.dev_attr.attr,
0690     &sensor_dev_attr_fan7_input.dev_attr.attr,
0691     &sensor_dev_attr_fan8_input.dev_attr.attr,
0692     &sensor_dev_attr_fan9_input.dev_attr.attr,
0693     &sensor_dev_attr_fan10_input.dev_attr.attr,
0694     &sensor_dev_attr_fan11_input.dev_attr.attr,
0695     &sensor_dev_attr_fan12_input.dev_attr.attr,
0696     &sensor_dev_attr_fan13_input.dev_attr.attr,
0697     &sensor_dev_attr_fan14_input.dev_attr.attr,
0698     &sensor_dev_attr_fan15_input.dev_attr.attr,
0699     &sensor_dev_attr_fan16_input.dev_attr.attr,
0700     NULL
0701 };
0702 
0703 static const struct attribute_group fan_dev_group = {
0704     .attrs = fan_dev_attrs,
0705     .is_visible = fan_dev_is_visible,
0706 };
0707 
0708 /*
0709  * The clock type is type M :
0710  * The PWM frequency = 24MHz / (type M clock division L bit *
0711  * type M clock division H bit * (type M PWM period bit + 1))
0712  */
0713 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
0714 {
0715     priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
0716     priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
0717     priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
0718     aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
0719                     M_PWM_DIV_L, M_PWM_PERIOD);
0720     aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
0721     priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
0722     priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
0723     priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
0724     aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
0725                      M_TACH_UNIT, M_TACH_CLK_DIV);
0726 }
0727 
0728 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
0729                    u8 pwm_port)
0730 {
0731     aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
0732     priv->pwm_present[pwm_port] = true;
0733 
0734     priv->pwm_port_type[pwm_port] = TYPEM;
0735     aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
0736 
0737     priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
0738     aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
0739 }
0740 
0741 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
0742                        u8 *fan_tach_ch,
0743                        int count,
0744                        u8 pwm_source)
0745 {
0746     u8 val, index;
0747 
0748     for (val = 0; val < count; val++) {
0749         index = fan_tach_ch[val];
0750         aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
0751         priv->fan_tach_present[index] = true;
0752         priv->fan_tach_ch_source[index] = pwm_source;
0753         aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
0754     }
0755 }
0756 
0757 static int
0758 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
0759                 unsigned long *state)
0760 {
0761     struct aspeed_cooling_device *cdev = tcdev->devdata;
0762 
0763     *state = cdev->max_state;
0764 
0765     return 0;
0766 }
0767 
0768 static int
0769 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
0770                 unsigned long *state)
0771 {
0772     struct aspeed_cooling_device *cdev = tcdev->devdata;
0773 
0774     *state = cdev->cur_state;
0775 
0776     return 0;
0777 }
0778 
0779 static int
0780 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
0781                 unsigned long state)
0782 {
0783     struct aspeed_cooling_device *cdev = tcdev->devdata;
0784 
0785     if (state > cdev->max_state)
0786         return -EINVAL;
0787 
0788     cdev->cur_state = state;
0789     cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
0790                     cdev->cooling_levels[cdev->cur_state];
0791     aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
0792                      cdev->cooling_levels[cdev->cur_state]);
0793 
0794     return 0;
0795 }
0796 
0797 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
0798     .get_max_state = aspeed_pwm_cz_get_max_state,
0799     .get_cur_state = aspeed_pwm_cz_get_cur_state,
0800     .set_cur_state = aspeed_pwm_cz_set_cur_state,
0801 };
0802 
0803 static int aspeed_create_pwm_cooling(struct device *dev,
0804                      struct device_node *child,
0805                      struct aspeed_pwm_tacho_data *priv,
0806                      u32 pwm_port, u8 num_levels)
0807 {
0808     int ret;
0809     struct aspeed_cooling_device *cdev;
0810 
0811     cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
0812 
0813     if (!cdev)
0814         return -ENOMEM;
0815 
0816     cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
0817     if (!cdev->cooling_levels)
0818         return -ENOMEM;
0819 
0820     cdev->max_state = num_levels - 1;
0821     ret = of_property_read_u8_array(child, "cooling-levels",
0822                     cdev->cooling_levels,
0823                     num_levels);
0824     if (ret) {
0825         dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
0826         return ret;
0827     }
0828     snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
0829 
0830     cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
0831                     cdev->name, cdev, &aspeed_pwm_cool_ops);
0832     if (IS_ERR(cdev->tcdev))
0833         return PTR_ERR(cdev->tcdev);
0834 
0835     cdev->priv = priv;
0836     cdev->pwm_port = pwm_port;
0837 
0838     priv->cdev[pwm_port] = cdev;
0839 
0840     return 0;
0841 }
0842 
0843 static int aspeed_create_fan(struct device *dev,
0844                  struct device_node *child,
0845                  struct aspeed_pwm_tacho_data *priv)
0846 {
0847     u8 *fan_tach_ch;
0848     u32 pwm_port;
0849     int ret, count;
0850 
0851     ret = of_property_read_u32(child, "reg", &pwm_port);
0852     if (ret)
0853         return ret;
0854     if (pwm_port >= ARRAY_SIZE(pwm_port_params))
0855         return -EINVAL;
0856     aspeed_create_pwm_port(priv, (u8)pwm_port);
0857 
0858     ret = of_property_count_u8_elems(child, "cooling-levels");
0859 
0860     if (ret > 0) {
0861         ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
0862                         ret);
0863         if (ret)
0864             return ret;
0865     }
0866 
0867     count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
0868     if (count < 1)
0869         return -EINVAL;
0870     fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
0871                    GFP_KERNEL);
0872     if (!fan_tach_ch)
0873         return -ENOMEM;
0874     ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
0875                     fan_tach_ch, count);
0876     if (ret)
0877         return ret;
0878     aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
0879 
0880     return 0;
0881 }
0882 
0883 static void aspeed_pwm_tacho_remove(void *data)
0884 {
0885     struct aspeed_pwm_tacho_data *priv = data;
0886 
0887     reset_control_assert(priv->rst);
0888 }
0889 
0890 static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
0891 {
0892     struct device *dev = &pdev->dev;
0893     struct device_node *np, *child;
0894     struct aspeed_pwm_tacho_data *priv;
0895     void __iomem *regs;
0896     struct device *hwmon;
0897     struct clk *clk;
0898     int ret;
0899 
0900     np = dev->of_node;
0901     regs = devm_platform_ioremap_resource(pdev, 0);
0902     if (IS_ERR(regs))
0903         return PTR_ERR(regs);
0904     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0905     if (!priv)
0906         return -ENOMEM;
0907     priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
0908             &aspeed_pwm_tacho_regmap_config);
0909     if (IS_ERR(priv->regmap))
0910         return PTR_ERR(priv->regmap);
0911 
0912     priv->rst = devm_reset_control_get_exclusive(dev, NULL);
0913     if (IS_ERR(priv->rst)) {
0914         dev_err(dev,
0915             "missing or invalid reset controller device tree entry");
0916         return PTR_ERR(priv->rst);
0917     }
0918     reset_control_deassert(priv->rst);
0919 
0920     ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
0921     if (ret)
0922         return ret;
0923 
0924     regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
0925     regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
0926 
0927     clk = devm_clk_get(dev, NULL);
0928     if (IS_ERR(clk))
0929         return -ENODEV;
0930     priv->clk_freq = clk_get_rate(clk);
0931     aspeed_set_clock_enable(priv->regmap, true);
0932     aspeed_set_clock_source(priv->regmap, 0);
0933 
0934     aspeed_create_type(priv);
0935 
0936     for_each_child_of_node(np, child) {
0937         ret = aspeed_create_fan(dev, child, priv);
0938         if (ret) {
0939             of_node_put(child);
0940             return ret;
0941         }
0942     }
0943 
0944     priv->groups[0] = &pwm_dev_group;
0945     priv->groups[1] = &fan_dev_group;
0946     priv->groups[2] = NULL;
0947     hwmon = devm_hwmon_device_register_with_groups(dev,
0948                                "aspeed_pwm_tacho",
0949                                priv, priv->groups);
0950     return PTR_ERR_OR_ZERO(hwmon);
0951 }
0952 
0953 static const struct of_device_id of_pwm_tacho_match_table[] = {
0954     { .compatible = "aspeed,ast2400-pwm-tacho", },
0955     { .compatible = "aspeed,ast2500-pwm-tacho", },
0956     {},
0957 };
0958 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
0959 
0960 static struct platform_driver aspeed_pwm_tacho_driver = {
0961     .probe      = aspeed_pwm_tacho_probe,
0962     .driver     = {
0963         .name   = "aspeed_pwm_tacho",
0964         .of_match_table = of_pwm_tacho_match_table,
0965     },
0966 };
0967 
0968 module_platform_driver(aspeed_pwm_tacho_driver);
0969 
0970 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
0971 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
0972 MODULE_LICENSE("GPL");
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