hsi/controllers/omap_ssi_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Hardware definitions for SSI.
0003  *
0004  * Copyright (C) 2010 Nokia Corporation. All rights reserved.
0005  *
0006  * Contact: Carlos Chinea <carlos.chinea@nokia.com>
0007  */
0008
0009 #ifndef __OMAP_SSI_REGS_H__
0010 #define __OMAP_SSI_REGS_H__
0011
0012 /*
0013  * SSI SYS registers
0014  */
0015 #define SSI_REVISION_REG    0
0016 #  define SSI_REV_MAJOR    0xf0
0017 #  define SSI_REV_MINOR    0xf
0018 #define SSI_SYSCONFIG_REG    0x10
0019 #  define SSI_AUTOIDLE    (1 << 0)
0020 #  define SSI_SOFTRESET    (1 << 1)
0021 #  define SSI_SIDLEMODE_FORCE  0
0022 #  define SSI_SIDLEMODE_NO    (1 << 3)
0023 #  define SSI_SIDLEMODE_SMART  (1 << 4)
0024 #  define SSI_SIDLEMODE_MASK  0x18
0025 #  define SSI_MIDLEMODE_FORCE  0
0026 #  define SSI_MIDLEMODE_NO    (1 << 12)
0027 #  define SSI_MIDLEMODE_SMART  (1 << 13)
0028 #  define SSI_MIDLEMODE_MASK  0x3000
0029 #define SSI_SYSSTATUS_REG    0x14
0030 #  define SSI_RESETDONE    1
0031 #define SSI_MPU_STATUS_REG(port, irq)  (0x808 + ((port) * 0x10) + ((irq) * 2))
0032 #define SSI_MPU_ENABLE_REG(port, irq)  (0x80c + ((port) * 0x10) + ((irq) * 8))
0033 #  define SSI_DATAACCEPT(channel)    (1 << (channel))
0034 #  define SSI_DATAAVAILABLE(channel)  (1 << ((channel) + 8))
0035 #  define SSI_DATAOVERRUN(channel)    (1 << ((channel) + 16))
0036 #  define SSI_ERROROCCURED      (1 << 24)
0037 #  define SSI_BREAKDETECTED    (1 << 25)
0038 #define SSI_GDD_MPU_IRQ_STATUS_REG  0x0800
0039 #define SSI_GDD_MPU_IRQ_ENABLE_REG  0x0804
0040 #  define SSI_GDD_LCH(channel)  (1 << (channel))
0041 #define SSI_WAKE_REG(port)    (0xc00 + ((port) * 0x10))
0042 #define SSI_CLEAR_WAKE_REG(port)  (0xc04 + ((port) * 0x10))
0043 #define SSI_SET_WAKE_REG(port)    (0xc08 + ((port) * 0x10))
0044 #  define SSI_WAKE(channel)  (1 << (channel))
0045 #  define SSI_WAKE_MASK    0xff
0046
0047 /*
0048  * SSI SST registers
0049  */
0050 #define SSI_SST_ID_REG      0
0051 #define SSI_SST_MODE_REG    4
0052 #  define SSI_MODE_VAL_MASK  3
0053 #  define SSI_MODE_SLEEP    0
0054 #  define SSI_MODE_STREAM    1
0055 #  define SSI_MODE_FRAME    2
0056 #  define SSI_MODE_MULTIPOINTS  3
0057 #define SSI_SST_FRAMESIZE_REG    8
0058 #  define SSI_FRAMESIZE_DEFAULT  31
0059 #define SSI_SST_TXSTATE_REG    0xc
0060 #  define  SSI_TXSTATE_IDLE  0
0061 #define SSI_SST_BUFSTATE_REG    0x10
0062 #  define  SSI_FULL(channel)  (1 << (channel))
0063 #define SSI_SST_DIVISOR_REG    0x18
0064 #  define SSI_MAX_DIVISOR    127
0065 #define SSI_SST_BREAK_REG    0x20
0066 #define SSI_SST_CHANNELS_REG    0x24
0067 #  define SSI_CHANNELS_DEFAULT  4
0068 #define SSI_SST_ARBMODE_REG    0x28
0069 #  define SSI_ARBMODE_ROUNDROBIN  0
0070 #  define SSI_ARBMODE_PRIORITY  1
0071 #define SSI_SST_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
0072 #define SSI_SST_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
0073
0074 /*
0075  * SSI SSR registers
0076  */
0077 #define SSI_SSR_ID_REG      0
0078 #define SSI_SSR_MODE_REG    4
0079 #define SSI_SSR_FRAMESIZE_REG    8
0080 #define SSI_SSR_RXSTATE_REG    0xc
0081 #define SSI_SSR_BUFSTATE_REG    0x10
0082 #  define SSI_NOTEMPTY(channel)  (1 << (channel))
0083 #define SSI_SSR_BREAK_REG    0x1c
0084 #define SSI_SSR_ERROR_REG    0x20
0085 #define SSI_SSR_ERRORACK_REG    0x24
0086 #define SSI_SSR_OVERRUN_REG    0x2c
0087 #define SSI_SSR_OVERRUNACK_REG    0x30
0088 #define SSI_SSR_TIMEOUT_REG    0x34
0089 #  define SSI_TIMEOUT_DEFAULT  0
0090 #define SSI_SSR_CHANNELS_REG    0x28
0091 #define SSI_SSR_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
0092 #define SSI_SSR_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
0093
0094 /*
0095  * SSI GDD registers
0096  */
0097 #define SSI_GDD_HW_ID_REG    0
0098 #define SSI_GDD_PPORT_ID_REG    0x10
0099 #define SSI_GDD_MPORT_ID_REG    0x14
0100 #define SSI_GDD_PPORT_SR_REG    0x20
0101 #define SSI_GDD_MPORT_SR_REG    0x24
0102 #  define SSI_ACTIVE_LCH_NUM_MASK  0xff
0103 #define SSI_GDD_TEST_REG    0x40
0104 #  define SSI_TEST      1
0105 #define SSI_GDD_GCR_REG      0x100
0106 #  define  SSI_CLK_AUTOGATING_ON  (1 << 3)
0107 #  define  SSI_FREE    (1 << 2)
0108 #  define  SSI_SWITCH_OFF    (1 << 0)
0109 #define SSI_GDD_GRST_REG    0x200
0110 #  define SSI_SWRESET    1
0111 #define SSI_GDD_CSDP_REG(channel)  (0x800 + ((channel) * 0x40))
0112 #  define SSI_DST_BURST_EN_MASK  0xc000
0113 #  define SSI_DST_SINGLE_ACCESS0  0
0114 #  define SSI_DST_SINGLE_ACCESS  (1 << 14)
0115 #  define SSI_DST_BURST_4x32_BIT  (2 << 14)
0116 #  define SSI_DST_BURST_8x32_BIT  (3 << 14)
0117 #  define SSI_DST_MASK    0x1e00
0118 #  define SSI_DST_MEMORY_PORT  (8 << 9)
0119 #  define SSI_DST_PERIPHERAL_PORT  (9 << 9)
0120 #  define SSI_SRC_BURST_EN_MASK  0x180
0121 #  define SSI_SRC_SINGLE_ACCESS0  0
0122 #  define SSI_SRC_SINGLE_ACCESS  (1 << 7)
0123 #  define SSI_SRC_BURST_4x32_BIT  (2 << 7)
0124 #  define SSI_SRC_BURST_8x32_BIT  (3 << 7)
0125 #  define SSI_SRC_MASK    0x3c
0126 #  define SSI_SRC_MEMORY_PORT  (8 << 2)
0127 #  define SSI_SRC_PERIPHERAL_PORT  (9 << 2)
0128 #  define SSI_DATA_TYPE_MASK  3
0129 #  define SSI_DATA_TYPE_S32  2
0130 #define SSI_GDD_CCR_REG(channel)  (0x802 + ((channel) * 0x40))
0131 #  define SSI_DST_AMODE_MASK  (3 << 14)
0132 #  define SSI_DST_AMODE_CONST  0
0133 #  define SSI_DST_AMODE_POSTINC  (1 << 12)
0134 #  define SSI_SRC_AMODE_MASK  (3 << 12)
0135 #  define SSI_SRC_AMODE_CONST  0
0136 #  define SSI_SRC_AMODE_POSTINC  (1 << 12)
0137 #  define SSI_CCR_ENABLE    (1 << 7)
0138 #  define SSI_CCR_SYNC_MASK  0x1f
0139 #define SSI_GDD_CICR_REG(channel)  (0x804 + ((channel) * 0x40))
0140 #  define SSI_BLOCK_IE    (1 << 5)
0141 #  define SSI_HALF_IE    (1 << 2)
0142 #  define SSI_TOUT_IE    (1 << 0)
0143 #define SSI_GDD_CSR_REG(channel)  (0x806 + ((channel) * 0x40))
0144 #  define SSI_CSR_SYNC    (1 << 6)
0145 #  define SSI_CSR_BLOCK    (1 << 5)
0146 #  define SSI_CSR_HALF    (1 << 2)
0147 #  define SSI_CSR_TOUR    (1 << 0)
0148 #define SSI_GDD_CSSA_REG(channel)  (0x808 + ((channel) * 0x40))
0149 #define SSI_GDD_CDSA_REG(channel)  (0x80c + ((channel) * 0x40))
0150 #define SSI_GDD_CEN_REG(channel)  (0x810 + ((channel) * 0x40))
0151 #define SSI_GDD_CSAC_REG(channel)  (0x818 + ((channel) * 0x40))
0152 #define SSI_GDD_CDAC_REG(channel)  (0x81a + ((channel) * 0x40))
0153 #define SSI_GDD_CLNK_CTRL_REG(channel)  (0x828 + ((channel) * 0x40))
0154 #  define SSI_ENABLE_LNK    (1 << 15)
0155 #  define SSI_STOP_LNK    (1 << 14)
0156 #  define SSI_NEXT_CH_ID_MASK  0xf
0157
0158 #endif /* __OMAP_SSI_REGS_H__ */