intel-ish-hid/ishtp/ishtp-dev.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Most ISHTP provider device and ISHTP logic declarations
0004  *
0005  * Copyright (c) 2003-2016, Intel Corporation.
0006  */
0007
0008 #ifndef _ISHTP_DEV_H_
0009 #define _ISHTP_DEV_H_
0010
0011 #include <linux/types.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/intel-ish-client-if.h>
0014 #include "bus.h"
0015 #include "hbm.h"
0016
0017 #define IPC_PAYLOAD_SIZE    128
0018 #define ISHTP_RD_MSG_BUF_SIZE   IPC_PAYLOAD_SIZE
0019 #define IPC_FULL_MSG_SIZE   132
0020
0021 /* Number of messages to be held in ISR->BH FIFO */
0022 #define RD_INT_FIFO_SIZE    64
0023
0024 /*
0025  * Number of IPC messages to be held in Tx FIFO, to be sent by ISR -
0026  * Tx complete interrupt or RX_COMPLETE handler
0027  */
0028 #define IPC_TX_FIFO_SIZE    512
0029
0030 /*
0031  * Number of Maximum ISHTP Clients
0032  */
0033 #define ISHTP_CLIENTS_MAX 256
0034
0035 /*
0036  * Number of File descriptors/handles
0037  * that can be opened to the driver.
0038  *
0039  * Limit to 255: 256 Total Clients
0040  * minus internal client for ISHTP Bus Messages
0041  */
0042 #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1)
0043
0044 /* Internal Clients Number */
0045 #define ISHTP_HOST_CLIENT_ID_ANY        (-1)
0046 #define ISHTP_HBM_HOST_CLIENT_ID        0
0047
0048 #define MAX_DMA_DELAY   20
0049
0050 /* ISHTP device states */
0051 enum ishtp_dev_state {
0052     ISHTP_DEV_INITIALIZING = 0,
0053     ISHTP_DEV_INIT_CLIENTS,
0054     ISHTP_DEV_ENABLED,
0055     ISHTP_DEV_RESETTING,
0056     ISHTP_DEV_DISABLED,
0057     ISHTP_DEV_POWER_DOWN,
0058     ISHTP_DEV_POWER_UP
0059 };
0060 const char *ishtp_dev_state_str(int state);
0061
0062 struct ishtp_cl;
0063
0064 /**
0065  * struct ishtp_fw_client - representation of fw client
0066  *
0067  * @props - client properties
0068  * @client_id - fw client id
0069  */
0070 struct ishtp_fw_client {
0071     struct ishtp_client_properties props;
0072     uint8_t client_id;
0073 };
0074
0075 /*
0076  * Control info for IPC messages ISHTP/IPC sending FIFO -
0077  * list with inline data buffer
0078  * This structure will be filled with parameters submitted
0079  * by the caller glue layer
0080  * 'buf' may be pointing to the external buffer or to 'inline_data'
0081  * 'offset' will be initialized to 0 by submitting
0082  *
0083  * 'ipc_send_compl' is intended for use by clients that send fragmented
0084  * messages. When a fragment is sent down to IPC msg regs,
0085  * it will be called.
0086  * If it has more fragments to send, it will do it. With last fragment
0087  * it will send appropriate ISHTP "message-complete" flag.
0088  * It will remove the outstanding message
0089  * (mark outstanding buffer as available).
0090  * If counting flow control is in work and there are more flow control
0091  * credits, it can put the next client message queued in cl.
0092  * structure for IPC processing.
0093  *
0094  */
0095 struct wr_msg_ctl_info {
0096     /* Will be called with 'ipc_send_compl_prm' as parameter */
0097     void (*ipc_send_compl)(void *);
0098
0099     void *ipc_send_compl_prm;
0100     size_t length;
0101     struct list_head    link;
0102     unsigned char   inline_data[IPC_FULL_MSG_SIZE];
0103 };
0104
0105 /*
0106  * The ISHTP layer talks to hardware IPC message using the following
0107  * callbacks
0108  */
0109 struct ishtp_hw_ops {
0110     int (*hw_reset)(struct ishtp_device *dev);
0111     int (*ipc_reset)(struct ishtp_device *dev);
0112     uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length,
0113                    int busy);
0114     int (*write)(struct ishtp_device *dev,
0115         void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
0116         unsigned char *msg, int length);
0117     uint32_t    (*ishtp_read_hdr)(const struct ishtp_device *dev);
0118     int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer,
0119             unsigned long buffer_length);
0120     uint32_t    (*get_fw_status)(struct ishtp_device *dev);
0121     void    (*sync_fw_clock)(struct ishtp_device *dev);
0122     bool    (*dma_no_cache_snooping)(struct ishtp_device *dev);
0123 };
0124
0125 /**
0126  * struct ishtp_device - ISHTP private device struct
0127  */
0128 struct ishtp_device {
0129     struct device *devc;    /* pointer to lowest device */
0130     struct pci_dev *pdev;   /* PCI device to get device ids */
0131
0132     /* waitq for waiting for suspend response */
0133     wait_queue_head_t suspend_wait;
0134     bool suspend_flag;  /* Suspend is active */
0135
0136     /* waitq for waiting for resume response */
0137     wait_queue_head_t resume_wait;
0138     bool resume_flag;   /*Resume is active */
0139
0140     /*
0141      * lock for the device, for everything that doesn't have
0142      * a dedicated spinlock
0143      */
0144     spinlock_t device_lock;
0145
0146     bool recvd_hw_ready;
0147     struct hbm_version version;
0148     int transfer_path; /* Choice of transfer path: IPC or DMA */
0149
0150     /* ishtp device states */
0151     enum ishtp_dev_state dev_state;
0152     enum ishtp_hbm_state hbm_state;
0153
0154     /* driver read queue */
0155     struct ishtp_cl_rb read_list;
0156     spinlock_t read_list_spinlock;
0157
0158     /* list of ishtp_cl's */
0159     struct list_head cl_list;
0160     spinlock_t cl_list_lock;
0161     long open_handle_count;
0162
0163     /* List of bus devices */
0164     struct list_head device_list;
0165     spinlock_t device_list_lock;
0166
0167     /* waiting queues for receive message from FW */
0168     wait_queue_head_t wait_hw_ready;
0169     wait_queue_head_t wait_hbm_recvd_msg;
0170
0171     /* FIFO for input messages for BH processing */
0172     unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE];
0173     unsigned int rd_msg_fifo_head, rd_msg_fifo_tail;
0174     spinlock_t rd_msg_spinlock;
0175     struct work_struct bh_hbm_work;
0176
0177     /* IPC write queue */
0178     struct list_head wr_processing_list, wr_free_list;
0179     /* For both processing list  and free list */
0180     spinlock_t wr_processing_spinlock;
0181
0182     struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/
0183     DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX);
0184     DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX);
0185     uint8_t fw_clients_num;
0186     uint8_t fw_client_presentation_num;
0187     uint8_t fw_client_index;
0188     spinlock_t fw_clients_lock;
0189
0190     /* TX DMA buffers and slots */
0191     int ishtp_host_dma_enabled;
0192     void *ishtp_host_dma_tx_buf;
0193     unsigned int ishtp_host_dma_tx_buf_size;
0194     uint64_t ishtp_host_dma_tx_buf_phys;
0195     int ishtp_dma_num_slots;
0196
0197     /* map of 4k blocks in Tx dma buf: 0-free, 1-used */
0198     uint8_t *ishtp_dma_tx_map;
0199     spinlock_t ishtp_dma_tx_lock;
0200
0201     /* RX DMA buffers and slots */
0202     void *ishtp_host_dma_rx_buf;
0203     unsigned int ishtp_host_dma_rx_buf_size;
0204     uint64_t ishtp_host_dma_rx_buf_phys;
0205
0206     /* Dump to trace buffers if enabled*/
0207     ishtp_print_log print_log;
0208
0209     /* Debug stats */
0210     unsigned int    ipc_rx_cnt;
0211     unsigned long long  ipc_rx_bytes_cnt;
0212     unsigned int    ipc_tx_cnt;
0213     unsigned long long  ipc_tx_bytes_cnt;
0214
0215     const struct ishtp_hw_ops *ops;
0216     size_t  mtu;
0217     uint32_t    ishtp_msg_hdr;
0218     char hw[] __aligned(sizeof(void *));
0219 };
0220
0221 static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec)
0222 {
0223     return msecs_to_jiffies(sec * MSEC_PER_SEC);
0224 }
0225
0226 /*
0227  * Register Access Function
0228  */
0229 static inline int ish_ipc_reset(struct ishtp_device *dev)
0230 {
0231     return dev->ops->ipc_reset(dev);
0232 }
0233
0234 /* Exported function */
0235 void    ishtp_device_init(struct ishtp_device *dev);
0236 int ishtp_start(struct ishtp_device *dev);
0237
0238 #endif /*_ISHTP_DEV_H_*/