intel-ish-hid/ipc/hw-ish.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * H/W layer of ISHTP provider device (ISH)
0004  *
0005  * Copyright (c) 2014-2016, Intel Corporation.
0006  */
0007
0008 #ifndef _ISHTP_HW_ISH_H_
0009 #define _ISHTP_HW_ISH_H_
0010
0011 #include <linux/pci.h>
0012 #include <linux/interrupt.h>
0013 #include "hw-ish-regs.h"
0014 #include "ishtp-dev.h"
0015
0016 #define CHV_DEVICE_ID       0x22D8
0017 #define BXT_Ax_DEVICE_ID    0x0AA2
0018 #define BXT_Bx_DEVICE_ID    0x1AA2
0019 #define APL_Ax_DEVICE_ID    0x5AA2
0020 #define SPT_Ax_DEVICE_ID    0x9D35
0021 #define CNL_Ax_DEVICE_ID    0x9DFC
0022 #define GLK_Ax_DEVICE_ID    0x31A2
0023 #define CNL_H_DEVICE_ID     0xA37C
0024 #define ICL_MOBILE_DEVICE_ID    0x34FC
0025 #define SPT_H_DEVICE_ID     0xA135
0026 #define CML_LP_DEVICE_ID    0x02FC
0027 #define CMP_H_DEVICE_ID     0x06FC
0028 #define EHL_Ax_DEVICE_ID    0x4BB3
0029 #define TGL_LP_DEVICE_ID    0xA0FC
0030 #define TGL_H_DEVICE_ID     0x43FC
0031 #define ADL_S_DEVICE_ID     0x7AF8
0032 #define ADL_P_DEVICE_ID     0x51FC
0033 #define ADL_N_DEVICE_ID     0x54FC
0034 #define RPL_S_DEVICE_ID     0x7A78
0035 #define MTL_P_DEVICE_ID     0x7E45
0036
0037 #define REVISION_ID_CHT_A0  0x6
0038 #define REVISION_ID_CHT_Ax_SI   0x0
0039 #define REVISION_ID_CHT_Bx_SI   0x10
0040 #define REVISION_ID_CHT_Kx_SI   0x20
0041 #define REVISION_ID_CHT_Dx_SI   0x30
0042 #define REVISION_ID_CHT_B0  0xB0
0043 #define REVISION_ID_SI_MASK 0x70
0044
0045 struct ipc_rst_payload_type {
0046     uint16_t    reset_id;
0047     uint16_t    reserved;
0048 };
0049
0050 struct time_sync_format {
0051     uint8_t ts1_source;
0052     uint8_t ts2_source;
0053     uint16_t reserved;
0054 } __packed;
0055
0056 struct ipc_time_update_msg {
0057     uint64_t primary_host_time;
0058     struct time_sync_format sync_info;
0059     uint64_t secondary_host_time;
0060 } __packed;
0061
0062 enum {
0063     HOST_UTC_TIME_USEC = 0,
0064     HOST_SYSTEM_TIME_USEC = 1
0065 };
0066
0067 struct ish_hw {
0068     void __iomem *mem_addr;
0069 };
0070
0071 /*
0072  * ISH FW status type
0073  */
0074 enum {
0075     FWSTS_AFTER_RESET       = 0,
0076     FWSTS_WAIT_FOR_HOST     = 4,
0077     FWSTS_START_KERNEL_DMA      = 5,
0078     FWSTS_FW_IS_RUNNING     = 7,
0079     FWSTS_SENSOR_APP_LOADED     = 8,
0080     FWSTS_SENSOR_APP_RUNNING    = 15
0081 };
0082
0083 #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
0084
0085 irqreturn_t ish_irq_handler(int irq, void *dev_id);
0086 struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
0087 int ish_hw_start(struct ishtp_device *dev);
0088 void ish_device_disable(struct ishtp_device *dev);
0089 int ish_disable_dma(struct ishtp_device *dev);
0090 void ish_set_host_ready(struct ishtp_device *dev);
0091
0092 #endif /* _ISHTP_HW_ISH_H_ */