intel-ish-hid/ipc/hw-ish-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ISH registers definitions
0004  *
0005  * Copyright (c) 2012-2016, Intel Corporation.
0006  */
0007
0008 #ifndef _ISHTP_ISH_REGS_H_
0009 #define _ISHTP_ISH_REGS_H_
0010
0011
0012 /*** IPC PCI Offsets and sizes ***/
0013 /* ISH IPC Base Address */
0014 #define IPC_REG_BASE        0x0000
0015 /* Peripheral Interrupt Status Register */
0016 #define IPC_REG_PISR_CHV_AB      (IPC_REG_BASE + 0x00)
0017 /* Peripheral Interrupt Mask Register */
0018 #define IPC_REG_PIMR_CHV_AB      (IPC_REG_BASE + 0x04)
0019 /*BXT, CHV_K0*/
0020 /*Peripheral Interrupt Status Register */
0021 #define IPC_REG_PISR_BXT     (IPC_REG_BASE + 0x0C)
0022 /*Peripheral Interrupt Mask Register */
0023 #define IPC_REG_PIMR_BXT     (IPC_REG_BASE + 0x08)
0024 /***********************************/
0025 /* ISH Host Firmware status Register */
0026 #define IPC_REG_ISH_HOST_FWSTS  (IPC_REG_BASE + 0x34)
0027 /* Host Communication Register */
0028 #define IPC_REG_HOST_COMM   (IPC_REG_BASE + 0x38)
0029 /* Reset register */
0030 #define IPC_REG_ISH_RST     (IPC_REG_BASE + 0x44)
0031
0032 /* Inbound doorbell register Host to ISH */
0033 #define IPC_REG_HOST2ISH_DRBL   (IPC_REG_BASE + 0x48)
0034 /* Outbound doorbell register ISH to Host */
0035 #define IPC_REG_ISH2HOST_DRBL   (IPC_REG_BASE + 0x54)
0036 /* ISH to HOST message registers */
0037 #define IPC_REG_ISH2HOST_MSG    (IPC_REG_BASE + 0x60)
0038 /* HOST to ISH message registers */
0039 #define IPC_REG_HOST2ISH_MSG    (IPC_REG_BASE + 0xE0)
0040 /* REMAP2 to enable DMA (D3 RCR) */
0041 #define IPC_REG_ISH_RMP2    (IPC_REG_BASE + 0x368)
0042
0043 #define IPC_REG_MAX     (IPC_REG_BASE + 0x400)
0044
0045 /*** register bits - HISR ***/
0046 /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */
0047 #define IPC_INT_HOST2ISH_BIT            (1<<0)
0048 /***********************************/
0049 /*CHV_A0, CHV_B0*/
0050 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
0051 #define IPC_INT_ISH2HOST_BIT_CHV_AB (1<<3)
0052 /*BXT, CHV_K0*/
0053 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
0054 #define IPC_INT_ISH2HOST_BIT_BXT    (1<<0)
0055 /***********************************/
0056
0057 /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */
0058 #define IPC_INT_ISH2HOST_CLR_MASK_BIT   (1<<11)
0059
0060 /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
0061 #define IPC_INT_ISH2HOST_CLR_OFFS   (0)
0062
0063 /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
0064 #define IPC_INT_ISH2HOST_CLR_BIT    (1<<IPC_INT_ISH2HOST_CLR_OFFS)
0065
0066 /* bit corresponds busy bit in doorbell registers */
0067 #define IPC_DRBL_BUSY_OFFS      (31)
0068 #define IPC_DRBL_BUSY_BIT       (1<<IPC_DRBL_BUSY_OFFS)
0069
0070 #define IPC_HOST_OWNS_MSG_OFFS      (30)
0071
0072 /*
0073  * A0: bit means that host owns MSGnn registers and is reading them.
0074  * ISH FW may not write to them
0075  */
0076 #define IPC_HOST_OWNS_MSG_BIT       (1<<IPC_HOST_OWNS_MSG_OFFS)
0077
0078 /*
0079  * Host status bits (HOSTCOMM)
0080  */
0081 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
0082 #define IPC_HOSTCOMM_READY_OFFS     (7)
0083 #define IPC_HOSTCOMM_READY_BIT      (1<<IPC_HOSTCOMM_READY_OFFS)
0084
0085 /***********************************/
0086 /*CHV_A0, CHV_B0*/
0087 #define IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB (31)
0088 #define IPC_HOSTCOMM_INT_EN_BIT_CHV_AB      \
0089     (1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB)
0090 /*BXT, CHV_K0*/
0091 #define IPC_PIMR_INT_EN_OFFS_BXT    (0)
0092 #define IPC_PIMR_INT_EN_BIT_BXT     (1<<IPC_PIMR_INT_EN_OFFS_BXT)
0093
0094 #define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT    (8)
0095 #define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT     \
0096     (1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT)
0097 /***********************************/
0098 /*
0099  * both Host and ISH have ILUP at bit 0
0100  * bit corresponds host ready bit in both status registers
0101  */
0102 #define IPC_ILUP_OFFS           (0)
0103 #define IPC_ILUP_BIT            (1<<IPC_ILUP_OFFS)
0104
0105 /*
0106  * ISH FW status bits in ISH FW Status Register
0107  */
0108 #define IPC_ISH_FWSTS_SHIFT     12
0109 #define IPC_ISH_FWSTS_MASK      GENMASK(15, 12)
0110 #define IPC_GET_ISH_FWSTS(status)   \
0111     (((status) & IPC_ISH_FWSTS_MASK) >> IPC_ISH_FWSTS_SHIFT)
0112
0113 /*
0114  * FW status bits (relevant)
0115  */
0116 #define IPC_FWSTS_ILUP      0x1
0117 #define IPC_FWSTS_ISHTP_UP  (1<<1)
0118 #define IPC_FWSTS_DMA0      (1<<16)
0119 #define IPC_FWSTS_DMA1      (1<<17)
0120 #define IPC_FWSTS_DMA2      (1<<18)
0121 #define IPC_FWSTS_DMA3      (1<<19)
0122
0123 #define IPC_ISH_IN_DMA      \
0124     (IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3)
0125
0126 /* bit corresponds host ready bit in ISH FW Status Register */
0127 #define IPC_ISH_ISHTP_READY_OFFS        (1)
0128 #define IPC_ISH_ISHTP_READY_BIT     (1<<IPC_ISH_ISHTP_READY_OFFS)
0129
0130 #define IPC_RMP2_DMA_ENABLED    0x1 /* Value to enable DMA, per D3 RCR */
0131
0132 #define IPC_MSG_MAX_SIZE    0x80
0133
0134
0135 #define IPC_HEADER_LENGTH_MASK      0x03FF
0136 #define IPC_HEADER_PROTOCOL_MASK    0x0F
0137 #define IPC_HEADER_MNG_CMD_MASK     0x0F
0138
0139 #define IPC_HEADER_LENGTH_OFFSET    0
0140 #define IPC_HEADER_PROTOCOL_OFFSET  10
0141 #define IPC_HEADER_MNG_CMD_OFFSET   16
0142
0143 #define IPC_HEADER_GET_LENGTH(drbl_reg)     \
0144     (((drbl_reg) >> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK)
0145 #define IPC_HEADER_GET_PROTOCOL(drbl_reg)   \
0146     (((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK)
0147 #define IPC_HEADER_GET_MNG_CMD(drbl_reg)    \
0148     (((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK)
0149
0150 #define IPC_IS_BUSY(drbl_reg)           \
0151     (((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT))
0152
0153 /***********************************/
0154 /*CHV_A0, CHV_B0*/
0155 #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \
0156     (((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \
0157     ((u32)IPC_INT_ISH2HOST_BIT_CHV_AB))
0158 /*BXT, CHV_K0*/
0159 #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \
0160     (((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \
0161     ((u32)IPC_INT_ISH2HOST_BIT_BXT))
0162 /***********************************/
0163
0164 #define IPC_BUILD_HEADER(length, protocol, busy)        \
0165     (((busy)<<IPC_DRBL_BUSY_OFFS) |             \
0166     ((protocol) << IPC_HEADER_PROTOCOL_OFFSET) |        \
0167     ((length)<<IPC_HEADER_LENGTH_OFFSET))
0168
0169 #define IPC_BUILD_MNG_MSG(cmd, length)              \
0170     (((1)<<IPC_DRBL_BUSY_OFFS)|             \
0171     ((IPC_PROTOCOL_MNG)<<IPC_HEADER_PROTOCOL_OFFSET)|   \
0172     ((cmd)<<IPC_HEADER_MNG_CMD_OFFSET)|         \
0173      ((length)<<IPC_HEADER_LENGTH_OFFSET))
0174
0175
0176 #define IPC_SET_HOST_READY(host_status)     \
0177                 ((host_status) |= (IPC_HOSTCOMM_READY_BIT))
0178
0179 #define IPC_SET_HOST_ILUP(host_status)      \
0180                 ((host_status) |= (IPC_ILUP_BIT))
0181
0182 #define IPC_CLEAR_HOST_READY(host_status)   \
0183                 ((host_status) ^= (IPC_HOSTCOMM_READY_BIT))
0184
0185 #define IPC_CLEAR_HOST_ILUP(host_status)    \
0186                 ((host_status) ^= (IPC_ILUP_BIT))
0187
0188 /* todo - temp until PIMR HW ready */
0189 #define IPC_HOST_BUSY_READING_OFFS  6
0190
0191 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
0192 #define IPC_HOST_BUSY_READING_BIT   (1<<IPC_HOST_BUSY_READING_OFFS)
0193
0194 #define IPC_SET_HOST_BUSY_READING(host_status)  \
0195                 ((host_status) |= (IPC_HOST_BUSY_READING_BIT))
0196
0197 #define IPC_CLEAR_HOST_BUSY_READING(host_status)\
0198                 ((host_status) ^= (IPC_HOST_BUSY_READING_BIT))
0199
0200
0201 #define IPC_IS_ISH_ISHTP_READY(ish_status)  \
0202         (((ish_status) & IPC_ISH_ISHTP_READY_BIT) ==    \
0203             ((uint32_t)IPC_ISH_ISHTP_READY_BIT))
0204
0205 #define IPC_IS_ISH_ILUP(ish_status)     \
0206         (((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT))
0207
0208
0209 #define IPC_PROTOCOL_ISHTP      1
0210 #define IPC_PROTOCOL_MNG        3
0211
0212 #define MNG_RX_CMPL_ENABLE      0
0213 #define MNG_RX_CMPL_DISABLE     1
0214 #define MNG_RX_CMPL_INDICATION      2
0215 #define MNG_RESET_NOTIFY        3
0216 #define MNG_RESET_NOTIFY_ACK        4
0217 #define MNG_SYNC_FW_CLOCK       5
0218 #define MNG_ILLEGAL_CMD         0xFF
0219
0220 #endif /* _ISHTP_ISH_REGS_H_ */