hid/amd-sfh-hid/amd_sfh_pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * AMD MP2 PCIe communication driver
0004  * Copyright 2020-2021 Advanced Micro Devices, Inc.
0005  *
0006  * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
0007  *      Sandeep Singh <Sandeep.singh@amd.com>
0008  *      Basavaraj Natikar <Basavaraj.Natikar@amd.com>
0009  */
0010
0011 #include <linux/bitops.h>
0012 #include <linux/delay.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/dmi.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io-64-nonatomic-lo-hi.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/module.h>
0019 #include <linux/slab.h>
0020
0021 #include "amd_sfh_pcie.h"
0022 #include "sfh1_1/amd_sfh_init.h"
0023
0024 #define DRIVER_NAME "pcie_mp2_amd"
0025 #define DRIVER_DESC "AMD(R) PCIe MP2 Communication Driver"
0026
0027 #define ACEL_EN     BIT(0)
0028 #define GYRO_EN     BIT(1)
0029 #define MAGNO_EN    BIT(2)
0030 #define HPD_EN      BIT(16)
0031 #define ALS_EN      BIT(19)
0032
0033 static int sensor_mask_override = -1;
0034 module_param_named(sensor_mask, sensor_mask_override, int, 0444);
0035 MODULE_PARM_DESC(sensor_mask, "override the detected sensors mask");
0036
0037 static int amd_sfh_wait_response_v2(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts)
0038 {
0039     union cmd_response cmd_resp;
0040
0041     /* Get response with status within a max of 1600 ms timeout */
0042     if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp,
0043                 (cmd_resp.response_v2.response == sensor_sts &&
0044                 cmd_resp.response_v2.status == 0 && (sid == 0xff ||
0045                 cmd_resp.response_v2.sensor_id == sid)), 500, 1600000))
0046         return cmd_resp.response_v2.response;
0047
0048     return SENSOR_DISABLED;
0049 }
0050
0051 static void amd_start_sensor_v2(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
0052 {
0053     union sfh_cmd_base cmd_base;
0054
0055     cmd_base.ul = 0;
0056     cmd_base.cmd_v2.cmd_id = ENABLE_SENSOR;
0057     cmd_base.cmd_v2.intr_disable = 1;
0058     cmd_base.cmd_v2.period = info.period;
0059     cmd_base.cmd_v2.sensor_id = info.sensor_idx;
0060     cmd_base.cmd_v2.length = 16;
0061
0062     if (info.sensor_idx == als_idx)
0063         cmd_base.cmd_v2.mem_type = USE_C2P_REG;
0064
0065     writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1);
0066     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0067 }
0068
0069 static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx)
0070 {
0071     union sfh_cmd_base cmd_base;
0072
0073     cmd_base.ul = 0;
0074     cmd_base.cmd_v2.cmd_id = DISABLE_SENSOR;
0075     cmd_base.cmd_v2.intr_disable = 1;
0076     cmd_base.cmd_v2.period = 0;
0077     cmd_base.cmd_v2.sensor_id = sensor_idx;
0078     cmd_base.cmd_v2.length  = 16;
0079
0080     writeq(0x0, privdata->mmio + AMD_C2P_MSG1);
0081     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0082 }
0083
0084 static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata)
0085 {
0086     union sfh_cmd_base cmd_base;
0087
0088     cmd_base.cmd_v2.cmd_id = STOP_ALL_SENSORS;
0089     cmd_base.cmd_v2.intr_disable = 1;
0090     cmd_base.cmd_v2.period = 0;
0091     cmd_base.cmd_v2.sensor_id = 0;
0092
0093     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0094 }
0095
0096 void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata)
0097 {
0098     if (readl(privdata->mmio + AMD_P2C_MSG(4))) {
0099         writel(0, privdata->mmio + AMD_P2C_MSG(4));
0100         writel(0xf, privdata->mmio + AMD_P2C_MSG(5));
0101     }
0102 }
0103
0104 void amd_sfh_clear_intr(struct amd_mp2_dev *privdata)
0105 {
0106     if (privdata->mp2_ops->clear_intr)
0107         privdata->mp2_ops->clear_intr(privdata);
0108 }
0109
0110 static irqreturn_t amd_sfh_irq_handler(int irq, void *data)
0111 {
0112     amd_sfh_clear_intr(data);
0113
0114     return IRQ_HANDLED;
0115 }
0116
0117 int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata)
0118 {
0119     int rc;
0120
0121     pci_intx(privdata->pdev, true);
0122
0123     rc = devm_request_irq(&privdata->pdev->dev, privdata->pdev->irq,
0124                   amd_sfh_irq_handler, 0, DRIVER_NAME, privdata);
0125     if (rc) {
0126         dev_err(&privdata->pdev->dev, "failed to request irq %d err=%d\n",
0127             privdata->pdev->irq, rc);
0128         return rc;
0129     }
0130
0131     return 0;
0132 }
0133
0134 static int amd_sfh_dis_sts_v2(struct amd_mp2_dev *privdata)
0135 {
0136     return (readl(privdata->mmio + AMD_P2C_MSG(1)) &
0137               SENSOR_DISCOVERY_STATUS_MASK) >> SENSOR_DISCOVERY_STATUS_SHIFT;
0138 }
0139
0140 static void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
0141 {
0142     union sfh_cmd_param cmd_param;
0143     union sfh_cmd_base cmd_base;
0144
0145     /* fill up command register */
0146     memset(&cmd_base, 0, sizeof(cmd_base));
0147     cmd_base.s.cmd_id = ENABLE_SENSOR;
0148     cmd_base.s.period = info.period;
0149     cmd_base.s.sensor_id = info.sensor_idx;
0150
0151     /* fill up command param register */
0152     memset(&cmd_param, 0, sizeof(cmd_param));
0153     cmd_param.s.buf_layout = 1;
0154     cmd_param.s.buf_length = 16;
0155
0156     writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG2);
0157     writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);
0158     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0159 }
0160
0161 static void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx)
0162 {
0163     union sfh_cmd_base cmd_base;
0164
0165     /* fill up command register */
0166     memset(&cmd_base, 0, sizeof(cmd_base));
0167     cmd_base.s.cmd_id = DISABLE_SENSOR;
0168     cmd_base.s.period = 0;
0169     cmd_base.s.sensor_id = sensor_idx;
0170
0171     writeq(0x0, privdata->mmio + AMD_C2P_MSG2);
0172     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0173 }
0174
0175 static void amd_stop_all_sensors(struct amd_mp2_dev *privdata)
0176 {
0177     union sfh_cmd_base cmd_base;
0178
0179     /* fill up command register */
0180     memset(&cmd_base, 0, sizeof(cmd_base));
0181     cmd_base.s.cmd_id = STOP_ALL_SENSORS;
0182     cmd_base.s.period = 0;
0183     cmd_base.s.sensor_id = 0;
0184
0185     writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
0186 }
0187
0188 static const struct dmi_system_id dmi_sensor_mask_overrides[] = {
0189     {
0190         .matches = {
0191             DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 13-ag0xxx"),
0192         },
0193         .driver_data = (void *)(ACEL_EN | MAGNO_EN),
0194     },
0195     {
0196         .matches = {
0197             DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 15-cp0xxx"),
0198         },
0199         .driver_data = (void *)(ACEL_EN | MAGNO_EN),
0200     },
0201     { }
0202 };
0203
0204 int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id)
0205 {
0206     int activestatus, num_of_sensors = 0;
0207     const struct dmi_system_id *dmi_id;
0208
0209     if (sensor_mask_override == -1) {
0210         dmi_id = dmi_first_match(dmi_sensor_mask_overrides);
0211         if (dmi_id)
0212             sensor_mask_override = (long)dmi_id->driver_data;
0213     }
0214
0215     if (sensor_mask_override >= 0) {
0216         activestatus = sensor_mask_override;
0217     } else {
0218         activestatus = privdata->mp2_acs >> 4;
0219     }
0220
0221     if (ACEL_EN  & activestatus)
0222         sensor_id[num_of_sensors++] = accel_idx;
0223
0224     if (GYRO_EN & activestatus)
0225         sensor_id[num_of_sensors++] = gyro_idx;
0226
0227     if (MAGNO_EN & activestatus)
0228         sensor_id[num_of_sensors++] = mag_idx;
0229
0230     if (ALS_EN & activestatus)
0231         sensor_id[num_of_sensors++] = als_idx;
0232
0233     if (HPD_EN & activestatus)
0234         sensor_id[num_of_sensors++] = HPD_IDX;
0235
0236     return num_of_sensors;
0237 }
0238
0239 static void amd_mp2_pci_remove(void *privdata)
0240 {
0241     struct amd_mp2_dev *mp2 = privdata;
0242     amd_sfh_hid_client_deinit(privdata);
0243     mp2->mp2_ops->stop_all(mp2);
0244     pci_intx(mp2->pdev, false);
0245     amd_sfh_clear_intr(mp2);
0246 }
0247
0248 static struct amd_mp2_ops amd_sfh_ops_v2 = {
0249     .start = amd_start_sensor_v2,
0250     .stop = amd_stop_sensor_v2,
0251     .stop_all = amd_stop_all_sensor_v2,
0252     .response = amd_sfh_wait_response_v2,
0253     .clear_intr = amd_sfh_clear_intr_v2,
0254     .init_intr = amd_sfh_irq_init_v2,
0255     .discovery_status = amd_sfh_dis_sts_v2,
0256     .remove = amd_mp2_pci_remove,
0257 };
0258
0259 static struct amd_mp2_ops amd_sfh_ops = {
0260     .start = amd_start_sensor,
0261     .stop = amd_stop_sensor,
0262     .stop_all = amd_stop_all_sensors,
0263     .remove = amd_mp2_pci_remove,
0264 };
0265
0266 static void mp2_select_ops(struct amd_mp2_dev *privdata)
0267 {
0268     u8 acs;
0269
0270     privdata->mp2_acs = readl(privdata->mmio + AMD_P2C_MSG3);
0271     acs = privdata->mp2_acs & GENMASK(3, 0);
0272
0273     switch (acs) {
0274     case V2_STATUS:
0275         privdata->mp2_ops = &amd_sfh_ops_v2;
0276         break;
0277     default:
0278         privdata->mp2_ops = &amd_sfh_ops;
0279         break;
0280     }
0281 }
0282
0283 int amd_sfh_irq_init(struct amd_mp2_dev *privdata)
0284 {
0285     if (privdata->mp2_ops->init_intr)
0286         return privdata->mp2_ops->init_intr(privdata);
0287
0288     return 0;
0289 }
0290
0291 static const struct dmi_system_id dmi_nodevs[] = {
0292     {
0293         /*
0294          * Google Chromebooks use Chrome OS Embedded Controller Sensor
0295          * Hub instead of Sensor Hub Fusion and leaves MP2
0296          * uninitialized, which disables all functionalities, even
0297          * including the registers necessary for feature detections.
0298          */
0299         .matches = {
0300             DMI_MATCH(DMI_SYS_VENDOR, "Google"),
0301         },
0302     },
0303     { }
0304 };
0305
0306 static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0307 {
0308     struct amd_mp2_dev *privdata;
0309     int rc;
0310
0311     if (dmi_first_match(dmi_nodevs))
0312         return -ENODEV;
0313
0314     privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL);
0315     if (!privdata)
0316         return -ENOMEM;
0317
0318     privdata->pdev = pdev;
0319     dev_set_drvdata(&pdev->dev, privdata);
0320     rc = pcim_enable_device(pdev);
0321     if (rc)
0322         return rc;
0323
0324     rc = pcim_iomap_regions(pdev, BIT(2), DRIVER_NAME);
0325     if (rc)
0326         return rc;
0327
0328     privdata->mmio = pcim_iomap_table(pdev)[2];
0329     pci_set_master(pdev);
0330     rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0331     if (rc) {
0332         dev_err(&pdev->dev, "failed to set DMA mask\n");
0333         return rc;
0334     }
0335
0336     privdata->cl_data = devm_kzalloc(&pdev->dev, sizeof(struct amdtp_cl_data), GFP_KERNEL);
0337     if (!privdata->cl_data)
0338         return -ENOMEM;
0339
0340     privdata->sfh1_1_ops = (const struct amd_sfh1_1_ops *)id->driver_data;
0341     if (privdata->sfh1_1_ops) {
0342         rc = privdata->sfh1_1_ops->init(privdata);
0343         if (rc)
0344             return rc;
0345         goto init_done;
0346     }
0347
0348     mp2_select_ops(privdata);
0349
0350     rc = amd_sfh_irq_init(privdata);
0351     if (rc) {
0352         dev_err(&pdev->dev, "amd_sfh_irq_init failed\n");
0353         return rc;
0354     }
0355
0356     rc = amd_sfh_hid_client_init(privdata);
0357     if (rc) {
0358         amd_sfh_clear_intr(privdata);
0359         if (rc != -EOPNOTSUPP)
0360             dev_err(&pdev->dev, "amd_sfh_hid_client_init failed\n");
0361         return rc;
0362     }
0363
0364 init_done:
0365     amd_sfh_clear_intr(privdata);
0366
0367     return devm_add_action_or_reset(&pdev->dev, privdata->mp2_ops->remove, privdata);
0368 }
0369
0370 static int __maybe_unused amd_mp2_pci_resume(struct device *dev)
0371 {
0372     struct amd_mp2_dev *mp2 = dev_get_drvdata(dev);
0373
0374     mp2->mp2_ops->resume(mp2);
0375
0376     return 0;
0377 }
0378
0379 static int __maybe_unused amd_mp2_pci_suspend(struct device *dev)
0380 {
0381     struct amd_mp2_dev *mp2 = dev_get_drvdata(dev);
0382
0383     mp2->mp2_ops->suspend(mp2);
0384
0385     return 0;
0386 }
0387
0388 static SIMPLE_DEV_PM_OPS(amd_mp2_pm_ops, amd_mp2_pci_suspend,
0389         amd_mp2_pci_resume);
0390
0391 static const struct pci_device_id amd_mp2_pci_tbl[] = {
0392     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2) },
0393     { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2_1_1),
0394       .driver_data = (kernel_ulong_t)&sfh1_1_ops },
0395     { }
0396 };
0397 MODULE_DEVICE_TABLE(pci, amd_mp2_pci_tbl);
0398
0399 static struct pci_driver amd_mp2_pci_driver = {
0400     .name       = DRIVER_NAME,
0401     .id_table   = amd_mp2_pci_tbl,
0402     .probe      = amd_mp2_pci_probe,
0403     .driver.pm  = &amd_mp2_pm_ops,
0404 };
0405 module_pci_driver(amd_mp2_pci_driver);
0406
0407 MODULE_DESCRIPTION(DRIVER_DESC);
0408 MODULE_LICENSE("Dual BSD/GPL");
0409 MODULE_AUTHOR("Shyam Sundar S K <Shyam-sundar.S-k@amd.com>");
0410 MODULE_AUTHOR("Sandeep Singh <Sandeep.singh@amd.com>");
0411 MODULE_AUTHOR("Basavaraj Natikar <Basavaraj.Natikar@amd.com>");