gpu/ipu-v3/ipu-vdi.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2012-2016 Mentor Graphics Inc.
0004  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
0005  */
0006 #include <linux/io.h>
0007 #include "ipu-prv.h"
0008
0009 struct ipu_vdi {
0010     void __iomem *base;
0011     u32 module;
0012     spinlock_t lock;
0013     int use_count;
0014     struct ipu_soc *ipu;
0015 };
0016
0017
0018 /* VDI Register Offsets */
0019 #define VDI_FSIZE 0x0000
0020 #define VDI_C     0x0004
0021
0022 /* VDI Register Fields */
0023 #define VDI_C_CH_420             (0 << 1)
0024 #define VDI_C_CH_422             (1 << 1)
0025 #define VDI_C_MOT_SEL_MASK       (0x3 << 2)
0026 #define VDI_C_MOT_SEL_FULL       (2 << 2)
0027 #define VDI_C_MOT_SEL_LOW        (1 << 2)
0028 #define VDI_C_MOT_SEL_MED        (0 << 2)
0029 #define VDI_C_BURST_SIZE1_4      (3 << 4)
0030 #define VDI_C_BURST_SIZE2_4      (3 << 8)
0031 #define VDI_C_BURST_SIZE3_4      (3 << 12)
0032 #define VDI_C_BURST_SIZE_MASK    0xF
0033 #define VDI_C_BURST_SIZE1_OFFSET 4
0034 #define VDI_C_BURST_SIZE2_OFFSET 8
0035 #define VDI_C_BURST_SIZE3_OFFSET 12
0036 #define VDI_C_VWM1_SET_1         (0 << 16)
0037 #define VDI_C_VWM1_SET_2         (1 << 16)
0038 #define VDI_C_VWM1_CLR_2         (1 << 19)
0039 #define VDI_C_VWM3_SET_1         (0 << 22)
0040 #define VDI_C_VWM3_SET_2         (1 << 22)
0041 #define VDI_C_VWM3_CLR_2         (1 << 25)
0042 #define VDI_C_TOP_FIELD_MAN_1    (1 << 30)
0043 #define VDI_C_TOP_FIELD_AUTO_1   (1 << 31)
0044
0045 static inline u32 ipu_vdi_read(struct ipu_vdi *vdi, unsigned int offset)
0046 {
0047     return readl(vdi->base + offset);
0048 }
0049
0050 static inline void ipu_vdi_write(struct ipu_vdi *vdi, u32 value,
0051                  unsigned int offset)
0052 {
0053     writel(value, vdi->base + offset);
0054 }
0055
0056 void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field)
0057 {
0058     bool top_field_0 = false;
0059     unsigned long flags;
0060     u32 reg;
0061
0062     switch (field) {
0063     case V4L2_FIELD_INTERLACED_TB:
0064     case V4L2_FIELD_SEQ_TB:
0065     case V4L2_FIELD_TOP:
0066         top_field_0 = true;
0067         break;
0068     case V4L2_FIELD_INTERLACED_BT:
0069     case V4L2_FIELD_SEQ_BT:
0070     case V4L2_FIELD_BOTTOM:
0071         top_field_0 = false;
0072         break;
0073     default:
0074         top_field_0 = (std & V4L2_STD_525_60) ? true : false;
0075         break;
0076     }
0077
0078     spin_lock_irqsave(&vdi->lock, flags);
0079
0080     reg = ipu_vdi_read(vdi, VDI_C);
0081     if (top_field_0)
0082         reg &= ~(VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1);
0083     else
0084         reg |= VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1;
0085     ipu_vdi_write(vdi, reg, VDI_C);
0086
0087     spin_unlock_irqrestore(&vdi->lock, flags);
0088 }
0089 EXPORT_SYMBOL_GPL(ipu_vdi_set_field_order);
0090
0091 void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel)
0092 {
0093     unsigned long flags;
0094     u32 reg;
0095
0096     spin_lock_irqsave(&vdi->lock, flags);
0097
0098     reg = ipu_vdi_read(vdi, VDI_C);
0099
0100     reg &= ~VDI_C_MOT_SEL_MASK;
0101
0102     switch (motion_sel) {
0103     case MED_MOTION:
0104         reg |= VDI_C_MOT_SEL_MED;
0105         break;
0106     case HIGH_MOTION:
0107         reg |= VDI_C_MOT_SEL_FULL;
0108         break;
0109     default:
0110         reg |= VDI_C_MOT_SEL_LOW;
0111         break;
0112     }
0113
0114     ipu_vdi_write(vdi, reg, VDI_C);
0115
0116     spin_unlock_irqrestore(&vdi->lock, flags);
0117 }
0118 EXPORT_SYMBOL_GPL(ipu_vdi_set_motion);
0119
0120 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres)
0121 {
0122     unsigned long flags;
0123     u32 pixel_fmt, reg;
0124
0125     spin_lock_irqsave(&vdi->lock, flags);
0126
0127     reg = ((yres - 1) << 16) | (xres - 1);
0128     ipu_vdi_write(vdi, reg, VDI_FSIZE);
0129
0130     /*
0131      * Full motion, only vertical filter is used.
0132      * Burst size is 4 accesses
0133      */
0134     if (code == MEDIA_BUS_FMT_UYVY8_2X8 ||
0135         code == MEDIA_BUS_FMT_UYVY8_1X16 ||
0136         code == MEDIA_BUS_FMT_YUYV8_2X8 ||
0137         code == MEDIA_BUS_FMT_YUYV8_1X16)
0138         pixel_fmt = VDI_C_CH_422;
0139     else
0140         pixel_fmt = VDI_C_CH_420;
0141
0142     reg = ipu_vdi_read(vdi, VDI_C);
0143     reg |= pixel_fmt;
0144     reg |= VDI_C_BURST_SIZE2_4;
0145     reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_CLR_2;
0146     reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_CLR_2;
0147     ipu_vdi_write(vdi, reg, VDI_C);
0148
0149     spin_unlock_irqrestore(&vdi->lock, flags);
0150 }
0151 EXPORT_SYMBOL_GPL(ipu_vdi_setup);
0152
0153 void ipu_vdi_unsetup(struct ipu_vdi *vdi)
0154 {
0155     unsigned long flags;
0156
0157     spin_lock_irqsave(&vdi->lock, flags);
0158     ipu_vdi_write(vdi, 0, VDI_FSIZE);
0159     ipu_vdi_write(vdi, 0, VDI_C);
0160     spin_unlock_irqrestore(&vdi->lock, flags);
0161 }
0162 EXPORT_SYMBOL_GPL(ipu_vdi_unsetup);
0163
0164 int ipu_vdi_enable(struct ipu_vdi *vdi)
0165 {
0166     unsigned long flags;
0167
0168     spin_lock_irqsave(&vdi->lock, flags);
0169
0170     if (!vdi->use_count)
0171         ipu_module_enable(vdi->ipu, vdi->module);
0172
0173     vdi->use_count++;
0174
0175     spin_unlock_irqrestore(&vdi->lock, flags);
0176
0177     return 0;
0178 }
0179 EXPORT_SYMBOL_GPL(ipu_vdi_enable);
0180
0181 int ipu_vdi_disable(struct ipu_vdi *vdi)
0182 {
0183     unsigned long flags;
0184
0185     spin_lock_irqsave(&vdi->lock, flags);
0186
0187     if (vdi->use_count) {
0188         if (!--vdi->use_count)
0189             ipu_module_disable(vdi->ipu, vdi->module);
0190     }
0191
0192     spin_unlock_irqrestore(&vdi->lock, flags);
0193
0194     return 0;
0195 }
0196 EXPORT_SYMBOL_GPL(ipu_vdi_disable);
0197
0198 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu)
0199 {
0200     return ipu->vdi_priv;
0201 }
0202 EXPORT_SYMBOL_GPL(ipu_vdi_get);
0203
0204 void ipu_vdi_put(struct ipu_vdi *vdi)
0205 {
0206 }
0207 EXPORT_SYMBOL_GPL(ipu_vdi_put);
0208
0209 int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
0210          unsigned long base, u32 module)
0211 {
0212     struct ipu_vdi *vdi;
0213
0214     vdi = devm_kzalloc(dev, sizeof(*vdi), GFP_KERNEL);
0215     if (!vdi)
0216         return -ENOMEM;
0217
0218     ipu->vdi_priv = vdi;
0219
0220     spin_lock_init(&vdi->lock);
0221     vdi->module = module;
0222     vdi->base = devm_ioremap(dev, base, PAGE_SIZE);
0223     if (!vdi->base)
0224         return -ENOMEM;
0225
0226     dev_dbg(dev, "VDI base: 0x%08lx remapped to %p\n", base, vdi->base);
0227     vdi->ipu = ipu;
0228
0229     return 0;
0230 }
0231
0232 void ipu_vdi_exit(struct ipu_soc *ipu)
0233 {
0234 }