gpu/ipu-v3/ipu-prv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
0004  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
0005  */
0006 #ifndef __IPU_PRV_H__
0007 #define __IPU_PRV_H__
0008
0009 struct ipu_soc;
0010
0011 #include <linux/types.h>
0012 #include <linux/device.h>
0013 #include <linux/clk.h>
0014 #include <linux/platform_device.h>
0015
0016 #include <video/imx-ipu-v3.h>
0017
0018 #define IPU_MCU_T_DEFAULT   8
0019 #define IPU_CM_IDMAC_REG_OFS    0x00008000
0020 #define IPU_CM_IC_REG_OFS   0x00020000
0021 #define IPU_CM_IRT_REG_OFS  0x00028000
0022 #define IPU_CM_CSI0_REG_OFS 0x00030000
0023 #define IPU_CM_CSI1_REG_OFS 0x00038000
0024 #define IPU_CM_SMFC_REG_OFS 0x00050000
0025 #define IPU_CM_DC_REG_OFS   0x00058000
0026 #define IPU_CM_DMFC_REG_OFS 0x00060000
0027
0028 /* Register addresses */
0029 /* IPU Common registers */
0030 #define IPU_CM_REG(offset)  (offset)
0031
0032 #define IPU_CONF            IPU_CM_REG(0)
0033
0034 #define IPU_SRM_PRI1            IPU_CM_REG(0x00a0)
0035 #define IPU_SRM_PRI2            IPU_CM_REG(0x00a4)
0036 #define IPU_FS_PROC_FLOW1       IPU_CM_REG(0x00a8)
0037 #define IPU_FS_PROC_FLOW2       IPU_CM_REG(0x00ac)
0038 #define IPU_FS_PROC_FLOW3       IPU_CM_REG(0x00b0)
0039 #define IPU_FS_DISP_FLOW1       IPU_CM_REG(0x00b4)
0040 #define IPU_FS_DISP_FLOW2       IPU_CM_REG(0x00b8)
0041 #define IPU_SKIP            IPU_CM_REG(0x00bc)
0042 #define IPU_DISP_ALT_CONF       IPU_CM_REG(0x00c0)
0043 #define IPU_DISP_GEN            IPU_CM_REG(0x00c4)
0044 #define IPU_DISP_ALT1           IPU_CM_REG(0x00c8)
0045 #define IPU_DISP_ALT2           IPU_CM_REG(0x00cc)
0046 #define IPU_DISP_ALT3           IPU_CM_REG(0x00d0)
0047 #define IPU_DISP_ALT4           IPU_CM_REG(0x00d4)
0048 #define IPU_SNOOP           IPU_CM_REG(0x00d8)
0049 #define IPU_MEM_RST         IPU_CM_REG(0x00dc)
0050 #define IPU_PM              IPU_CM_REG(0x00e0)
0051 #define IPU_GPR             IPU_CM_REG(0x00e4)
0052 #define IPU_CHA_DB_MODE_SEL(ch)     IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
0053 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
0054 #define IPU_CHA_CUR_BUF(ch)     IPU_CM_REG(0x023C + 4 * ((ch) / 32))
0055 #define IPU_ALT_CUR_BUF0        IPU_CM_REG(0x0244)
0056 #define IPU_ALT_CUR_BUF1        IPU_CM_REG(0x0248)
0057 #define IPU_SRM_STAT            IPU_CM_REG(0x024C)
0058 #define IPU_PROC_TASK_STAT      IPU_CM_REG(0x0250)
0059 #define IPU_DISP_TASK_STAT      IPU_CM_REG(0x0254)
0060 #define IPU_CHA_BUF0_RDY(ch)        IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
0061 #define IPU_CHA_BUF1_RDY(ch)        IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
0062 #define IPU_CHA_BUF2_RDY(ch)        IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
0063 #define IPU_ALT_CHA_BUF0_RDY(ch)    IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
0064 #define IPU_ALT_CHA_BUF1_RDY(ch)    IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
0065
0066 #define IPU_INT_CTRL(n)     IPU_CM_REG(0x003C + 4 * (n))
0067 #define IPU_INT_STAT(n)     IPU_CM_REG(0x0200 + 4 * (n))
0068
0069 /* SRM_PRI2 */
0070 #define DP_S_SRM_MODE_MASK      (0x3 << 3)
0071 #define DP_S_SRM_MODE_NOW       (0x3 << 3)
0072 #define DP_S_SRM_MODE_NEXT_FRAME    (0x1 << 3)
0073
0074 /* FS_PROC_FLOW1 */
0075 #define FS_PRPENC_ROT_SRC_SEL_MASK  (0xf << 0)
0076 #define FS_PRPENC_ROT_SRC_SEL_ENC       (0x7 << 0)
0077 #define FS_PRPVF_ROT_SRC_SEL_MASK   (0xf << 8)
0078 #define FS_PRPVF_ROT_SRC_SEL_VF         (0x8 << 8)
0079 #define FS_PP_SRC_SEL_MASK      (0xf << 12)
0080 #define FS_PP_ROT_SRC_SEL_MASK      (0xf << 16)
0081 #define FS_PP_ROT_SRC_SEL_PP            (0x5 << 16)
0082 #define FS_VDI1_SRC_SEL_MASK        (0x3 << 20)
0083 #define FS_VDI3_SRC_SEL_MASK        (0x3 << 20)
0084 #define FS_PRP_SRC_SEL_MASK     (0xf << 24)
0085 #define FS_VDI_SRC_SEL_MASK     (0x3 << 28)
0086 #define FS_VDI_SRC_SEL_CSI_DIRECT       (0x1 << 28)
0087 #define FS_VDI_SRC_SEL_VDOA         (0x2 << 28)
0088
0089 /* FS_PROC_FLOW2 */
0090 #define FS_PRP_ENC_DEST_SEL_MASK    (0xf << 0)
0091 #define FS_PRP_ENC_DEST_SEL_IRT_ENC     (0x1 << 0)
0092 #define FS_PRPVF_DEST_SEL_MASK      (0xf << 4)
0093 #define FS_PRPVF_DEST_SEL_IRT_VF        (0x1 << 4)
0094 #define FS_PRPVF_ROT_DEST_SEL_MASK  (0xf << 8)
0095 #define FS_PP_DEST_SEL_MASK     (0xf << 12)
0096 #define FS_PP_DEST_SEL_IRT_PP           (0x3 << 12)
0097 #define FS_PP_ROT_DEST_SEL_MASK     (0xf << 16)
0098 #define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
0099 #define FS_PRP_DEST_SEL_MASK        (0xf << 24)
0100
0101 #define IPU_DI0_COUNTER_RELEASE         (1 << 24)
0102 #define IPU_DI1_COUNTER_RELEASE         (1 << 25)
0103
0104 #define IPU_IDMAC_REG(offset)   (offset)
0105
0106 #define IDMAC_CONF          IPU_IDMAC_REG(0x0000)
0107 #define IDMAC_CHA_EN(ch)        IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
0108 #define IDMAC_SEP_ALPHA         IPU_IDMAC_REG(0x000c)
0109 #define IDMAC_ALT_SEP_ALPHA     IPU_IDMAC_REG(0x0010)
0110 #define IDMAC_CHA_PRI(ch)       IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
0111 #define IDMAC_WM_EN(ch)         IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
0112 #define IDMAC_CH_LOCK_EN_1      IPU_IDMAC_REG(0x0024)
0113 #define IDMAC_CH_LOCK_EN_2      IPU_IDMAC_REG(0x0028)
0114 #define IDMAC_SUB_ADDR_0        IPU_IDMAC_REG(0x002c)
0115 #define IDMAC_SUB_ADDR_1        IPU_IDMAC_REG(0x0030)
0116 #define IDMAC_SUB_ADDR_2        IPU_IDMAC_REG(0x0034)
0117 #define IDMAC_BAND_EN(ch)       IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
0118 #define IDMAC_CHA_BUSY(ch)      IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
0119
0120 #define IPU_NUM_IRQS    (32 * 15)
0121
0122 enum ipu_modules {
0123     IPU_CONF_CSI0_EN        = (1 << 0),
0124     IPU_CONF_CSI1_EN        = (1 << 1),
0125     IPU_CONF_IC_EN          = (1 << 2),
0126     IPU_CONF_ROT_EN         = (1 << 3),
0127     IPU_CONF_ISP_EN         = (1 << 4),
0128     IPU_CONF_DP_EN          = (1 << 5),
0129     IPU_CONF_DI0_EN         = (1 << 6),
0130     IPU_CONF_DI1_EN         = (1 << 7),
0131     IPU_CONF_SMFC_EN        = (1 << 8),
0132     IPU_CONF_DC_EN          = (1 << 9),
0133     IPU_CONF_DMFC_EN        = (1 << 10),
0134
0135     IPU_CONF_VDI_EN         = (1 << 12),
0136
0137     IPU_CONF_IDMAC_DIS      = (1 << 22),
0138
0139     IPU_CONF_IC_DMFC_SEL        = (1 << 25),
0140     IPU_CONF_IC_DMFC_SYNC       = (1 << 26),
0141     IPU_CONF_VDI_DMFC_SYNC      = (1 << 27),
0142
0143     IPU_CONF_CSI0_DATA_SOURCE   = (1 << 28),
0144     IPU_CONF_CSI1_DATA_SOURCE   = (1 << 29),
0145     IPU_CONF_IC_INPUT       = (1 << 30),
0146     IPU_CONF_CSI_SEL        = (1 << 31),
0147 };
0148
0149 struct ipuv3_channel {
0150     unsigned int num;
0151     struct ipu_soc *ipu;
0152     struct list_head list;
0153 };
0154
0155 struct ipu_cpmem;
0156 struct ipu_csi;
0157 struct ipu_dc_priv;
0158 struct ipu_dmfc_priv;
0159 struct ipu_di;
0160 struct ipu_ic_priv;
0161 struct ipu_vdi;
0162 struct ipu_image_convert_priv;
0163 struct ipu_smfc_priv;
0164 struct ipu_pre;
0165 struct ipu_prg;
0166
0167 struct ipu_devtype;
0168
0169 struct ipu_soc {
0170     struct device       *dev;
0171     const struct ipu_devtype    *devtype;
0172     enum ipuv3_type     ipu_type;
0173     spinlock_t      lock;
0174     struct mutex        channel_lock;
0175     struct list_head    channels;
0176
0177     void __iomem        *cm_reg;
0178     void __iomem        *idmac_reg;
0179
0180     int         id;
0181     int         usecount;
0182
0183     struct clk      *clk;
0184
0185     int         irq_sync;
0186     int         irq_err;
0187     struct irq_domain   *domain;
0188
0189     struct ipu_cpmem    *cpmem_priv;
0190     struct ipu_dc_priv  *dc_priv;
0191     struct ipu_dp_priv  *dp_priv;
0192     struct ipu_dmfc_priv    *dmfc_priv;
0193     struct ipu_di       *di_priv[2];
0194     struct ipu_csi      *csi_priv[2];
0195     struct ipu_ic_priv  *ic_priv;
0196     struct ipu_vdi          *vdi_priv;
0197     struct ipu_image_convert_priv *image_convert_priv;
0198     struct ipu_smfc_priv    *smfc_priv;
0199     struct ipu_prg      *prg_priv;
0200 };
0201
0202 static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
0203 {
0204     return readl(ipu->idmac_reg + offset);
0205 }
0206
0207 static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
0208                    unsigned offset)
0209 {
0210     writel(value, ipu->idmac_reg + offset);
0211 }
0212
0213 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
0214
0215 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
0216 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
0217
0218 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
0219
0220 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
0221          unsigned long base, u32 module, struct clk *clk_ipu);
0222 void ipu_csi_exit(struct ipu_soc *ipu, int id);
0223
0224 int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
0225         unsigned long base, unsigned long tpmem_base);
0226 void ipu_ic_exit(struct ipu_soc *ipu);
0227
0228 int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
0229          unsigned long base, u32 module);
0230 void ipu_vdi_exit(struct ipu_soc *ipu);
0231
0232 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
0233 void ipu_image_convert_exit(struct ipu_soc *ipu);
0234
0235 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
0236         unsigned long base, u32 module, struct clk *ipu_clk);
0237 void ipu_di_exit(struct ipu_soc *ipu, int id);
0238
0239 int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
0240         struct clk *ipu_clk);
0241 void ipu_dmfc_exit(struct ipu_soc *ipu);
0242
0243 int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
0244 void ipu_dp_exit(struct ipu_soc *ipu);
0245
0246 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
0247         unsigned long template_base);
0248 void ipu_dc_exit(struct ipu_soc *ipu);
0249
0250 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
0251 void ipu_cpmem_exit(struct ipu_soc *ipu);
0252
0253 int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
0254 void ipu_smfc_exit(struct ipu_soc *ipu);
0255
0256 struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
0257                       int index);
0258 int ipu_pre_get_available_count(void);
0259 int ipu_pre_get(struct ipu_pre *pre);
0260 void ipu_pre_put(struct ipu_pre *pre);
0261 u32 ipu_pre_get_baddr(struct ipu_pre *pre);
0262 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
0263                unsigned int height, unsigned int stride, u32 format,
0264                uint64_t modifier, unsigned int bufaddr);
0265 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
0266 bool ipu_pre_update_pending(struct ipu_pre *pre);
0267
0268 struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
0269                       int ipu_id);
0270
0271 extern struct platform_driver ipu_pre_drv;
0272 extern struct platform_driver ipu_prg_drv;
0273
0274 #endif              /* __IPU_PRV_H__ */