gpu/ipu-v3/ipu-pre.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 Lucas Stach, Pengutronix
0004  */
0005
0006 #include <drm/drm_fourcc.h>
0007 #include <linux/clk.h>
0008 #include <linux/err.h>
0009 #include <linux/genalloc.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <video/imx-ipu-v3.h>
0014
0015 #include "ipu-prv.h"
0016
0017 #define IPU_PRE_MAX_WIDTH   2048
0018 #define IPU_PRE_NUM_SCANLINES   8
0019
0020 #define IPU_PRE_CTRL                    0x000
0021 #define IPU_PRE_CTRL_SET                0x004
0022 #define  IPU_PRE_CTRL_ENABLE                (1 << 0)
0023 #define  IPU_PRE_CTRL_BLOCK_EN              (1 << 1)
0024 #define  IPU_PRE_CTRL_BLOCK_16              (1 << 2)
0025 #define  IPU_PRE_CTRL_SDW_UPDATE            (1 << 4)
0026 #define  IPU_PRE_CTRL_VFLIP             (1 << 5)
0027 #define  IPU_PRE_CTRL_SO                (1 << 6)
0028 #define  IPU_PRE_CTRL_INTERLACED_FIELD          (1 << 7)
0029 #define  IPU_PRE_CTRL_HANDSHAKE_EN          (1 << 8)
0030 #define  IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v)     ((v & 0x3) << 9)
0031 #define  IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN       (1 << 11)
0032 #define  IPU_PRE_CTRL_EN_REPEAT             (1 << 28)
0033 #define  IPU_PRE_CTRL_TPR_REST_SEL          (1 << 29)
0034 #define  IPU_PRE_CTRL_CLKGATE               (1 << 30)
0035 #define  IPU_PRE_CTRL_SFTRST                (1 << 31)
0036
0037 #define IPU_PRE_CUR_BUF                 0x030
0038
0039 #define IPU_PRE_NEXT_BUF                0x040
0040
0041 #define IPU_PRE_TPR_CTRL                0x070
0042 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT(v)        ((v & 0xff) << 0)
0043 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK      0xff
0044 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT        (1 << 0)
0045 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF     (1 << 4)
0046 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF    (1 << 5)
0047 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED   (1 << 6)
0048
0049 #define IPU_PRE_PREFETCH_ENG_CTRL           0x080
0050 #define  IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN      (1 << 0)
0051 #define  IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v)      ((v & 0x7) << 1)
0052 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v)  ((v & 0x3) << 4)
0053 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v)    ((v & 0x7) << 8)
0054 #define  IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS     (1 << 11)
0055 #define  IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE        (1 << 12)
0056 #define  IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP      (1 << 14)
0057 #define  IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN   (1 << 15)
0058
0059 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE         0x0a0
0060 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v)   ((v & 0xffff) << 0)
0061 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v)  ((v & 0xffff) << 16)
0062
0063 #define IPU_PRE_PREFETCH_ENG_PITCH          0x0d0
0064 #define  IPU_PRE_PREFETCH_ENG_PITCH_Y(v)        ((v & 0xffff) << 0)
0065 #define  IPU_PRE_PREFETCH_ENG_PITCH_UV(v)       ((v & 0xffff) << 16)
0066
0067 #define IPU_PRE_STORE_ENG_CTRL              0x110
0068 #define  IPU_PRE_STORE_ENG_CTRL_STORE_EN        (1 << 0)
0069 #define  IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v)     ((v & 0x7) << 1)
0070 #define  IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v)    ((v & 0x3) << 4)
0071
0072 #define IPU_PRE_STORE_ENG_STATUS            0x120
0073 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK    0xffff
0074 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT   0
0075 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK    0x3fff
0076 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT   16
0077 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL   (1 << 30)
0078 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIELD       (1 << 31)
0079
0080 #define IPU_PRE_STORE_ENG_SIZE              0x130
0081 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v)      ((v & 0xffff) << 0)
0082 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v)     ((v & 0xffff) << 16)
0083
0084 #define IPU_PRE_STORE_ENG_PITCH             0x140
0085 #define  IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v)       ((v & 0xffff) << 0)
0086
0087 #define IPU_PRE_STORE_ENG_ADDR              0x150
0088
0089 struct ipu_pre {
0090     struct list_head    list;
0091     struct device       *dev;
0092
0093     void __iomem        *regs;
0094     struct clk      *clk_axi;
0095     struct gen_pool     *iram;
0096
0097     dma_addr_t      buffer_paddr;
0098     void            *buffer_virt;
0099     bool            in_use;
0100     unsigned int        safe_window_end;
0101     unsigned int        last_bufaddr;
0102 };
0103
0104 static DEFINE_MUTEX(ipu_pre_list_mutex);
0105 static LIST_HEAD(ipu_pre_list);
0106 static int available_pres;
0107
0108 int ipu_pre_get_available_count(void)
0109 {
0110     return available_pres;
0111 }
0112
0113 struct ipu_pre *
0114 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
0115 {
0116     struct device_node *pre_node = of_parse_phandle(dev->of_node,
0117                             name, index);
0118     struct ipu_pre *pre;
0119
0120     mutex_lock(&ipu_pre_list_mutex);
0121     list_for_each_entry(pre, &ipu_pre_list, list) {
0122         if (pre_node == pre->dev->of_node) {
0123             mutex_unlock(&ipu_pre_list_mutex);
0124             device_link_add(dev, pre->dev,
0125                     DL_FLAG_AUTOREMOVE_CONSUMER);
0126             of_node_put(pre_node);
0127             return pre;
0128         }
0129     }
0130     mutex_unlock(&ipu_pre_list_mutex);
0131
0132     of_node_put(pre_node);
0133
0134     return NULL;
0135 }
0136
0137 int ipu_pre_get(struct ipu_pre *pre)
0138 {
0139     u32 val;
0140
0141     if (pre->in_use)
0142         return -EBUSY;
0143
0144     /* first get the engine out of reset and remove clock gating */
0145     writel(0, pre->regs + IPU_PRE_CTRL);
0146
0147     /* init defaults that should be applied to all streams */
0148     val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
0149           IPU_PRE_CTRL_HANDSHAKE_EN |
0150           IPU_PRE_CTRL_TPR_REST_SEL |
0151           IPU_PRE_CTRL_SDW_UPDATE;
0152     writel(val, pre->regs + IPU_PRE_CTRL);
0153
0154     pre->in_use = true;
0155     return 0;
0156 }
0157
0158 void ipu_pre_put(struct ipu_pre *pre)
0159 {
0160     writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
0161
0162     pre->in_use = false;
0163 }
0164
0165 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
0166                unsigned int height, unsigned int stride, u32 format,
0167                uint64_t modifier, unsigned int bufaddr)
0168 {
0169     const struct drm_format_info *info = drm_format_info(format);
0170     u32 active_bpp = info->cpp[0] >> 1;
0171     u32 val;
0172
0173     /* calculate safe window for ctrl register updates */
0174     if (modifier == DRM_FORMAT_MOD_LINEAR)
0175         pre->safe_window_end = height - 2;
0176     else
0177         pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
0178
0179     writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
0180     writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
0181     pre->last_bufaddr = bufaddr;
0182
0183     val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
0184           IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
0185           IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
0186           IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
0187           IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
0188     writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
0189
0190     val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
0191           IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
0192     writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
0193
0194     val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
0195     writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
0196
0197     val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
0198           IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
0199           IPU_PRE_STORE_ENG_CTRL_STORE_EN;
0200     writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
0201
0202     val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
0203           IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
0204     writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
0205
0206     val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
0207     writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
0208
0209     writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
0210
0211     val = readl(pre->regs + IPU_PRE_TPR_CTRL);
0212     val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
0213     if (modifier != DRM_FORMAT_MOD_LINEAR) {
0214         /* only support single buffer formats for now */
0215         val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
0216         if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
0217             val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
0218         if (info->cpp[0] == 2)
0219             val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
0220     }
0221     writel(val, pre->regs + IPU_PRE_TPR_CTRL);
0222
0223     val = readl(pre->regs + IPU_PRE_CTRL);
0224     val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
0225            IPU_PRE_CTRL_SDW_UPDATE;
0226     if (modifier == DRM_FORMAT_MOD_LINEAR)
0227         val &= ~IPU_PRE_CTRL_BLOCK_EN;
0228     else
0229         val |= IPU_PRE_CTRL_BLOCK_EN;
0230     writel(val, pre->regs + IPU_PRE_CTRL);
0231 }
0232
0233 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
0234 {
0235     unsigned long timeout = jiffies + msecs_to_jiffies(5);
0236     unsigned short current_yblock;
0237     u32 val;
0238
0239     if (bufaddr == pre->last_bufaddr)
0240         return;
0241
0242     writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
0243     pre->last_bufaddr = bufaddr;
0244
0245     do {
0246         if (time_after(jiffies, timeout)) {
0247             dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
0248             return;
0249         }
0250
0251         val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
0252         current_yblock =
0253             (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
0254             IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
0255     } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
0256
0257     writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
0258 }
0259
0260 bool ipu_pre_update_pending(struct ipu_pre *pre)
0261 {
0262     return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
0263           IPU_PRE_CTRL_SDW_UPDATE);
0264 }
0265
0266 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
0267 {
0268     return (u32)pre->buffer_paddr;
0269 }
0270
0271 static int ipu_pre_probe(struct platform_device *pdev)
0272 {
0273     struct device *dev = &pdev->dev;
0274     struct resource *res;
0275     struct ipu_pre *pre;
0276
0277     pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
0278     if (!pre)
0279         return -ENOMEM;
0280
0281     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0282     pre->regs = devm_ioremap_resource(&pdev->dev, res);
0283     if (IS_ERR(pre->regs))
0284         return PTR_ERR(pre->regs);
0285
0286     pre->clk_axi = devm_clk_get(dev, "axi");
0287     if (IS_ERR(pre->clk_axi))
0288         return PTR_ERR(pre->clk_axi);
0289
0290     pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
0291     if (!pre->iram)
0292         return -EPROBE_DEFER;
0293
0294     /*
0295      * Allocate IRAM buffer with maximum size. This could be made dynamic,
0296      * but as there is no other user of this IRAM region and we can fit all
0297      * max sized buffers into it, there is no need yet.
0298      */
0299     pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
0300                           IPU_PRE_NUM_SCANLINES * 4,
0301                           &pre->buffer_paddr);
0302     if (!pre->buffer_virt)
0303         return -ENOMEM;
0304
0305     clk_prepare_enable(pre->clk_axi);
0306
0307     pre->dev = dev;
0308     platform_set_drvdata(pdev, pre);
0309     mutex_lock(&ipu_pre_list_mutex);
0310     list_add(&pre->list, &ipu_pre_list);
0311     available_pres++;
0312     mutex_unlock(&ipu_pre_list_mutex);
0313
0314     return 0;
0315 }
0316
0317 static int ipu_pre_remove(struct platform_device *pdev)
0318 {
0319     struct ipu_pre *pre = platform_get_drvdata(pdev);
0320
0321     mutex_lock(&ipu_pre_list_mutex);
0322     list_del(&pre->list);
0323     available_pres--;
0324     mutex_unlock(&ipu_pre_list_mutex);
0325
0326     clk_disable_unprepare(pre->clk_axi);
0327
0328     if (pre->buffer_virt)
0329         gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
0330                   IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
0331     return 0;
0332 }
0333
0334 static const struct of_device_id ipu_pre_dt_ids[] = {
0335     { .compatible = "fsl,imx6qp-pre", },
0336     { /* sentinel */ },
0337 };
0338
0339 struct platform_driver ipu_pre_drv = {
0340     .probe      = ipu_pre_probe,
0341     .remove     = ipu_pre_remove,
0342     .driver     = {
0343         .name   = "imx-ipu-pre",
0344         .of_match_table = ipu_pre_dt_ids,
0345     },
0346 };