gpu/host1x/mipi.c

0001 /*
0002  * Copyright (C) 2013 NVIDIA Corporation
0003  *
0004  * Permission to use, copy, modify, distribute, and sell this software and its
0005  * documentation for any purpose is hereby granted without fee, provided that
0006  * the above copyright notice appear in all copies and that both that copyright
0007  * notice and this permission notice appear in supporting documentation, and
0008  * that the name of the copyright holders not be used in advertising or
0009  * publicity pertaining to distribution of the software without specific,
0010  * written prior permission.  The copyright holders make no representations
0011  * about the suitability of this software for any purpose.  It is provided "as
0012  * is" without express or implied warranty.
0013  *
0014  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
0015  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
0016  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
0017  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
0018  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
0019  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
0020  * OF THIS SOFTWARE.
0021  */
0022
0023 #include <linux/clk.h>
0024 #include <linux/host1x.h>
0025 #include <linux/io.h>
0026 #include <linux/iopoll.h>
0027 #include <linux/of_platform.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/slab.h>
0030
0031 #include "dev.h"
0032
0033 #define MIPI_CAL_CTRL           0x00
0034 #define MIPI_CAL_CTRL_NOISE_FILTER(x)   (((x) & 0xf) << 26)
0035 #define MIPI_CAL_CTRL_PRESCALE(x)   (((x) & 0x3) << 24)
0036 #define MIPI_CAL_CTRL_CLKEN_OVR     (1 << 4)
0037 #define MIPI_CAL_CTRL_START     (1 << 0)
0038
0039 #define MIPI_CAL_AUTOCAL_CTRL       0x01
0040
0041 #define MIPI_CAL_STATUS         0x02
0042 #define MIPI_CAL_STATUS_DONE        (1 << 16)
0043 #define MIPI_CAL_STATUS_ACTIVE      (1 <<  0)
0044
0045 #define MIPI_CAL_CONFIG_CSIA        0x05
0046 #define MIPI_CAL_CONFIG_CSIB        0x06
0047 #define MIPI_CAL_CONFIG_CSIC        0x07
0048 #define MIPI_CAL_CONFIG_CSID        0x08
0049 #define MIPI_CAL_CONFIG_CSIE        0x09
0050 #define MIPI_CAL_CONFIG_CSIF        0x0a
0051 #define MIPI_CAL_CONFIG_DSIA        0x0e
0052 #define MIPI_CAL_CONFIG_DSIB        0x0f
0053 #define MIPI_CAL_CONFIG_DSIC        0x10
0054 #define MIPI_CAL_CONFIG_DSID        0x11
0055
0056 #define MIPI_CAL_CONFIG_DSIA_CLK    0x19
0057 #define MIPI_CAL_CONFIG_DSIB_CLK    0x1a
0058 #define MIPI_CAL_CONFIG_CSIAB_CLK   0x1b
0059 #define MIPI_CAL_CONFIG_DSIC_CLK    0x1c
0060 #define MIPI_CAL_CONFIG_CSICD_CLK   0x1c
0061 #define MIPI_CAL_CONFIG_DSID_CLK    0x1d
0062 #define MIPI_CAL_CONFIG_CSIE_CLK    0x1d
0063
0064 /* for data and clock lanes */
0065 #define MIPI_CAL_CONFIG_SELECT      (1 << 21)
0066
0067 /* for data lanes */
0068 #define MIPI_CAL_CONFIG_HSPDOS(x)   (((x) & 0x1f) << 16)
0069 #define MIPI_CAL_CONFIG_HSPUOS(x)   (((x) & 0x1f) <<  8)
0070 #define MIPI_CAL_CONFIG_TERMOS(x)   (((x) & 0x1f) <<  0)
0071
0072 /* for clock lanes */
0073 #define MIPI_CAL_CONFIG_HSCLKPDOSD(x)   (((x) & 0x1f) <<  8)
0074 #define MIPI_CAL_CONFIG_HSCLKPUOSD(x)   (((x) & 0x1f) <<  0)
0075
0076 #define MIPI_CAL_BIAS_PAD_CFG0      0x16
0077 #define MIPI_CAL_BIAS_PAD_PDVCLAMP  (1 << 1)
0078 #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF  (1 << 0)
0079
0080 #define MIPI_CAL_BIAS_PAD_CFG1      0x17
0081 #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
0082 #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
0083
0084 #define MIPI_CAL_BIAS_PAD_CFG2      0x18
0085 #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
0086 #define MIPI_CAL_BIAS_PAD_VAUXP(x)  (((x) & 0x7) << 4)
0087 #define MIPI_CAL_BIAS_PAD_PDVREG    (1 << 1)
0088
0089 struct tegra_mipi_pad {
0090     unsigned long data;
0091     unsigned long clk;
0092 };
0093
0094 struct tegra_mipi_soc {
0095     bool has_clk_lane;
0096     const struct tegra_mipi_pad *pads;
0097     unsigned int num_pads;
0098
0099     bool clock_enable_override;
0100     bool needs_vclamp_ref;
0101
0102     /* bias pad configuration settings */
0103     u8 pad_drive_down_ref;
0104     u8 pad_drive_up_ref;
0105
0106     u8 pad_vclamp_level;
0107     u8 pad_vauxp_level;
0108
0109     /* calibration settings for data lanes */
0110     u8 hspdos;
0111     u8 hspuos;
0112     u8 termos;
0113
0114     /* calibration settings for clock lanes */
0115     u8 hsclkpdos;
0116     u8 hsclkpuos;
0117 };
0118
0119 struct tegra_mipi {
0120     const struct tegra_mipi_soc *soc;
0121     struct device *dev;
0122     void __iomem *regs;
0123     struct mutex lock;
0124     struct clk *clk;
0125
0126     unsigned long usage_count;
0127 };
0128
0129 struct tegra_mipi_device {
0130     struct platform_device *pdev;
0131     struct tegra_mipi *mipi;
0132     struct device *device;
0133     unsigned long pads;
0134 };
0135
0136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
0137                    unsigned long offset)
0138 {
0139     return readl(mipi->regs + (offset << 2));
0140 }
0141
0142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
0143                      unsigned long offset)
0144 {
0145     writel(value, mipi->regs + (offset << 2));
0146 }
0147
0148 static int tegra_mipi_power_up(struct tegra_mipi *mipi)
0149 {
0150     u32 value;
0151     int err;
0152
0153     err = clk_enable(mipi->clk);
0154     if (err < 0)
0155         return err;
0156
0157     value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
0158     value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
0159
0160     if (mipi->soc->needs_vclamp_ref)
0161         value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
0162
0163     tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
0164
0165     value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
0166     value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
0167     tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
0168
0169     clk_disable(mipi->clk);
0170
0171     return 0;
0172 }
0173
0174 static int tegra_mipi_power_down(struct tegra_mipi *mipi)
0175 {
0176     u32 value;
0177     int err;
0178
0179     err = clk_enable(mipi->clk);
0180     if (err < 0)
0181         return err;
0182
0183     /*
0184      * The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
0185      * supplies the DSI pads. This must be kept enabled until none of the
0186      * DSI lanes are used anymore.
0187      */
0188     value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
0189     value |= MIPI_CAL_BIAS_PAD_PDVREG;
0190     tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
0191
0192     /*
0193      * MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
0194      * control a regulator that supplies current to the pre-driver logic.
0195      * Powering down this regulator causes DSI to fail, so it must remain
0196      * powered on until none of the DSI lanes are used anymore.
0197      */
0198     value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
0199
0200     if (mipi->soc->needs_vclamp_ref)
0201         value &= ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
0202
0203     value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
0204     tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
0205
0206     return 0;
0207 }
0208
0209 struct tegra_mipi_device *tegra_mipi_request(struct device *device,
0210                          struct device_node *np)
0211 {
0212     struct tegra_mipi_device *dev;
0213     struct of_phandle_args args;
0214     int err;
0215
0216     err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
0217                      "#nvidia,mipi-calibrate-cells", 0,
0218                      &args);
0219     if (err < 0)
0220         return ERR_PTR(err);
0221
0222     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0223     if (!dev) {
0224         err = -ENOMEM;
0225         goto out;
0226     }
0227
0228     dev->pdev = of_find_device_by_node(args.np);
0229     if (!dev->pdev) {
0230         err = -ENODEV;
0231         goto free;
0232     }
0233
0234     dev->mipi = platform_get_drvdata(dev->pdev);
0235     if (!dev->mipi) {
0236         err = -EPROBE_DEFER;
0237         goto put;
0238     }
0239
0240     of_node_put(args.np);
0241
0242     dev->pads = args.args[0];
0243     dev->device = device;
0244
0245     return dev;
0246
0247 put:
0248     platform_device_put(dev->pdev);
0249 free:
0250     kfree(dev);
0251 out:
0252     of_node_put(args.np);
0253     return ERR_PTR(err);
0254 }
0255 EXPORT_SYMBOL(tegra_mipi_request);
0256
0257 void tegra_mipi_free(struct tegra_mipi_device *device)
0258 {
0259     platform_device_put(device->pdev);
0260     kfree(device);
0261 }
0262 EXPORT_SYMBOL(tegra_mipi_free);
0263
0264 int tegra_mipi_enable(struct tegra_mipi_device *dev)
0265 {
0266     int err = 0;
0267
0268     mutex_lock(&dev->mipi->lock);
0269
0270     if (dev->mipi->usage_count++ == 0)
0271         err = tegra_mipi_power_up(dev->mipi);
0272
0273     mutex_unlock(&dev->mipi->lock);
0274
0275     return err;
0276
0277 }
0278 EXPORT_SYMBOL(tegra_mipi_enable);
0279
0280 int tegra_mipi_disable(struct tegra_mipi_device *dev)
0281 {
0282     int err = 0;
0283
0284     mutex_lock(&dev->mipi->lock);
0285
0286     if (--dev->mipi->usage_count == 0)
0287         err = tegra_mipi_power_down(dev->mipi);
0288
0289     mutex_unlock(&dev->mipi->lock);
0290
0291     return err;
0292
0293 }
0294 EXPORT_SYMBOL(tegra_mipi_disable);
0295
0296 int tegra_mipi_finish_calibration(struct tegra_mipi_device *device)
0297 {
0298     struct tegra_mipi *mipi = device->mipi;
0299     void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2);
0300     u32 value;
0301     int err;
0302
0303     err = readl_relaxed_poll_timeout(status_reg, value,
0304                      !(value & MIPI_CAL_STATUS_ACTIVE) &&
0305                      (value & MIPI_CAL_STATUS_DONE), 50,
0306                      250000);
0307     mutex_unlock(&device->mipi->lock);
0308     clk_disable(device->mipi->clk);
0309
0310     return err;
0311 }
0312 EXPORT_SYMBOL(tegra_mipi_finish_calibration);
0313
0314 int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
0315 {
0316     const struct tegra_mipi_soc *soc = device->mipi->soc;
0317     unsigned int i;
0318     u32 value;
0319     int err;
0320
0321     err = clk_enable(device->mipi->clk);
0322     if (err < 0)
0323         return err;
0324
0325     mutex_lock(&device->mipi->lock);
0326
0327     value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
0328         MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
0329     tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
0330
0331     value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
0332     value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
0333     value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
0334     value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
0335     value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
0336     tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
0337
0338     for (i = 0; i < soc->num_pads; i++) {
0339         u32 clk = 0, data = 0;
0340
0341         if (device->pads & BIT(i)) {
0342             data = MIPI_CAL_CONFIG_SELECT |
0343                    MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
0344                    MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
0345                    MIPI_CAL_CONFIG_TERMOS(soc->termos);
0346             clk = MIPI_CAL_CONFIG_SELECT |
0347                   MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
0348                   MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
0349         }
0350
0351         tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
0352
0353         if (soc->has_clk_lane && soc->pads[i].clk != 0)
0354             tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
0355     }
0356
0357     value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
0358     value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
0359     value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
0360     value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
0361     value |= MIPI_CAL_CTRL_PRESCALE(0x2);
0362
0363     if (!soc->clock_enable_override)
0364         value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
0365     else
0366         value |= MIPI_CAL_CTRL_CLKEN_OVR;
0367
0368     tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
0369
0370     /* clear any pending status bits */
0371     value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
0372     tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
0373
0374     value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
0375     value |= MIPI_CAL_CTRL_START;
0376     tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
0377
0378     /*
0379      * Wait for min 72uS to let calibration logic finish calibration
0380      * sequence codes before waiting for pads idle state to apply the
0381      * results.
0382      */
0383     usleep_range(75, 80);
0384
0385     return 0;
0386 }
0387 EXPORT_SYMBOL(tegra_mipi_start_calibration);
0388
0389 static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
0390     { .data = MIPI_CAL_CONFIG_CSIA },
0391     { .data = MIPI_CAL_CONFIG_CSIB },
0392     { .data = MIPI_CAL_CONFIG_CSIC },
0393     { .data = MIPI_CAL_CONFIG_CSID },
0394     { .data = MIPI_CAL_CONFIG_CSIE },
0395     { .data = MIPI_CAL_CONFIG_DSIA },
0396     { .data = MIPI_CAL_CONFIG_DSIB },
0397     { .data = MIPI_CAL_CONFIG_DSIC },
0398     { .data = MIPI_CAL_CONFIG_DSID },
0399 };
0400
0401 static const struct tegra_mipi_soc tegra114_mipi_soc = {
0402     .has_clk_lane = false,
0403     .pads = tegra114_mipi_pads,
0404     .num_pads = ARRAY_SIZE(tegra114_mipi_pads),
0405     .clock_enable_override = true,
0406     .needs_vclamp_ref = true,
0407     .pad_drive_down_ref = 0x2,
0408     .pad_drive_up_ref = 0x0,
0409     .pad_vclamp_level = 0x0,
0410     .pad_vauxp_level = 0x0,
0411     .hspdos = 0x0,
0412     .hspuos = 0x4,
0413     .termos = 0x5,
0414     .hsclkpdos = 0x0,
0415     .hsclkpuos = 0x4,
0416 };
0417
0418 static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
0419     { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
0420     { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
0421     { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
0422     { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
0423     { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK  },
0424     { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK  },
0425     { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK  },
0426 };
0427
0428 static const struct tegra_mipi_soc tegra124_mipi_soc = {
0429     .has_clk_lane = true,
0430     .pads = tegra124_mipi_pads,
0431     .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
0432     .clock_enable_override = true,
0433     .needs_vclamp_ref = true,
0434     .pad_drive_down_ref = 0x2,
0435     .pad_drive_up_ref = 0x0,
0436     .pad_vclamp_level = 0x0,
0437     .pad_vauxp_level = 0x0,
0438     .hspdos = 0x0,
0439     .hspuos = 0x0,
0440     .termos = 0x0,
0441     .hsclkpdos = 0x1,
0442     .hsclkpuos = 0x2,
0443 };
0444
0445 static const struct tegra_mipi_soc tegra132_mipi_soc = {
0446     .has_clk_lane = true,
0447     .pads = tegra124_mipi_pads,
0448     .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
0449     .clock_enable_override = false,
0450     .needs_vclamp_ref = false,
0451     .pad_drive_down_ref = 0x0,
0452     .pad_drive_up_ref = 0x3,
0453     .pad_vclamp_level = 0x0,
0454     .pad_vauxp_level = 0x0,
0455     .hspdos = 0x0,
0456     .hspuos = 0x0,
0457     .termos = 0x0,
0458     .hsclkpdos = 0x3,
0459     .hsclkpuos = 0x2,
0460 };
0461
0462 static const struct tegra_mipi_pad tegra210_mipi_pads[] = {
0463     { .data = MIPI_CAL_CONFIG_CSIA, .clk = 0 },
0464     { .data = MIPI_CAL_CONFIG_CSIB, .clk = 0 },
0465     { .data = MIPI_CAL_CONFIG_CSIC, .clk = 0 },
0466     { .data = MIPI_CAL_CONFIG_CSID, .clk = 0 },
0467     { .data = MIPI_CAL_CONFIG_CSIE, .clk = 0 },
0468     { .data = MIPI_CAL_CONFIG_CSIF, .clk = 0 },
0469     { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
0470     { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
0471     { .data = MIPI_CAL_CONFIG_DSIC, .clk = MIPI_CAL_CONFIG_DSIC_CLK },
0472     { .data = MIPI_CAL_CONFIG_DSID, .clk = MIPI_CAL_CONFIG_DSID_CLK },
0473 };
0474
0475 static const struct tegra_mipi_soc tegra210_mipi_soc = {
0476     .has_clk_lane = true,
0477     .pads = tegra210_mipi_pads,
0478     .num_pads = ARRAY_SIZE(tegra210_mipi_pads),
0479     .clock_enable_override = true,
0480     .needs_vclamp_ref = false,
0481     .pad_drive_down_ref = 0x0,
0482     .pad_drive_up_ref = 0x3,
0483     .pad_vclamp_level = 0x1,
0484     .pad_vauxp_level = 0x1,
0485     .hspdos = 0x0,
0486     .hspuos = 0x2,
0487     .termos = 0x0,
0488     .hsclkpdos = 0x0,
0489     .hsclkpuos = 0x2,
0490 };
0491
0492 static const struct of_device_id tegra_mipi_of_match[] = {
0493     { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
0494     { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
0495     { .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc },
0496     { .compatible = "nvidia,tegra210-mipi", .data = &tegra210_mipi_soc },
0497     { },
0498 };
0499
0500 static int tegra_mipi_probe(struct platform_device *pdev)
0501 {
0502     const struct of_device_id *match;
0503     struct tegra_mipi *mipi;
0504     struct resource *res;
0505     int err;
0506
0507     match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
0508     if (!match)
0509         return -ENODEV;
0510
0511     mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
0512     if (!mipi)
0513         return -ENOMEM;
0514
0515     mipi->soc = match->data;
0516     mipi->dev = &pdev->dev;
0517
0518     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0519     mipi->regs = devm_ioremap_resource(&pdev->dev, res);
0520     if (IS_ERR(mipi->regs))
0521         return PTR_ERR(mipi->regs);
0522
0523     mutex_init(&mipi->lock);
0524
0525     mipi->clk = devm_clk_get(&pdev->dev, NULL);
0526     if (IS_ERR(mipi->clk)) {
0527         dev_err(&pdev->dev, "failed to get clock\n");
0528         return PTR_ERR(mipi->clk);
0529     }
0530
0531     err = clk_prepare(mipi->clk);
0532     if (err < 0)
0533         return err;
0534
0535     platform_set_drvdata(pdev, mipi);
0536
0537     return 0;
0538 }
0539
0540 static int tegra_mipi_remove(struct platform_device *pdev)
0541 {
0542     struct tegra_mipi *mipi = platform_get_drvdata(pdev);
0543
0544     clk_unprepare(mipi->clk);
0545
0546     return 0;
0547 }
0548
0549 struct platform_driver tegra_mipi_driver = {
0550     .driver = {
0551         .name = "tegra-mipi",
0552         .of_match_table = tegra_mipi_of_match,
0553     },
0554     .probe = tegra_mipi_probe,
0555     .remove = tegra_mipi_remove,
0556 };